Lets keep this thread on the subject of the 970, please. There is another thread for the completely unsubstantiated rumors about AMD & Apple. This thread should remain true to its title: Apple will be using the new IBM PPC 970 sometime around the middle of next year.
It'll be interesting to see Hannibal's next article if he's actually talking to the guys at IBM -- I think his last article was a little off the mark and missed some important features of the 970's design.
When Apple released the FP iMacs they did not reach wide circulation untill the end of March, with only the most expensive model available at first, and people waiting a fair bit before they got those. Clearly they weren't ready yet, but Apple had nothing else and needed to do something, so they did more of a pre-announcement disguised as a semi-release. I think they may do that again here. ANd it may take as long as 3 months before anyone gets to use a PPC970 based Mac, and mebbe a touch more than that, but it's better to have 50-100K macs "on-order" by April than have another round of well deserved griping about the state of the G4 (unless the state of the G4 can be radically improved.) If IBM can help in this regard, I think they will. March/April to H2 isn't that far, no one will complain about IBM beating their own forecasts, everyone comes out smelling like roses. I didn't mean you would get a PPC970 Powermac at MWSF, at least not get to take one home, just that you'd get to see one and place an order for it. It's firmly possible that what I describe may transpire, reports are IBM has been at it for a long while and that Apple has been waiting in anticipation for a fair bit too.
Steve doesn't enjoy putting on a shitty keynote. He's been able to taste the disapointment on a few occassions over the last two years, and as much as Apple may want to get away from keynote releases, they need a big keynote in a big way. That's a Wintel annihilating PPC970 away, unless another digital device is making its paces around the Infinite Loop...
It'll be interesting to see Hannibal's next article if he's actually talking to the guys at IBM -- I think his last article was a little off the mark and missed some important features of the 970's design.</strong><hr></blockquote>
Could you elaborate on that a bit more Programmer? While I thought his article was incomplete, I didn't think it was "off the mark" as you put it. Was there something patently wrong in the write-up? Personally, I don't remember anything glaringly obvious, but it has been several weeks since I read the article, and I am too lazy to go back and re-read it.
Could you elaborate on that a bit more Programmer? While I thought his article was incomplete, I didn't think it was "off the mark" as you put it. Was there something patently wrong in the write-up? Personally, I don't remember anything glaringly obvious, but it has been several weeks since I read the article, and I am too lazy to go back and re-read it.
</strong><hr></blockquote>
I disagree with some of his subjective analysis is all.
Can someone explain to me how the regular P4 can beat the P4 Xeon in both SPECint and SPECfp? And it's by no small margin either.</strong><hr></blockquote>
The Xeon is 1) designed for use in boxes with more SMP going on, and 2) higher reliability.
1: You _can_ make any chip in an insanely SMP box - but it is a LOT easier and cheaper if the chip itself is designed with that in mind. I don't hear about many 8 CPU P4 boxes. You do (or can) hear about 8 way Xeons. (Although you might need to wade through a lot of gobbledygook and deal with a smarmy salesman or two to find that out). This is different than a 'blade server' with 8 P4s in it - those are more like 8 'individual' computers slammed into one box. But adding extra complexity to the chip means less room for speed improvements -> slower at precisely the same transistor count.
2: The boxes the Xeon (or the full Power4) is targeted at are a little more mission-critical than a 5-man department's file server. By making the physical traces on the CPU slightly heftier, the failure rate of the chips can be significantly lower. I don't have any idea what the numbers are, but something like this: By sacrificing 50% in speed (thicker wires -> more heat -> slower) getting the chance of failure in the next year or two to drop 10-fold. Or 100-fold. I'd expect any random Xeon or Power4 that passed to last awhile even after running full tilt for 4 years. Straight.
The part about the ppc970 that has me excited are the various comments reported as coming from IBM that indicate the 970 is 'designed with SMP in mind'. The best attribution I can turn up mentioned 8-way SMP.
If Apple did ever release an 8-way, Matsu could change his .sig to 'Bumping prices AND specs'
Programmer, with respect to your comments about the Article keyed by Hannibal, I think you might be referring to a few things that a trusted contact and CPU designer elaborated on a few weeks back when the ArsTech article first came out.
Let is also be know that this individual doesn't frequent Ars, particularly because he doesn't care for the site all that much. He prefers RealWorldTech, but that's neither here nor there...
Anyway here is what he had to saw about Hannibal's article (as well as the article that followed, the one written by friend, David K. Every over at igeek.com)
<begin reply>
[[[ Hey, thanks for that link. I used to read his MacKiDo site quite often, was sorry to see him shut it down a while back and didn't know he was writing again. Nice.
However, as far as this article goes I really think he kind of missed the point. David does make a good point in the vector section, but it is unfair to the Ars article because Hannibal clearly says that he will cover the execution core (which would include vector execution) in part two (we'll see).
Hannibal's article has a few inaccuracies (which I'll touch on a little below), but I respect the fact that he seems to have spent some time actually researching info on Power4 and others. David's article also has some problems (particularly the branch and IPC sections).
As far as the Ars link you sent me previously, I think that some of his comparisons are unfair inasmuch as they are comparing currently shipping Intel and Moto parts to an IBM part that is ~1 year away. Both Intel and Moto will have better parts by then, the Moto G4e design in particular will compare better in some stats when they have a .13um part to compare to Intel and IBM's 0.13um parts.
The Ars article also contains a few factual errors ... for example the repeated point Hannibal makes comparing 200 vs 126 inflight instructions is not actually comparing the same things (and I don't mean the difference between x86 and PPC).
David's article makes the same mistake though. People on the net keep complaining that we know that P4 has 12K-uop cache and G4e is 32KB and 970 is 64KB, and keep whining about not knowing the size of the uop. Big deal, it can be normed another way. PPC instructions are 32-bit instructions, which means that G4e holds 8K-instructions, and 970 holds 16K-instructions. So P4 is in the middle of that ... albeit trace-cache
versus instruction cache also throws in another level of complexity ...
I also don't think the branch prediction section is fully accurate either, but I can't go into details on that ... In general, the Ars tech article is a decent article with some solid research, and a few sour notes that should have been corrected. However, this is only part 1 of a 3 part article.]]] - anonymous source <end reply>
If the PPC970 is coming out at MWSF this could explain why Woz is going to be there. It would actually make a lot of since for apple to do a early release of the 970. I agree with Matsu in thinking that this is a strong possibility.
<strong>Programmer, with respect to your comments about the Article keyed by Hannibal, I think you might be referring to a few things that a trusted contact and CPU designer elaborated on a few weeks back when the ArsTech article first came out.</strong><hr></blockquote>
Your friend looks like he knows what he's talking about. I wasn't too impressed with Every's article either -- it seemed reactionary and had many inaccuracies. Hannibal was in general more accurate on the facts, but drew conclusions that I feel are a little suspect.
A while back, I believe Moki referred to some company as 'sandbagging'. As I recall, the subject was IBM and their 970 chip announcement. Could this mean IBM has something to help Apple during the first-half of 2003? Any thoughts?
thicker wires actually reduces resistance, and thereby heat. What makes a circuit produced on a larger process slower is mostly the increased capacitance due to larger features, and to some extent, the greater distance between transistors.
Moki please come back. We need some real information on this BB. It seems that no one really does have a clue about when we can expect the 970 to be announced by Apple. You must have some idea what the target date is beyond the end of 2003.
<strong>Moki please come back. We need some real information on this BB. It seems that no one really does have a clue about when we can expect the 970 to be announced by Apple. You must have some idea what the target date is beyond the end of 2003.
Without compromising any NDAs. </strong><hr></blockquote>
What?! First of all, we all have a clue if we stop daydreaming for a collective minute -- second half '03. How many times does this have to be repeated? This is not the same thing as "end of 2003" either.
What?! First of all, we all have a clue if we stop daydreaming for a collective minute -- second half '03. How many times does this have to be repeated? This is not the same thing as "end of 2003" either.</strong><hr></blockquote>
Sorry Programmer, didn't mean to sound so pessimistic. But if things were no repeated on this forum, the total posting count would be about a tenth of what it is.
Do any of you think the flat panel iMac will get a new processor in 2003, or will it keep the G4 with speedbump(s) for all of next year? Is all the talk about the new processor(s) to come for just the tower units in 2003? Thanks for the input....
Comments
It'll be interesting to see Hannibal's next article if he's actually talking to the guys at IBM -- I think his last article was a little off the mark and missed some important features of the 970's design.
When Apple released the FP iMacs they did not reach wide circulation untill the end of March, with only the most expensive model available at first, and people waiting a fair bit before they got those. Clearly they weren't ready yet, but Apple had nothing else and needed to do something, so they did more of a pre-announcement disguised as a semi-release. I think they may do that again here. ANd it may take as long as 3 months before anyone gets to use a PPC970 based Mac, and mebbe a touch more than that, but it's better to have 50-100K macs "on-order" by April than have another round of well deserved griping about the state of the G4 (unless the state of the G4 can be radically improved.) If IBM can help in this regard, I think they will. March/April to H2 isn't that far, no one will complain about IBM beating their own forecasts, everyone comes out smelling like roses. I didn't mean you would get a PPC970 Powermac at MWSF, at least not get to take one home, just that you'd get to see one and place an order for it. It's firmly possible that what I describe may transpire, reports are IBM has been at it for a long while and that Apple has been waiting in anticipation for a fair bit too.
Steve doesn't enjoy putting on a shitty keynote. He's been able to taste the disapointment on a few occassions over the last two years, and as much as Apple may want to get away from keynote releases, they need a big keynote in a big way. That's a Wintel annihilating PPC970 away, unless another digital device is making its paces around the Infinite Loop...
<strong>
It'll be interesting to see Hannibal's next article if he's actually talking to the guys at IBM -- I think his last article was a little off the mark and missed some important features of the 970's design.</strong><hr></blockquote>
Could you elaborate on that a bit more Programmer? While I thought his article was incomplete, I didn't think it was "off the mark" as you put it. Was there something patently wrong in the write-up? Personally, I don't remember anything glaringly obvious, but it has been several weeks since I read the article, and I am too lazy to go back and re-read it.
Cheers!
<strong>
Could you elaborate on that a bit more Programmer? While I thought his article was incomplete, I didn't think it was "off the mark" as you put it. Was there something patently wrong in the write-up? Personally, I don't remember anything glaringly obvious, but it has been several weeks since I read the article, and I am too lazy to go back and re-read it.
</strong><hr></blockquote>
I disagree with some of his subjective analysis is all.
<strong>
Can someone explain to me how the regular P4 can beat the P4 Xeon in both SPECint and SPECfp? And it's by no small margin either.</strong><hr></blockquote>
The Xeon is 1) designed for use in boxes with more SMP going on, and 2) higher reliability.
1: You _can_ make any chip in an insanely SMP box - but it is a LOT easier and cheaper if the chip itself is designed with that in mind. I don't hear about many 8 CPU P4 boxes. You do (or can) hear about 8 way Xeons. (Although you might need to wade through a lot of gobbledygook and deal with a smarmy salesman or two to find that out). This is different than a 'blade server' with 8 P4s in it - those are more like 8 'individual' computers slammed into one box. But adding extra complexity to the chip means less room for speed improvements -> slower at precisely the same transistor count.
2: The boxes the Xeon (or the full Power4) is targeted at are a little more mission-critical than a 5-man department's file server. By making the physical traces on the CPU slightly heftier, the failure rate of the chips can be significantly lower. I don't have any idea what the numbers are, but something like this: By sacrificing 50% in speed (thicker wires -> more heat -> slower) getting the chance of failure in the next year or two to drop 10-fold. Or 100-fold. I'd expect any random Xeon or Power4 that passed to last awhile even after running full tilt for 4 years. Straight.
The part about the ppc970 that has me excited are the various comments reported as coming from IBM that indicate the 970 is 'designed with SMP in mind'. The best attribution I can turn up mentioned 8-way SMP.
If Apple did ever release an 8-way, Matsu could change his .sig to 'Bumping prices AND specs'
<strong>
If Apple did ever release an 8-way, Matsu could change his .sig to 'Bumping prices AND specs'
<img src="graemlins/lol.gif" border="0" alt="[Laughing]" /> <img src="graemlins/lol.gif" border="0" alt="[Laughing]" /> <img src="graemlins/lol.gif" border="0" alt="[Laughing]" /> I'll keep it in mind!
Let is also be know that this individual doesn't frequent Ars, particularly because he doesn't care for the site all that much. He prefers RealWorldTech, but that's neither here nor there...
Anyway here is what he had to saw about Hannibal's article (as well as the article that followed, the one written by friend, David K. Every over at igeek.com)
<begin reply>
[[[ Hey, thanks for that link. I used to read his MacKiDo site quite often, was sorry to see him shut it down a while back and didn't know he was writing again. Nice.
However, as far as this article goes I really think he kind of missed the point. David does make a good point in the vector section, but it is unfair to the Ars article because Hannibal clearly says that he will cover the execution core (which would include vector execution) in part two (we'll see).
Hannibal's article has a few inaccuracies (which I'll touch on a little below), but I respect the fact that he seems to have spent some time actually researching info on Power4 and others. David's article also has some problems (particularly the branch and IPC sections).
As far as the Ars link you sent me previously, I think that some of his comparisons are unfair inasmuch as they are comparing currently shipping Intel and Moto parts to an IBM part that is ~1 year away. Both Intel and Moto will have better parts by then, the Moto G4e design in particular will compare better in some stats when they have a .13um part to compare to Intel and IBM's 0.13um parts.
The Ars article also contains a few factual errors ... for example the repeated point Hannibal makes comparing 200 vs 126 inflight instructions is not actually comparing the same things (and I don't mean the difference between x86 and PPC).
David's article makes the same mistake though. People on the net keep complaining that we know that P4 has 12K-uop cache and G4e is 32KB and 970 is 64KB, and keep whining about not knowing the size of the uop. Big deal, it can be normed another way. PPC instructions are 32-bit instructions, which means that G4e holds 8K-instructions, and 970 holds 16K-instructions. So P4 is in the middle of that ... albeit trace-cache
versus instruction cache also throws in another level of complexity ...
I also don't think the branch prediction section is fully accurate either, but I can't go into details on that ... In general, the Ars tech article is a decent article with some solid research, and a few sour notes that should have been corrected. However, this is only part 1 of a 3 part article.]]] - anonymous source <end reply>
--
Ed M.
<strong>Programmer, with respect to your comments about the Article keyed by Hannibal, I think you might be referring to a few things that a trusted contact and CPU designer elaborated on a few weeks back when the ArsTech article first came out.</strong><hr></blockquote>
Your friend looks like he knows what he's talking about. I wasn't too impressed with Every's article either -- it seemed reactionary and had many inaccuracies. Hannibal was in general more accurate on the facts, but drew conclusions that I feel are a little suspect.
[ 11-23-2002: Message edited by: sc_markt ]</p>
<strong>
(thicker wires -> more heat -> slower)
</strong><hr></blockquote>
Just a note to an otherwise good post:
thicker wires actually reduces resistance, and thereby heat. What makes a circuit produced on a larger process slower is mostly the increased capacitance due to larger features, and to some extent, the greater distance between transistors.
Without compromising any NDAs.
<strong>Moki please come back. We need some real information on this BB. It seems that no one really does have a clue about when we can expect the 970 to be announced by Apple. You must have some idea what the target date is beyond the end of 2003.
Without compromising any NDAs.
What?! First of all, we all have a clue if we stop daydreaming for a collective minute -- second half '03. How many times does this have to be repeated? This is not the same thing as "end of 2003" either.
<strong>How many times does this have to be repeated?</strong><hr></blockquote>
Hm, lesse.. 3.061 times.
*sits back and starts counting*
<strong>
What?! First of all, we all have a clue if we stop daydreaming for a collective minute -- second half '03. How many times does this have to be repeated? This is not the same thing as "end of 2003" either.</strong><hr></blockquote>
Sorry Programmer, didn't mean to sound so pessimistic. But if things were no repeated on this forum, the total posting count would be about a tenth of what it is.
<strong>
Hm, lesse.. 3.061 times.
*sits back and starts counting*</strong><hr></blockquote>
Don't you mean 3.14159265 times
<strong>
Don't you mean 3.14159265 times</strong><hr></blockquote>
I run a Pentium.
Ok, I know, bad joke.