His point is that the Ars-Technica review may be accurate (as far as it goes), but conveniently leaves out the strengths of the PPC 970, while playing of up the strengths of the P4, when comparing the likely real-world performance we'll be getting...a good read.
Oops! You beat me to it...I should have refreshed the thread before posting! :eek:
Where on Earth does he get the idea that the PPC bus is double pumped?
From the article:
[quote]
You hear things like the P4 has a memory bus running at 800 MHz and the PowerPC?s only runs at 133 MHz. But then if you get the facts, the PowerPC?s is a wider bus (meaning it transfers more each cycle), and while both busses are double pumped (using the rising and falling edges of a clock to double the effective clock speed), but people are often stating the doubled number for the P4, and the halved number for the PPC; again to sort of mislead. Or in other words, the 133 MHz bus double pumped is running at 266; while the 400 MHz bus of the P4 is double pumped to 800, but is also not as wide, and has more latency, and there are whole inefficiencies with the RDRAM bus design, and so on.
<hr></blockquote>
Mot's said that it's not, and that it has no plans to double-pump MaxBus. Apple calls it 133Mhz (or 167MHz) and that's certainly not how they describe the RAM in the new models!
I anticipate a corrected version of the article shortly. <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
DKE has always existed in his own little world. Most of his writings are half of the picture at best, and completely misinformed at worst. There are *many* factual problems with the DKE article, the "double pumped" issue being one of them. MOst of his inaccuracies are due to his misunderstanding of the X86 series of microprocessors.
Take is writings with a hefty grain of salt. Yes, there are some good facts in his articles, but mostly it's concentrating on one little area while *completely* missing the larger picture.
Well, this is turning into a bit more of a rant than I'd like, so I'll quit now, and try to get somewhat back on topic.
....no, there is no provision for a L3 Cache on the 970 according to the MPF presentation
And that makes sense, since the 3.2GB/s pipes to and from main RAM and the generous on-chip caches obviate the need for one.</strong><hr></blockquote>
I don't completely agree with the first point - even with daul channel PC2700 or Rambus RAM, L3 cache can still make some sense, as it has much smaller latency than any main RAM.
I don't completely agree with the first point - even with daul channel PC2700 or Rambus RAM, L3 cache can still make some sense, as it has much smaller latency than any main RAM.
</strong><hr></blockquote>
Yeah, but does it make enough sense in a package that already has almost 600 pins?
Adding additional tags for the L3 cache in the 970 would make the chip larger than it currently is, thus driving up cost/heat/power. The L3 would be of minimal benefit, despite the lower latency, and wouldn't cost-justify.
The current "wind-tunnel" PowerMacs are designed for the 1.25GHz G4. Period. End of story.
</strong><hr></blockquote>
Wrong. Sorry. Nope. End of story. The current tower was for the Moto G4 to be released in jan. It's new mobo was way too hot, and had major cooling issues. That delayed the release of it until jan abd the stop gap chips were thrown in. So don't get your feathers all ruffled.
Yeah, but does it make enough sense in a package that already has almost 600 pins?
</strong><hr></blockquote>
My point was just that a fast FSB and fast main memory alone don't automatically make L3 useless (your post seemed to imply that). Packaging and silicon real estate are different stories, and certainly good arguments against an on-die L3 controller in this case.
My point was just that a fast FSB and fast main memory alone don't automatically make L3 useless (your post seemed to imply that). Packaging and silicon real estate are different stories, and certainly good arguments against an on-die L3 controller in this case.
</strong><hr></blockquote>
True, the word "obviate" was too strong. Just to be clear, I meant that given the size of the chip, the memory bandwidth and big on-chip caches make L3 more of an enhancement than a need, so it could be axed to save pins and silicon.
"Wrong. Sorry. Nope. End of story. The current tower was for the Moto G4 to be released in jan. It's new mobo was way too hot, and had major cooling issues. That delayed the release of it until jan abd the stop gap chips were thrown in. So don't get your feathers all ruffled."
Hmmm. It will be interesting to see this 'new mobo' in January. The benches compared to the current 'stop gap' machines will be intriguing...
Getting back to the Power Mac G5 "Featuring the PowerPC 970"...
A radical new motherboard architecture may be on the way. An idea follows:
GigaWire is an 10-bit bus which connects devices in a chain. 2-bits of the bus negotiate the next 16-byte packet transfer simultaniously with the current one.
GigaWire connects chips on a motherboard and external devices. There is a single master controller. Digital Video, USB data, AGP & PCI data and removable & fixed storage data can travel over a GigaWire chain.
This allows for smaller motherboards, and clustering of computers in a very small area.
Here's a senario if the Power Mac G5 was a modular computer.
In the Power Mac G5, a northbridge, southbridge and audio controller (5.1?) are connected in a GigaWire chain. The audio connects to the southbrige and also through the feet of other modules. The master controller is on the n-bridge.
The northbridge connects to the southbridge and an external GigaWire port. The GigaWire port can be connected to a 2nd Power Mac G5, and whatever computer is turned on first takes over the 2nd computer. The master controller on the 1st assumes control over the chips in the 2nd computer, basically.
Here's what the Power Mac G5 might look like (mmm... 4x anti-aliased AppleWorks drawings...)
That would be a base system with dual/single CPUs, an AGP port, 4 ram slots, single optical and hard drives, dual ethernet and 5.1 Audio. The amount of on-board functionality means most users won't need PCI slots.
The first image is of a CD/DVD server (duh) and has 6 CD/DVD drives (duh) using a GigaWire 6-channel ATA controller, and a UPS module.
The second image is of a workstation and has 6 PCI slots using a GigaWire PCI controller, and 6 Hard Drives using a GigaWire 6-channel ATA controller
The third image is of a general use G5 and has 3 PCI slots and 4 hard disks in a combo case using a GigaWire PCI controller, and 2 drives (CD/DVD drive(s) and or (a) Hard Drive(s)) using a GigaWire 2-channel ATA controller
It also says the 1067, 933, 867MHz 7455 will be released in October and December of this year. Yet we have had 1250MHz for many weeks now. Either they really underestimate or Apple gets the first pickings. I think it's a little of both.
<a href="http://e-www.motorola.com/brdata/PDFDB/docs/MPC7455EC.pdf"; target="_blank">Check this out</a>. I think the new 1.3v 7455 is running in the new 1.25GHz. Well before documentation was released Apple had it. motorola has its faults but it does give Apple the cream of its crop.
<strong><a href="http://e-www.motorola.com/brdata/PDFDB/docs/MPC7455EC.pdf"; target="_blank">Check this out</a>. I think the new 1.3v 7455 is running in the new 1.25GHz. Well before documentation was released Apple had it. motorola has its faults but it does give Apple the cream of its crop.</strong><hr></blockquote>
No, this is data on the low voltage version of the 7455A. The high voltage (1.8V) version of the 7455A is what is running in the 1.25GHz towers, and dissipating maybe 100W per pair of processors.
The volatege rating is encoded in the chip number, the L version is low voltage (1.3 in this case), the N version normal voltage (1.6), and the P version high voltage (1.8)
Comments
His point is that the Ars-Technica review may be accurate (as far as it goes), but conveniently leaves out the strengths of the PPC 970, while playing of up the strengths of the P4, when comparing the likely real-world performance we'll be getting...a good read.
Oops! You beat me to it...I should have refreshed the thread before posting! :eek:
[ 10-31-2002: Message edited by: Dave Marsh ]</p>
From the article:
[quote]
You hear things like the P4 has a memory bus running at 800 MHz and the PowerPC?s only runs at 133 MHz. But then if you get the facts, the PowerPC?s is a wider bus (meaning it transfers more each cycle), and while both busses are double pumped (using the rising and falling edges of a clock to double the effective clock speed), but people are often stating the doubled number for the P4, and the halved number for the PPC; again to sort of mislead. Or in other words, the 133 MHz bus double pumped is running at 266; while the 400 MHz bus of the P4 is double pumped to 800, but is also not as wide, and has more latency, and there are whole inefficiencies with the RDRAM bus design, and so on.
<hr></blockquote>
Mot's said that it's not, and that it has no plans to double-pump MaxBus. Apple calls it 133Mhz (or 167MHz) and that's certainly not how they describe the RAM in the new models!
I anticipate a corrected version of the article shortly. <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
Take is writings with a hefty grain of salt. Yes, there are some good facts in his articles, but mostly it's concentrating on one little area while *completely* missing the larger picture.
Well, this is turning into a bit more of a rant than I'd like, so I'll quit now, and try to get somewhat back on topic.
....no, there is no provision for a L3 Cache on the 970 according to the MPF presentation
<strong>....no, there is no provision for a L3 Cache on the 970 according to the MPF presentation</strong><hr></blockquote>
And that makes sense, since the 3.2GB/s pipes to and from main RAM and the generous on-chip caches obviate the need for one.
<strong>
And that makes sense, since the 3.2GB/s pipes to and from main RAM and the generous on-chip caches obviate the need for one.</strong><hr></blockquote>
I don't completely agree with the first point - even with daul channel PC2700 or Rambus RAM, L3 cache can still make some sense, as it has much smaller latency than any main RAM.
Bye,
RazzFazz
<strong>
I don't completely agree with the first point - even with daul channel PC2700 or Rambus RAM, L3 cache can still make some sense, as it has much smaller latency than any main RAM.
</strong><hr></blockquote>
Yeah, but does it make enough sense in a package that already has almost 600 pins?
It seems like a fair tradeoff to me.
--
The Visigothe
<strong>
The current "wind-tunnel" PowerMacs are designed for the 1.25GHz G4. Period. End of story.
</strong><hr></blockquote>
Wrong. Sorry. Nope. End of story. The current tower was for the Moto G4 to be released in jan. It's new mobo was way too hot, and had major cooling issues. That delayed the release of it until jan abd the stop gap chips were thrown in. So don't get your feathers all ruffled.
<strong>
Yeah, but does it make enough sense in a package that already has almost 600 pins?
</strong><hr></blockquote>
My point was just that a fast FSB and fast main memory alone don't automatically make L3 useless (your post seemed to imply that). Packaging and silicon real estate are different stories, and certainly good arguments against an on-die L3 controller in this case.
Bye,
RazzFazz
<strong>
My point was just that a fast FSB and fast main memory alone don't automatically make L3 useless (your post seemed to imply that). Packaging and silicon real estate are different stories, and certainly good arguments against an on-die L3 controller in this case.
</strong><hr></blockquote>
True, the word "obviate" was too strong. Just to be clear, I meant that given the size of the chip, the memory bandwidth and big on-chip caches make L3 more of an enhancement than a need, so it could be axed to save pins and silicon.
Hmmm. It will be interesting to see this 'new mobo' in January. The benches compared to the current 'stop gap' machines will be intriguing...
Lemon Bon Bon
The Motorola Confidential PDF said Q2 2003.
Getting back to the Power Mac G5 "Featuring the PowerPC 970"...
A radical new motherboard architecture may be on the way. An idea follows:
GigaWire is an 10-bit bus which connects devices in a chain. 2-bits of the bus negotiate the next 16-byte packet transfer simultaniously with the current one.
GigaWire connects chips on a motherboard and external devices. There is a single master controller. Digital Video, USB data, AGP & PCI data and removable & fixed storage data can travel over a GigaWire chain.
This allows for smaller motherboards, and clustering of computers in a very small area.
Here's a senario if the Power Mac G5 was a modular computer.
In the Power Mac G5, a northbridge, southbridge and audio controller (5.1?) are connected in a GigaWire chain. The audio connects to the southbrige and also through the feet of other modules. The master controller is on the n-bridge.
The northbridge connects to the southbridge and an external GigaWire port. The GigaWire port can be connected to a 2nd Power Mac G5, and whatever computer is turned on first takes over the 2nd computer. The master controller on the 1st assumes control over the chips in the 2nd computer, basically.
Here's what the Power Mac G5 might look like (mmm... 4x anti-aliased AppleWorks drawings...)
<a href="http://bartoact.netfirms.com/Power Mac G5.tiff" target="_blank">http://bartoact.netfirms.com/Power Mac G5.tiff</a>
That would be a base system with dual/single CPUs, an AGP port, 4 ram slots, single optical and hard drives, dual ethernet and 5.1 Audio. The amount of on-board functionality means most users won't need PCI slots.
<a href="http://bartoact.netfirms.com/Power Mac G5 CD Server Small.tiff" target="_blank">http://bartoact.netfirms.com/Power Mac G5 CD Server Small.tiff</a> <a href="http://bartoact.netfirms.com/Power Mac G5 Workstation Small.tiff" target="_blank">http://bartoact.netfirms.com/Power Mac G5 Workstation Small.tiff</a> <a href="http://bartoact.netfirms.com/Power Mac G5 General Use Small.tiff" target="_blank">http://bartoact.netfirms.com/Power Mac G5 General Use Small.tiff</a>
The first image is of a CD/DVD server (duh) and has 6 CD/DVD drives (duh) using a GigaWire 6-channel ATA controller, and a UPS module.
The second image is of a workstation and has 6 PCI slots using a GigaWire PCI controller, and 6 Hard Drives using a GigaWire 6-channel ATA controller
The third image is of a general use G5 and has 3 PCI slots and 4 hard disks in a combo case using a GigaWire PCI controller, and 2 drives (CD/DVD drive(s) and or (a) Hard Drive(s)) using a GigaWire 2-channel ATA controller
Barto
[ 11-01-2002: Message edited by: Barto ]</p>
<strong>New G4 in January???
The Motorola Confidential PDF said Q2 2003.
</strong><hr></blockquote>
It also says the 1067, 933, 867MHz 7455 will be released in October and December of this year. Yet we have had 1250MHz for many weeks now. Either they really underestimate or Apple gets the first pickings. I think it's a little of both.
The G4 Apple uses is the same except the GHz rating is based on testing in Apple or simulated Apple hardware.
That means a 1.5kg heatsink and 120mm delta fan. What PC users see and yell, in a reflex action, "holy f***ing s***!"
If Apple used more sedate cooling, the G4 would only just be breaking the 1GHz barrier.
Barto
<strong><a href="http://e-www.motorola.com/brdata/PDFDB/docs/MPC7455EC.pdf"; target="_blank">Check this out</a>. I think the new 1.3v 7455 is running in the new 1.25GHz. Well before documentation was released Apple had it. motorola has its faults but it does give Apple the cream of its crop.</strong><hr></blockquote>
No, this is data on the low voltage version of the 7455A. The high voltage (1.8V) version of the 7455A is what is running in the 1.25GHz towers, and dissipating maybe 100W per pair of processors.
The volatege rating is encoded in the chip number, the L version is low voltage (1.3 in this case), the N version normal voltage (1.6), and the P version high voltage (1.8)
michael
[ 11-04-2002: Message edited by: Barto ]</p>