does anyone worry that apple might hamper the potential of the new powermacs. like they currently do by messing around with L3 cache and using slower PCI and ATA speeds than current PCs?
Here is an EXCELLENT article (<a href="http://www.anandtech.com/IT/showdoc.html?i=1747"; target="_blank">Comparison</a>) about the PIV XEON chips. They compare the XEON DP, XEON MP and the Athlon MP.
It is important to remember the price of the CPU's you are comparing. The XEON DP is similar in price to the Athlon...but remember the XEON MP 2.0 runs about $5,000.00 each.
Now, you may be asking, why are these the important chips to watch? Well, I will not order any workstations at work that are anything less the Xeon. Entry level Xeon workstations from Dell are ~$1,400.00.
We run RH Linux on all our servers and I can tell you that the XEON DP with Hyperthreading performs extremely well. If the next processor in Macs can't at compare to the PIV Xeon DP then I am concerned.
Edit: Another note...
Also, I DO NOT consider Linux a good desktop environment. I can EASILY see OSX replacing windows and Linux as corporate workstations. Servers...that's a different story. Apple is nowhere ready for the server market IMHO.
<strong>Here is an EXCELLENT article (<a href="http://www.anandtech.com/IT/showdoc.html?i=1747"; target="_blank">Comparison</a>) about the PIV XEON chips. They compare the XEON DP, XEON MP and the Athlon MP.</strong><hr></blockquote>
I find this quote from the article interesting:
[quote]
Since the Xeon MP processors still all connect to the North Bridge through a 3.2GB/s FSB link, having a 6.4GB/s memory bus might seem a bit useless. However, if you take into account that a great deal of these 4-way machines require more than 1GB/s of I/O alone, it is clear where the additional memory bandwidth becomes useful. <hr></blockquote>
This is the same "DDR hack" that Apple is using in its systems (albeit 2.4 times faster). Also interesting is that Intel uses a shared bus architecture, which I hadn't realized. That could give SMP 970's an advantage since each processor gets 6.4 GB/sec of bus bandwidth in such a system (whether the memory system can keep up is another matter). It'll be interesting to see if the companion chip(s) for the 970 has an L3 cache built into it to bolster the memory system's performance.
You can't express performance in a single number unless you define what your task is. Are you running Photoshop? Maya? Web browsing? Mail? Apache? Databases? Scientific processing? Games? If you don't specify a task then you may as well just use SPEC... even then its 2 numbers.</strong><hr></blockquote>
Naturally!
My point was that everyone is focussing on the speed of a single core using a couple of questionable metrics. By all appearances the core of the 970 will not be a world-beater when it arrives, but is this going to be the most important factor in a live system?
My suggestion is that IBM and Apple plan to go aggressively after SMP and multi-core designs -- you yourself have made similar predictions IIRC. Now in these kinds of configurations, wouldn't the processor bus be the major limiting factor? After all, you could keep on adding cores until the bus is saturated and/or the cows come home.
So: even if the 970's core is not earth-shaking when it comes out, the performance of SMP 970 systems might well be, given that the processor bus is very fast indeed.
Edit:
Ooh. Read your post just before mine. Does this mean that you think that memory will be the main limiting factor? Hmmm. Wasn't THT wondering aloud a while ago about the virtues of a Rambus+970 setup?
<strong>Rambus? Virtues? /me steps out of Bizarro-World.</strong><hr></blockquote>
I'm not too clear on just why Rambus is supposed to be the devil's spawn, apart from the fact that they're in bed with Intel. And expensive. But I do seem to recall THT (a little apologetically) suggesting that Rambus was especially well-suited to the expected performance profile of the 970.
Or maybe it was someone else, and I've unwitting defamed THT. I'll try to dig up the post.
I think it had something to do with the fact that Rambus is a serial memory technology and it is well suited for the type of bus that the 970 employs; a fast streaming bus.
<strong>It didn't 1-2 years ago when Intel was ignoring DDR.</strong><hr></blockquote>
If I am not mistaken Intel wasn't ignoring DDR, they were contractually required to use Rambus for a certain time period. Once that period was over you saw a shift towards DDR based systems.
This is the same "DDR hack" that Apple is using in its systems (albeit 2.4 times faster). Also interesting is that Intel uses a shared bus architecture, which I hadn't realized. That could give SMP 970's an advantage since each processor gets 6.4 GB/sec of bus bandwidth in such a system (whether the memory system can keep up is another matter). It'll be interesting to see if the companion chip(s) for the 970 has an L3 cache built into it to bolster the memory system's performance.</strong><hr></blockquote>
Something to not forget is that these systems with 4 cpu's use 4 way memory interleaving.
I know seemingly everyone is so concerned about apple's ddr "hack" but it isn't that big of an issue. I think people are complaining more out of frustration than anything else! I would rather see an interleaved setup on the workstations. That's what I'm guessing we will see if we ever see the "G5".
Also, the Xeon MP's price hike is cause by the L3 cache. I don't know if we really need an L3 cache on a workstation cpu (aka 970) if we get one that is fast...like the Xeon DP.
I'm getting ready to order a Xeon MP machine (Dell 6600) I'll have to post some pictures here once I get it. 16G ram, RAID 0+1 with 15k drives, and 4 Xeon MP 2.0's...mmmmmmmm . Now if only apple would make hardware like this! Maybe they would get more of my money!!!!!
<a href="http://www.extremetech.com/article2/0,3973,835085,00.asp"; target="_blank">Here</a> is a nice little article over at extreme tech talking about upcoming AMD/Intel stuff up to the middle of next year. It also has a recap of last year and even a little snippit about Apple's future (nothing that hasn't already been speculated however)
Comments
It is important to remember the price of the CPU's you are comparing. The XEON DP is similar in price to the Athlon...but remember the XEON MP 2.0 runs about $5,000.00 each.
Now, you may be asking, why are these the important chips to watch? Well, I will not order any workstations at work that are anything less the Xeon. Entry level Xeon workstations from Dell are ~$1,400.00.
We run RH Linux on all our servers and I can tell you that the XEON DP with Hyperthreading performs extremely well. If the next processor in Macs can't at compare to the PIV Xeon DP then I am concerned.
Edit: Another note...
Also, I DO NOT consider Linux a good desktop environment. I can EASILY see OSX replacing windows and Linux as corporate workstations. Servers...that's a different story. Apple is nowhere ready for the server market IMHO.
We DO need the 970 NOW!
[ 01-19-2003: Message edited by: Mike ]</p>
<strong>Here is an EXCELLENT article (<a href="http://www.anandtech.com/IT/showdoc.html?i=1747"; target="_blank">Comparison</a>) about the PIV XEON chips. They compare the XEON DP, XEON MP and the Athlon MP.</strong><hr></blockquote>
I find this quote from the article interesting:
[quote]
Since the Xeon MP processors still all connect to the North Bridge through a 3.2GB/s FSB link, having a 6.4GB/s memory bus might seem a bit useless. However, if you take into account that a great deal of these 4-way machines require more than 1GB/s of I/O alone, it is clear where the additional memory bandwidth becomes useful. <hr></blockquote>
This is the same "DDR hack" that Apple is using in its systems (albeit 2.4 times faster). Also interesting is that Intel uses a shared bus architecture, which I hadn't realized. That could give SMP 970's an advantage since each processor gets 6.4 GB/sec of bus bandwidth in such a system (whether the memory system can keep up is another matter). It'll be interesting to see if the companion chip(s) for the 970 has an L3 cache built into it to bolster the memory system's performance.
<strong>
You can't express performance in a single number unless you define what your task is. Are you running Photoshop? Maya? Web browsing? Mail? Apache? Databases? Scientific processing? Games? If you don't specify a task then you may as well just use SPEC... even then its 2 numbers.</strong><hr></blockquote>
Naturally!
My point was that everyone is focussing on the speed of a single core using a couple of questionable metrics. By all appearances the core of the 970 will not be a world-beater when it arrives, but is this going to be the most important factor in a live system?
My suggestion is that IBM and Apple plan to go aggressively after SMP and multi-core designs -- you yourself have made similar predictions IIRC. Now in these kinds of configurations, wouldn't the processor bus be the major limiting factor? After all, you could keep on adding cores until the bus is saturated and/or the cows come home.
So: even if the 970's core is not earth-shaking when it comes out, the performance of SMP 970 systems might well be, given that the processor bus is very fast indeed.
Edit:
Ooh. Read your post just before mine. Does this mean that you think that memory will be the main limiting factor? Hmmm. Wasn't THT wondering aloud a while ago about the virtues of a Rambus+970 setup?
[ 01-20-2003: Message edited by: boy_analog ]
[ 01-20-2003: Message edited by: boy_analog ]</p>
<strong>Rambus? Virtues? /me steps out of Bizarro-World.</strong><hr></blockquote>
I'm not too clear on just why Rambus is supposed to be the devil's spawn, apart from the fact that they're in bed with Intel. And expensive. But I do seem to recall THT (a little apologetically) suggesting that Rambus was especially well-suited to the expected performance profile of the 970.
Or maybe it was someone else, and I've unwitting defamed THT. I'll try to dig up the post.
Edit:
Nope, can't get the search to work. Bummer.
[ 01-20-2003: Message edited by: boy_analog ]</p>
The technology is very sound and scaling very well too. And most important it addresses latency much better than DDR does.
Intel is slowly dropping Rambus, but actually now Rambus makes sense. It didn't 1-2 years ago when Intel was ignoring DDR.
<strong>It didn't 1-2 years ago when Intel was ignoring DDR.</strong><hr></blockquote>
If I am not mistaken Intel wasn't ignoring DDR, they were contractually required to use Rambus for a certain time period. Once that period was over you saw a shift towards DDR based systems.
<strong>
This is the same "DDR hack" that Apple is using in its systems (albeit 2.4 times faster). Also interesting is that Intel uses a shared bus architecture, which I hadn't realized. That could give SMP 970's an advantage since each processor gets 6.4 GB/sec of bus bandwidth in such a system (whether the memory system can keep up is another matter). It'll be interesting to see if the companion chip(s) for the 970 has an L3 cache built into it to bolster the memory system's performance.</strong><hr></blockquote>
Something to not forget is that these systems with 4 cpu's use 4 way memory interleaving.
I know seemingly everyone is so concerned about apple's ddr "hack" but it isn't that big of an issue. I think people are complaining more out of frustration than anything else! I would rather see an interleaved setup on the workstations. That's what I'm guessing we will see if we ever see the "G5".
Also, the Xeon MP's price hike is cause by the L3 cache. I don't know if we really need an L3 cache on a workstation cpu (aka 970) if we get one that is fast...like the Xeon DP.
I'm getting ready to order a Xeon MP machine (Dell 6600)
Enjoy!
[ 01-20-2003: Message edited by: JohnHenry ]</p>