Power5 info

thttht
Posted:
in Future Apple Hardware edited January 2014
There will two major news bursts for the IBM's Power5 processor: the Hot Chips conference this week and Microprocessor Forum in October. Well here is a news blurb from Hot Chips:



IBM's Power5 Chip Adds New Threading Technology



IBM's upcoming Power5 microprocessor will enable administrators to easily switch back and forth from multi-threaded to single-threaded mode, and will dynamically shift power within the chip as needed by the work being done.

...

Papermaster said the SMT technology in the 64-bit dual-core Power5 will effectively boost user performance fourfold. In the chip, each core will be able to handle two threads simultaneously.

...

In addition, the chip automatically can sense the work it is being asked to do, and can dynamically shift energy resources toward that job as needed and away from areas where demand is less, Papermaster said.




We should know much more tomorrow, and more accurately. The Power5 is essentially a Power4 with the above and maybe other undisclosed additions, imo. So it's 2 thread SMT per core and dynamic power usage so far. Hopefully a single core version will make it into Apple machines in 2005. Sure hope the dynamic power usage makes it into 130 and 90 nm 970 chips.



No word on Fast Path, so maybe it was a strawman from IBM or something.
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Comments

  • Reply 1 of 31
    wizard69wizard69 Posts: 12,647member
    Why wait for 2005. July of 2004 sounds good to me.



    Hot chips should be very interesting. Unfortunately as things progress "hot" can be taken literally.



    Dave





    Quote:

    Originally posted by THT

    There will two major news bursts for the IBM's Power5 processor: the Hot Chips conference this week and Microprocessor Forum in October. Well here is a news blurb from Hot Chips:



    IBM's Power5 Chip Adds New Threading Technology



    IBM's upcoming Power5 microprocessor will enable administrators to easily switch back and forth from multi-threaded to single-threaded mode, and will dynamically shift power within the chip as needed by the work being done.

    ...

    Papermaster said the SMT technology in the 64-bit dual-core Power5 will effectively boost user performance fourfold. In the chip, each core will be able to handle two threads simultaneously.

    ...

    In addition, the chip automatically can sense the work it is being asked to do, and can dynamically shift energy resources toward that job as needed and away from areas where demand is less, Papermaster said.




    We should know much more tomorrow, and more accurately. The Power5 is essentially a Power4 with the above and maybe other undisclosed additions, imo. So it's 2 thread SMT per core and dynamic power usage so far. Hopefully a single core version will make it into Apple machines in 2005. Sure hope the dynamic power usage makes it into 130 and 90 nm 970 chips.



    No word on Fast Path, so maybe it was a strawman from IBM or something.




  • Reply 2 of 31
    hmurchisonhmurchison Posts: 12,129member
    Sounds like Multithreading done right!



    This is just what we need. Right now I prefer good multitasking over brute force because i'm a simple consumer who needs to have music in the background, a small 3d render going on and other various tasks running without the system bogging down. This SMT will make this easy to run with little to no code needed from programmers.



    I look forward to reading more info.
  • Reply 3 of 31
    hmurchisonhmurchison Posts: 12,129member
    Good minireport by "Exponent"



    here:



    http://forums.macrumors.com/showthre...threadid=35585
  • Reply 4 of 31
    thttht Posts: 3,011member
    More info:



    IBM: Power5 Chip to Tap Threading



    PALO ALTO, Calif.?A clever implementation of simultaneous multithreading will allow IBM Corp.'s Power5 processor to increase performance by 40 percent compared with the Power4, while only increasing the per-core die size by about 24 percent.

    ...

    The Power5 chip is on track to ship in 2004, Kalla said. Initially, IBM will fabricate the chip using 130-nm process technologies

    ...

    Kalla characterized the Power5 as an extension to the Power4 architecture, with additions tacked on to support the additional thread.

    ...

    While the Power4 has 80 physical registers, 120 registers will be available to programmers using the Power5, Kalla said. All registers, caches and instruction units can be shared between both threads.

    ...

    Most of the microarchitectural units within the chip are power-managed, although Kalla declined to say what the effect the power management would have.



    But actually disabling the multithreading option actually has an important side effect?it can improve performance, Kalla said. Turning off a thread gives the single thread access to all 120 registers, affording the Power5 a significant instruction-per-clock (IPC) advantage compared with the Power4.

    ...





    24% increase in the core would translate to about 140 sq mm for a hypothetical 970 with Power5 features. It does not appear the Power5 has AltiVec. Lets hope that 24% is including things other than SMT logic. The thread level control looks excellent though. Power management for the architectural units is real good news.



    Hopefully these features will be folded into the PPC 970 ASAP.
  • Reply 5 of 31
    bigcbigc Posts: 1,224member
    Still only on a 130nm chip in 2004 for the Power5, thought they were going for 90nm, is IBM not talking about 90nm anymore? Thought the plan was to cram more stuff into the same space.



    Also read that the Power5 was to have an on-board memory controller which I thought would have required the 90nm process. I must be missing something or IBM is quieting down their speak.
  • Reply 6 of 31
    telomartelomar Posts: 1,804member
    Quote:

    Originally posted by Bigc

    Still only on a 130nm chip in 2004 for the Power5, thought they were going for 90nm, is IBM not talking about 90nm anymore? Thought the plan was to cram more stuff into the same space.



    Also read that the Power5 was to have an on-board memory controller which I thought would have required the 90nm process. I must be missing something or IBM is quieting down their speak.




    IBM is sticking to what they've said all along. The POWER5 has always been roadmapped to appear on a 130 nm process at launch and it will indeed be getting a memory controller on chip. The plan with the POWER5 has always been to design it more efficiently and that's exactly what they've done from what I've seen.
  • Reply 7 of 31
    henriokhenriok Posts: 537member
    Power5 like the Power4 will probably be manufactured to be reliable, not nessessarily trying to push the limits of what fabrication process is on the bleeding edge at the moment. 90 nm is still an experimental process while 130 nm is a proven, trustworthy process with high yield. Pwert5 will eventually move to 90 nm, but that'd be the Power5+. Just like Power4 went from 180 nm to 130 nm and became Power4+.



    Excellent news regarding Power5! Shipping starts in Q4'03 and so forth.. The thing that processes can command the processor to turn off SMT seems very good compated to Intel's implementation. The actual performance gain seems to be waaaay up from intel's hack too.



    And.. The Power5-derivative is called "97x" not 980. IBM says so.. so do I. I would guess that it will be called PowerPC 975 when it finally arrives, and the die shrink version of 970 will be called 970FX or something like that. Since the development of 97x must have beed parallell to that of Power5 it probably won't be far off.. how far off, I cannot say, but late 2004 seems reasonable. 2.5 GHz 970FX next spring and 3 GHz 975 in the fall?



    Looking at the Intel roadmap, I'm not to worried.. they are not going to break the 4 GHz barrier with Prescott next year, and we will have dual 3 GHz by then.. or more.
  • Reply 8 of 31
    Quote:

    Originally posted by Bigc

    Still only on a 130nm chip in 2004 for the Power5, thought they were going for 90nm, is IBM not talking about 90nm anymore? Thought the plan was to cram more stuff into the same space.



    Also read that the Power5 was to have an on-board memory controller which I thought would have required the 90nm process. I must be missing something or IBM is quieting down their speak.




    As reported on Computer Business Review Online:

    The word on the street is that clock speeds will range from 1.5GHz to 2GHz or higher with the Power5s. The Power5+ processors, due sometime in 2005, will use a 90 nanometer copper/SOI process and could scale from 2GHz to 3GHz or faster. These Power5 and Power5+ chips will be manufactured in IBM's most advanced 300mm fab line in East Fishkill, New York.

  • Reply 9 of 31
    bigcbigc Posts: 1,224member
    Quote:

    Originally posted by BostonMH

    As reported on Computer Business Review Online:

    The word on the street is that clock speeds will range from 1.5GHz to 2GHz or higher with the Power5s. The Power5+ processors, due sometime in 2005, will use a 90 nanometer copper/SOI process and could scale from 2GHz to 3GHz or faster. These Power5 and Power5+ chips will be manufactured in IBM's most advanced 300mm fab line in East Fishkill, New York.





    So when does the 970 go to 90nm, 2004 or 2005? I was under the assumption (hope, maybe) that the 970 would go to 90nm with a memory controller in 2004.
  • Reply 10 of 31
    thttht Posts: 3,011member
    Quote:

    Originally posted by Bigc

    So when does the 970 go to 90nm, 2004 or 2005? I was under the assumption (hope, maybe) that the 970 would go to 90nm with a memory controller in 2004.



    I believe IBM will start 90 nm production 2Q 04. By that time IBM would have been shipping at 130 nm for 2 years, and a 90 nm ramp should be right for about that time. I would hope Power5 features creep into the 970 by then as well.



    The Power5 may get an on-die memory controller, but I'm doubting that feature will creep into 970 derivative. The 970 already is a little bit large in die size, albiet it's because of automated tools and its floor plan seems to waste a lot of space, and adding an on-die memory controller will only make it bigger. It reall needs to be under 100 sq mm, and that acreage is desperately needed for more L2 cache.
  • Reply 11 of 31
    bigcbigc Posts: 1,224member
    Quote:

    Originally posted by THT

    I believe IBM will start 90 nm production 2Q 04. By that time IBM would have been shipping at 130 nm for 2 years, and a 90 nm ramp should be right for about that time. I would hope Power5 features creep into the 970 by then as well.



    The Power5 may get an on-die memory controller, but I'm doubting that feature will creep into 970 derivative. The 970 already is a little bit large in die size, albiet it's because of automated tools and its floor plan seems to waste a lot of space, and adding an on-die memory controller will only make it bigger. It reall needs to be under 100 sq mm, and that acreage is desperately needed for more L2 cache.




    Isn't the 970 512KB L2 enough? Seems like L3 (off-die) or a memory controller would be the way to go but that would take 90nm. What would be first to get 90nm, some ASIC or would they go right to a PowerPC (or Power5)?
  • Reply 12 of 31
    programmerprogrammer Posts: 3,409member
    Quote:

    Originally posted by THT

    I believe IBM will start 90 nm production 2Q 04. By that time IBM would have been shipping at 130 nm for 2 years, and a 90 nm ramp should be right for about that time. I would hope Power5 features creep into the 970 by then as well.



    The Power5 may get an on-die memory controller, but I'm doubting that feature will creep into 970 derivative. The 970 already is a little bit large in die size, albiet it's because of automated tools and its floor plan seems to waste a lot of space, and adding an on-die memory controller will only make it bigger. It reall needs to be under 100 sq mm, and that acreage is desperately needed for more L2 cache.




    On the contrary -- I think the 9xx is more likely to get an on-chip memory controller than the POWER series, at least to begin with. IBM was (informally) discussing an on-chip memory controller as something they'll do in the low end if they feel it is advantageous. The 9xx will shrink to 90nm in ~6 months just as the POWER5 starts to get rolling on 130nm.
  • Reply 13 of 31
    thttht Posts: 3,011member
    Quote:

    Originally posted by Bigc

    Isn't the 970 512KB L2 enough?



    No. CPU clock rates are increasing much faster than main memory, and every generation of CPU will have more and more on-die cache to make up for the slower rate of increase in memory performance.



    Quote:

    Seems like L3 (off-die) or a memory controller would be the way to go but that would take 90nm. What would be first to get 90nm, some ASIC or would they go right to a PowerPC (or Power5)?



    The problem with on-die memory controllers is that Apple has to redesign its motherboard architecture, and apparently do it in a year or so. The current G5 architecture is very very good, and Apple should keep it for the next 3 years or so. To differentiate between low end and high chips, IBM and Apple can do quite a few things without changing the motherboard design. Namely, 512k L2 970 chips for low end, 1MB L2 SMT 970+ chips for high end. It should just be a drop in replacement. I believe it'll be cheaper for IBM and Apple to fab 1 MB on-die L2 970s than adding off-die cache.



    Lastly, I'll guess it'll be either a PPC 750 derived chip, a 970 dervied chip, or some embedded PPC chip that'll be the the 1st to come out of the 90 nm fab. The Power5 would be a rather daunting chip to ramp up first at 90 nm.
  • Reply 14 of 31
    thttht Posts: 3,011member
    Quote:

    Originally posted by Programmer

    On the contrary -- I think the 9xx is more likely to get an on-chip memory controller than the POWER series, at least to begin with. IBM was (informally) discussing an on-chip memory controller as something they'll do in the low end if they feel it is advantageous. The 9xx will shrink to 90nm in ~6 months just as the POWER5 starts to get rolling on 130nm.



    That's possible. Do you think Apple would use it? A 970 with on-die memory controller and Hypertransport would be an interesting chip.
  • Reply 15 of 31
    wizard69wizard69 Posts: 12,647member
    It might be that by going with an on die memory controller and hyper transport that the actual die usage will go down. If not go down it might mot be as much as one first suspects due to the elimination of the other bus. I think Apple really needs something like this to make Powerbooks and iMACs feasable.



    I'm with you on the need for more cache. With the present design the cache can never be to large. SMT is likely to put some severe strain on the cache so a vast improvement there is in order.



    Quote:

    Originally posted by THT

    I believe IBM will start 90 nm production 2Q 04. By that time IBM would have been shipping at 130 nm for 2 years, and a 90 nm ramp should be right for about that time. I would hope Power5 features creep into the 970 by then as well.



    The Power5 may get an on-die memory controller, but I'm doubting that feature will creep into 970 derivative. The 970 already is a little bit large in die size, albiet it's because of automated tools and its floor plan seems to waste a lot of space, and adding an on-die memory controller will only make it bigger. It reall needs to be under 100 sq mm, and that acreage is desperately needed for more L2 cache.




  • Reply 16 of 31
    wizard69wizard69 Posts: 12,647member
    Not just interesting but almost a requirement for smaller more integrated systems. Such a chip is Apples best hope for Portables or iMACs that don't suck. Mu suspicions are that the present bus and hub arraingement would be a huge power drain, plus it takes up to much space.



    The interesting thing would be the impact on die usage. For some systems though I don't think in makes much differrence because fo the size and space advantages.



    Dave





    Quote:

    Originally posted by THT

    That's possible. Do you think Apple would use it? A 970 with on-die memory controller and Hypertransport would be an interesting chip.



  • Reply 17 of 31
    krassykrassy Posts: 595member
    Quote:

    Originally posted by Programmer

    On the contrary -- I think the 9xx is more likely to get an on-chip memory controller than the POWER series, at least to begin with. IBM was (informally) discussing an on-chip memory controller as something they'll do in the low end if they feel it is advantageous. The 9xx will shrink to 90nm in ~6 months just as the POWER5 starts to get rolling on 130nm.



    i think the following sentence out of an IBM email makes it pretty clear that they are going to implement an on-chip memory controller in future 970s: "IBM has joined the HyperTransport Consortium and will build HyperTransport links into its PowerPC 970 chip, which will ship with Apple's G5 desktop computers. HyperTransport is a standard for linking chips such as the CPU (central processing unit) and the memory in a system."



    or am i wrong on this?
  • Reply 18 of 31
    thttht Posts: 3,011member
    Quote:

    Originally posted by wizard69

    Not just interesting but almost a requirement for smaller more integrated systems. Such a chip is Apples best hope for Portables or iMACs that don't suck. Mu suspicions are that the present bus and hub arraingement would be a huge power drain, plus it takes up to much space.



    I don't really think so. The hub arrangement is still going to be there: a CPU chip, an AGP tunnel, and an I/O tunnel. The Powerbook G4s currently use a single ASIC integrating the memory controller, AGP, and I/O function, but prior to that they have used the same basic hub arrangement: CPU, system ASIC, I/O ASIC. So, the issues still are mostly the same for now.



    From a technical standpoint, there's really nothing stopping Apple from making a PowerBook G5 or an iMac G5 today, they just don't want to or don't have the resources to do so. There's lots of 1 to 1.4 GHz 970 CPUs just sitting around doing not much right now. Waiting on 90 nm chips would be a mistake, and it may not be the power saving panacea that die shrinks are supposed to be due to increased power leakage at those scales.



    Quote:

    The interesting thing would be the impact on die usage. For some systems though I don't think in makes much differrence because fo the size and space advantages.



    The die size of this prospective 970 with an on-chip memory controller seems pretty important to me. It has a pretty direct relationship to the cost of the chip. It's a tradeoff between the costs due to larger die size and Hypertransport AGP tunnel versus Apple's system ASIC. Over the past 4 years, Apple has been essentially using the same system ASIC and I/O ASICs for all of its systems. It'll be interesting to see if they start going away from that. Maybe IBM will produce multiple 970 chips



    One of the most important things I've yet to hear about is power management for the 970. Power management is going to be vastly important as we move forward with future designs, and there hardly has been a peep. The dynamic control of the Power5's architectural units is interesting, but I'd like to have more about dynamic voltage and frequency control.
  • Reply 19 of 31
    prior to Hannibal's quite insightful 970 tech articles at ARS,

    there was some talk here about the fact the 970 doesn't need L3 as much as it needs L2



    and, IIRC, some suggested that L3 might actually degrade performance now that the new memory subsystem bandwidth has jumped to over 6GB of throughput. since the new architecture allows for superfast swaps to RAM, the necessity of some cache seems to face diminishing returns, where, according to the Power4 specs, Pairs of CPUs will address jointly address a Single external L3 module of up to 32MB



    from here and whitepapers here



    as for the relevant ASICs involved,

    doesn't the 970 sport the new ApplePI interconnect, designed by Apple, manufactured at Fishkill?

    it used to be on the Powermac architecture page, but the graphics have been replaced by all silver chips
  • Reply 20 of 31
    cubedudecubedude Posts: 1,556member
    Quote:

    Originally posted by hmurchison

    Sounds like Multithreading done right!



    This is just what we need. Right now I prefer good multitasking over brute force because i'm a simple consumer who needs to have music in the background, a small 3d render going on and other various tasks running without the system bogging down. This SMT will make this easy to run with little to no code needed from programmers.



    I look forward to reading more info.




    My Cube handles music in the background, iMovie importing a QuickTime file, and Safari all at the same time, and still with reasonable speed.
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