I know this is a little bit off topic, but I'm curious: How does this mode bit correspond to the G3/G4 pseudo little-endian mode? That's the mode which I heard is missing from the G5, and the reason why Virtual PC won't run on the G5.
If the G5 has a some form of a little-endian mode -- even if it's different in some specific details from G3/G4 little-endian support -- that bodes well for an easier and faster G5 fix for the next version of Virtual PC. I'd been worried that much of the potential performance gain of VPC on the G5 would be lost to having to flip the ends of integers in software all of the time.
From what you see in "Programming Environments Manual for the PowerPC", is my above-expressed hope warranted?
I know this is a little bit off topic, but I'm curious: How does this mode bit correspond to the G3/G4 pseudo little-endian mode? That's the mode which I heard is missing from the G5, and the reason why Virtual PC won't run on the G5.
If the G5 has a some form of a little-endian mode -- even if it's different in some specific details from G3/G4 little-endian support -- that bodes well for an easier and faster G5 fix for the next version of Virtual PC. I'd been worried that much of the potential performance gain of VPC on the G5 would be lost to having to flip the ends of integers in software all of the time.
From what you see in "Programming Environments Manual for the PowerPC", is my above-expressed hope warranted?
Tough to say -- here's what it says in this particular reference:
Quote:
1.2.2.1 Byte Ordering
The default mapping for PowerPC processors is big-endian, but the UISA (user instruction set architecture) provides the option of operating in either big or little-endian mode.
The PowerPC Operating Environment Architecture (supervisor-level resources typically required by an operating system) defines two bits in the MSR for specifying byte ordering?LE (little-endian mode) and ILE (exception little-endian mode). The LE bit specifies whether the processor is configured for big-endian or little-endian mode; the ILE bit specifies the mode when an exception is taken by being copied into the LE bit of the MSR. A value of 0 specifies big-endian mode and a value of 1 specifies little-endian mode.
That's all it says. It does not specifically mention the 970, of course, but IBM is pretty good about putting in details for exceptions to the stated rules.
It also does not say what performance penalties there might be for mode-switching. I have to say I don't really understand why you would need little-endian mode except to be able to load instruction operands directly from the object code of the emulated machine's ISA.
My guess is that the LE mode was removed from the 970 and that is why VirtualPC doesn't run on the G5. The 970 will likely still retain the load byte-reversed instructions, however, which could be used to do much the same thing at the existing VirtualPC code. The problem is that there is currently no way to get the C/C++ compiler to generate that instruction. I had hoped somebody would add a "byte reversed" attribute to GCC that would tell the compiler to load the attributed data in byte-reversed format, but so far that hasn't materialized.
Comments
Originally posted by lundy
Little-endian is supported by a mode bit.
I know this is a little bit off topic, but I'm curious: How does this mode bit correspond to the G3/G4 pseudo little-endian mode? That's the mode which I heard is missing from the G5, and the reason why Virtual PC won't run on the G5.
If the G5 has a some form of a little-endian mode -- even if it's different in some specific details from G3/G4 little-endian support -- that bodes well for an easier and faster G5 fix for the next version of Virtual PC. I'd been worried that much of the potential performance gain of VPC on the G5 would be lost to having to flip the ends of integers in software all of the time.
From what you see in "Programming Environments Manual for the PowerPC", is my above-expressed hope warranted?
Creating Thread Number: 0
Creating Thread Number: 1
Loop Done; Time=9 secs for thread#:0, Loops=25000000
Loop Done; Time=9 secs for thread#:1, Loops=25000000
9 Seconds seems good.
Originally posted by lundy
Is it normal for gcc to give a warning on a source statement
static long long int A=0xFFFFFFFFFFFFFFFF;
that the constant is too big for a long int? Well duh, it's not a long int.
Append LL to the value to eliminate the warning.
static long long int A = 0xFFFFFFFFFFFFFFFFLL;
Originally posted by shetline
I know this is a little bit off topic, but I'm curious: How does this mode bit correspond to the G3/G4 pseudo little-endian mode? That's the mode which I heard is missing from the G5, and the reason why Virtual PC won't run on the G5.
If the G5 has a some form of a little-endian mode -- even if it's different in some specific details from G3/G4 little-endian support -- that bodes well for an easier and faster G5 fix for the next version of Virtual PC. I'd been worried that much of the potential performance gain of VPC on the G5 would be lost to having to flip the ends of integers in software all of the time.
From what you see in "Programming Environments Manual for the PowerPC", is my above-expressed hope warranted?
Tough to say -- here's what it says in this particular reference:
1.2.2.1 Byte Ordering
The default mapping for PowerPC processors is big-endian, but the UISA (user instruction set architecture) provides the option of operating in either big or little-endian mode.
The PowerPC Operating Environment Architecture (supervisor-level resources typically required by an operating system) defines two bits in the MSR for specifying byte ordering?LE (little-endian mode) and ILE (exception little-endian mode). The LE bit specifies whether the processor is configured for big-endian or little-endian mode; the ILE bit specifies the mode when an exception is taken by being copied into the LE bit of the MSR. A value of 0 specifies big-endian mode and a value of 1 specifies little-endian mode.
That's all it says. It does not specifically mention the 970, of course, but IBM is pretty good about putting in details for exceptions to the stated rules.
It also does not say what performance penalties there might be for mode-switching. I have to say I don't really understand why you would need little-endian mode except to be able to load instruction operands directly from the object code of the emulated machine's ISA.
Originally posted by Tidris
Append LL to the value to eliminate the warning.
static long long int A = 0xFFFFFFFFFFFFFFFFLL;
Thanks a lot!