Interesting DP Tidbit From Developer Article

in Current Mac Hardware edited January 2014
This isn't a rumor but it is perhaps a sign of things to come, and I thought it was worth posting since things are slow right now anyway. In Apple's new G5 optimization developer article, we find the following statement:

Dual-processor Power Mac G5 models include separate frontside buses to each G5 processor; this gives them an extra speed advantage over dual-processor Intel computers, which force both processors to share a single bus.

Article Link

Now I'm probably reading too much into this, but note the plural case, DP "models include. . ." There's only one DP model right now. I realize it's basically nothing, but it caught my eye.


  • Reply 1 of 8
    costiquecostique Posts: 1,084member
    You should read it so:

    From now on all dual-processor Power Mac G5 models will include separate frontside buses to each G5 processor.

  • Reply 2 of 8
    You must have been living under a rock since about October last year. We've known for some time that the 970 has a point-to-point front side bus. Yes, its a great thing but it'll be interesting to see how relevent it stays given the future multi-core processors and on-chip memory controllers.
  • Reply 3 of 8
    matsumatsu Posts: 6,558member
    I wonder if at some point it will be cheaper to put two G5's on a single card to get DP performance out of one CPU slot? Perhaps outright performance won't be as good as a machine with two independent buses, but possibly costs would come down for the lower rung machines?

    Multi core chips seem one way to do this, but perhaps it would be possible to do a G4 type arrangement with two CPU's on one card if it allows Apple to make a smaller cheaper Mobo for dual machines in the lower end. The bandwidth, even in such a config, would still be very high.
  • Reply 4 of 8
    Shouldn't this be Current Hardware?
  • Reply 5 of 8
    bodhibodhi Posts: 1,424member
    Going to Current Hardware...
  • Reply 6 of 8
    I do apologize for posting in the wrong forum. I posted in FH because I thought the statement indicated there would be more than one DP configuration in the near future.
  • Reply 7 of 8
    Who cares if the Busses are seperate you still have a logjam at the Memory Controller.

    Think about it. Each G5 is still only getting half of the theoretical 7.2Gbps bandwidth. The way to maximize performance would be two memory controllers. That way each processor would have the ful 6.4Gbps memory throughput.
  • Reply 8 of 8

    Originally posted by hmurchison

    Who cares if the Busses are seperate you still have a logjam at the Memory Controller.

    It's not a perfect solution to have two memory controllers, like in a NUMA architecture, because then each processor has a serious time hit accessing the memory that's owned by the other processor, and managing that memory can be a problem.

    -- Mark
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