G5 in Jan - new info

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  • Reply 101 of 141
    tcotco Posts: 87member
    [quote]Oh. OK, so what does that mean in terms of it's concept with the G4? I'm not a techie so does that mean there will be two motherboards? Then what's the graphics card to be used? The GForce 3 or the rumored Elsa card?<hr></blockquote>



    The nForce is currently an integrated motherboard solution supporting AMD processors. It has onboard sound and graphics solutions. People speculating about the nForce are really saying that there may be a similiar integrated nVidia based motherboard product for the G4/5.



    BTW, those motherboards also have AGP slots, so you have the option of using the built-in graphics capability, or adding in the aftermarket 3-d card of your choice for higher performance.



    The integrated solution would most likely show up in the new iMac.
  • Reply 102 of 141
    The nForce is interesting as a low-cost motherboard chipset. Good performance, but fairly low end if I recall correctly. Certainly its built-in graphics capabilities are only at geForce2 levels.



    What I was refering to was the next high end nVidia chipset, call it the nv30 (prototype name) or geForce4 (product name). The current geForce3 begins to expose some extremely powerful flexibility, the next generation is going to blow people's minds. On the Mac we still can't get access to the power of the geForce3, but if you look at some of the things being done on the XBox you'll see what is possible -- and this is just the beginning. 3DLabs' OpenGL 2.0 proposal hints at some of this as well... and I am desperately hoping that Apple gets serious about where OpenGL and 3D hardware are going.
  • Reply 103 of 141
    [quote]What I was refering to was the next high end nVidia chipset, call it the nv30 (prototype name) or geForce4 (product name). The current geForce3 begins to expose some extremely powerful flexibility, the next generation is going to blow people's minds. On the Mac we still can't get access to the power of the geForce3, but if you look at some of the things being done on the XBox you'll see what is possible -- and this is just the beginning. 3DLabs' OpenGL 2.0 proposal hints at some of this as well... and I am desperately hoping that Apple gets serious about where OpenGL and 3D hardware are going.[/QB]<hr></blockquote>



    Two questions:

    1) When might the GeForce4 come out? Is MWSF completely out of the question?

    2) What's so great about OpenGL 2.0?
  • Reply 104 of 141
    xypexype Posts: 672member
    [quote]Originally posted by Whisper:

    <strong>



    Two questions:

    1) When might the GeForce4 come out? Is MWSF completely out of the question?

    2) What's so great about OpenGL 2.0?</strong><hr></blockquote>



    The GeForce4 is rumored to come out this january and imho it will be at MWSF.



    OpenGL 2.0 is basically a new way to code 3D apps, it going away from the current technology which can not keep pace with the fast development of game graphics cards. Adding special "extensions" to OpenGL to accomodate all the new functions of the cards creates more and more of a mess of functions that only work with specific cards, more or less. OpenGL 2.0 would change the "call function" approach to a "universal shading language" one, iirc, which would simplify writing 3D games and applications even more.



    nForce is a nice chipset and quite fast, lots of people like it's sound integration which is quite good (5.1) and the network, bus, ram, cpu connection is solved nicely as well. the integrated gfx chip is geforce2mx only, but one is free to use any other agp card with it (and I think that also enables the use of two screens). it's a nice all-in-one package which would be ideal for a consumer machine. as far as i know it's amd/intel only now.
  • Reply 105 of 141
    paulpaul Posts: 5,278member
    [quote]Originally posted by xype:

    <strong>The GeForce4 is rumored to come out this january and imho it will be at MWSF. </strong><hr></blockquote>



    ummm I haven't read anything that suggested this... where?



    If it is to be announced in Jan, and it is ready for the show, it will probably be announced at MWSF, like last year... BUT if it isn't even close to completion (which makes more sence based on info available) I don't think we will hear much about it... I'd look for GeForce3 500i or whatever...



    -Paul
  • Reply 106 of 141
    xypexype Posts: 672member
    [quote]Originally posted by psantora:

    <strong>



    ummm I haven't read anything that suggested this... where?



    -Paul</strong><hr></blockquote>



    You can read about it

    <a href="http://www.xbitlabs.com/news/story.html?id=1009492812"; target="_blank">here</a> - but it's been delayed to february (and quite possibly march). My info was old, but if some high-end systems start shipping in february they might sport it already.
  • Reply 107 of 141
    [quote]Originally posted by macrumorzz:

    <strong>One more thing: the 58 mio transistors that have been rumored could be accurate. Usually I calculate 20 mio transistors for 256 kb L2 cache (although this depends a lot on the L2 design too). If the G5 should then have 512 kb L2 cache, leaving 18 mio transistors for all circuits and the L1 cache. Let's consider the G5 has 2x64 kb L1 cache, that should leave us with less than 8 mio transistors for all logic circuits.

    </strong><hr></blockquote>

    I think 20 million transistors for 256K cache is over the top, you have 256*1024*8*6 = 12,582,912 for the actual cells themselves, you need some for the tag lines and TLBs and miscellaneous logic, but these need not scale linearily with the cache size. I would be very surprised if they used more than 30 million total for the 512K L2 cache.

    As for the L1 cache, I very much doubt they will bump it up to 2*64K, as it would be extremely difficult to do this without increasing the latency, and low latency is what L1 cache is all about, the L2 gives you bandwidth, and main memory gives you storage.



    Also the rumours mention a very large die size for the G5, this would not come from increases in cache as these are very compact, there must be a considerable increase in logic.



    [quote]Originally posted by macrumorzz:

    <strong>

    Generally you can double the number of transistors when going from 32 to 64 bits, but the G5 is somewhat special. AltiVec transistors will not double, on the other hand some more circuits could be implemented (like ocean, RapidIO,...). This is rather hard to say as we don't know much about the units the G5 will use, neither about these technologies, but it *could* be correct.</strong><hr></blockquote>



    Only a few of the units will double transistor counts when going to 64 bits, mainly the integer ALUs and registers, which account for quite a small fraction of the total transistor count. The FPU, Altivec, cache control, and miscellaneous logic (decode/issue/rename etc.) will hardly be affected.



    OCEAN is an on-chip network, it is meant for embedded use, it won't be in the desktop chip. RapidIO may be, but I tend to believe that Hypertransport is more likely. Hypertransport would not necessarily imply an increase in transistor count, unless there are multiple busses, because it is replacing the old front side bus.



    I think a large part of the extra area and transistors will be in the memory system, an embedded memory controller, increased internal bus width between memory controller and L2 cache, and L2 cache to L1 cache would also eat up space. Without a major redesign of the core, I don't think adding a lot of transistors there would be effective, especially for integer code, there simply isn't enough instruction level parallelism to issue more instructions at once.



    Moving to 256 bit Altivec would eat up transistors, but Motorola have specifically said this is coming in G6. (shame)



    Of course, I wish I had a bit more hard evidence to go on. <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />



    Michael
  • Reply 108 of 141
    [quote]Originally posted by mmicist:

    <strong>



    Moving to 256 bit Altivec would eat up transistors, but Motorola have specifically said this is coming in G6. (shame)

    </strong><hr></blockquote>





    Exactly where did they say this? I certainly wouldn't complain about having longer vectors, but I would guess they'd need a 32-bit/64-bit mode style of switch to support old code. This is a rather ugly transition because its hard enough getting people to write for AltiVec -- getting them to support two versions of it is even worse!
  • Reply 109 of 141
    Hi folks,



    I'm convinced the G5 is ready for Jan. I can't tell you specifically how. I've learned quite a bit more about what was inside those boxes by talking to others who had access to them. While no one could 'see' it with their own eyes, there's a lot one can infer by how certain operations run.



    Many of the messages in this thread have hit very close to the mark in terms of technology. But there's more that you haven't quite figured out yet. And definitely a surprise or too.



    If Apple waits longer than January, it would HAVE to be for economic reasons - fear of economic slowdown etc..., high costs of manufacturing. Because the technology is ready. It's only a matter of TIMING...



  • Reply 110 of 141
    andersanders Posts: 6,523member
    [quote]Originally posted by fahre451:

    <strong>Hi folks,



    I'm convinced the G5 is ready for Jan. I can't tell you specifically how. I've learned quite a bit more about what was inside those boxes by talking to others who had access to them. While no one could 'see' it with their own eyes, there's a lot one can infer by how certain operations run.



    Many of the messages in this thread have hit very close to the mark in terms of technology. But there's more that you haven't quite figured out yet. And definitely a surprise or too.



    If Apple waits longer than January, it would HAVE to be for economic reasons - fear of economic slowdown etc..., high costs of manufacturing. Because the technology is ready. It's only a matter of TIMING...



    </strong><hr></blockquote>



    [quote]<strong>Posts: 2</strong><hr></blockquote>
  • Reply 111 of 141
    outsideroutsider Posts: 6,008member
    G5= RapidIO. NOT Hyper Transport. Sorry but just because Apple is part of the HTC, doesn't mean Motorola will change the basic interface to their flagship processor to something more inferior (HT).
  • Reply 112 of 141
    Hey if the guy is busy working and only gets NewYears off each year then he might surf over here, see all the commotion and decide to toss some legit info. Just because he has only 2 posts doesn't mean they aren't both the two most important ones on the entire board!
  • Reply 113 of 141
    I trust an insider who posts rarely more than someone who posts often. Why?



    More likely they're not just a regular member who already posts a lot.
  • Reply 113 of 141
    crusadercrusader Posts: 1,129member
    mmmm 64 bit
  • Reply 115 of 141
    pookjppookjp Posts: 280member
  • Reply 116 of 141
    [quote]Originally posted by Outsider:

    <strong>G5= RapidIO. NOT Hyper Transport. Sorry but just because Apple is part of the HTC, doesn't mean Motorola will change the basic interface to their flagship processor to something more inferior (HT).</strong><hr></blockquote>



    Could well be, but I don't think so. The rapidIO is not the basic interface for the processor core, although it is for 8540 chip.



    Hypertransport is, however, definitely not an inferior interface, it's a bit different, but currently outperforms rapidIO, though their performance limits are similar. The 8540 has a 2GB/s spec. for rapidIO badwidth, which amounts to 1GB/s in each direction. Existing HT links at 16bit width 400MHz double pumped give 1.6GB/s in each direction, and the chip to chip spec. is for an 800MHz double pumped bus.



    My suspicion is that the core for Apple's G5 is very different to the e500 core in Motorola's G5 class chips, those are optimised for high MIPs per Watt and MIPs per $, Apple's G5 is, I hope, just optimised for high MIPs.



    Michael
  • Reply 117 of 141
    Okay, you're right, 30 mio transistors for the L2 cache. No matter if the L1 cache is 2x32 or 2x64 kb, this leaves a lot of transistors for the ALU, AltiVec and the memory controller.



    If the G5 has no Ocean crossbar switch and no RapidIO, then it is probably not based on Motorola's e500 core. As far as I know IBM doesn't plan support for HT either, so this is - for me - some indication that Apple did most work on this chip. The G5 is neither a Motorola, nor an IBM processor, but an Apple product that will be fabbed by Moto, IBM, or even maybe AMD.



    I think that Apple couldn't design a CPU that complex all alone, and it would even be rather stupid to do so. Maybe they have chosen Motorola's 64 bit ALU, AltiVec core and memory controller and combined it with someone else's HT circuits, who knows.



    If this (or something comparable) is the case, then the G5 we will get will probably not be called "PowerPC 8500". Remember, the "8xx" and "8xxx" series are Motorola's embedded chips, and the G5 should originally have used the 75xx name scheme. The fact that Moto says the G5 will use the 85xx name scheme means shit if they're not the ones that have designed the chip. If Motorola has created Apple's G5, and if it's really so powerful, why have they removed the "microprocessor" category on their site? If the G5 is an Apple product it will be Apple giving this CPU a name, and why should they chose "8500" ?



    Something else: what about the Raycer Graphics deal? Some people said that Apple might have designed a 3D acceleration chip for Aqua. Wouldn't it be more efficient to implement a quite simple acceleration circuit right into the CPU? Not an entire 2D/3D graphics processor, of course (would be too complex), but only what's necessary to speed up Aqua and maybe to allow some new effects (like 3D effects when moving windows to the dock - I know, pretty silly stuff, but something M$ could never do then). The G5 would then have a "Velocity Engine", and... let's call it an "Aquadynamics Engine"
  • Reply 118 of 141
    mmicistmmicist Posts: 214member
    [quote]Originally posted by macrumorzz:

    <strong>Okay, you're right, 30 mio transistors for the L2 cache. No matter if the L1 cache is 2x32 or 2x64 kb, this leaves a lot of transistors for the ALU, AltiVec and the memory controller.



    If the G5 has no Ocean crossbar switch and no RapidIO, then it is probably not based on Motorola's e500 core. As far as I know IBM doesn't plan support for HT either, so this is - for me - some indication that Apple did most work on this chip. The G5 is neither a Motorola, nor an IBM processor, but an Apple product that will be fabbed by Moto, IBM, or even maybe AMD.

    </strong><hr></blockquote>



    Exactly. I had another look at the Motorola G5/e500 docs. This is an embedded core, it has fewer units than the 7450, no FPU, no Altivec, it is not the basis for Apple's G5 as it stands.

    I would be very suprised if AMD were fabbing for Apple, as they are still ramping their Dresden plant, and need all their capacity for their own chips at the moment.



    [quote]Originally posted by macrumorzz:

    <strong>

    I think that Apple couldn't design a CPU that complex all alone, and it would even be rather stupid to do so. Maybe they have chosen Motorola's 64 bit ALU, AltiVec core and memory controller and combined it with someone else's HT circuits, who knows.

    </strong><hr></blockquote>



    Again, this sounds right to me, rumours are that Motorola are fabbing the chip, but Apple are part of AIM, the PowerPC alliance, and have had input to earlier chip designs as well. I suspect they may also have had some collaboration with AMD, and we know AMD and Motorola have collaborated on process development.

    I don't know about the timescale, but something like the upcoming Hammer chips memory controller and Hypertransport switch and busses would be very nice with a PowerPC core. Even if the core were little more than a modified G4, this would still give awesome improvements in overall performance especially at the higher clock rates of which one would hope it would be capable.



    [quote]Originally posted by macrumorzz:

    <strong>

    If this (or something comparable) is the case, then the G5 we will get will probably not be called "PowerPC 8500". Remember, the "8xx" and "8xxx" series are Motorola's embedded chips, and the G5 should originally have used the 75xx name scheme. The fact that Moto says the G5 will use the 85xx name scheme means shit if they're not the ones that have designed the chip. If Motorola has created Apple's G5, and if it's really so powerful, why have they removed the "microprocessor" category on their site? If the G5 is an Apple product it will be Apple giving this CPU a name, and why should they chose "8500" ?

    </strong><hr></blockquote>



    I would'nt speculate on this, trying to second guess product names is a loser's game. Apple will just refer to it as the G5, I'm sure.





    [quote]Originally posted by macrumorzz:

    <strong>

    Something else: what about the Raycer Graphics deal? Some people said that Apple might have designed a 3D acceleration chip for Aqua. Wouldn't it be more efficient to implement a quite simple acceleration circuit right into the CPU? Not an entire 2D/3D graphics processor, of course (would be too complex), but only what's necessary to speed up Aqua and maybe to allow some new effects (like 3D effects when moving windows to the dock - I know, pretty silly stuff, but something M$ could never do then). The G5 would then have a "Velocity Engine", and... let's call it an "Aquadynamics Engine" </strong><hr></blockquote>



    Is possible , but I know nothing about it.

    One possibility did cross my mind. If Apple use the Hypertransport connection scheme from AMD's Hammer, there is little technical problem in putting both processors on the same motherboard, sharing memory and peripherals. Two distinct 64 bit chips in one computer, it will run damn nearly everything.



    Michael



  • Reply 119 of 141
    telomartelomar Posts: 1,804member
    [quote]Originally posted by macrumorzz:

    <strong>let's call it an "Aquadynamics Engine" </strong><hr></blockquote>



    lol. It wouldn't surprise me if Apple did give it a name like that should they do it
  • Reply 120 of 141
    razzfazzrazzfazz Posts: 728member
    [quote]Originally posted by The Mactivist:

    <strong>

    Hmmm.... also, about this 64 vs 32 thing. What kind of software would crunch 64 bit integers? 3d rendering perhaps? Some scientific program? Any ideas?

    </strong><hr></blockquote>



    I think 3D rendering mostly uses floats, not ints.

    Encryption does use large ints, but "large" usually means even more than 64 bits there.

    I think the main point about 64-bit-architectures is the fact that they allow for huge address space, and for efficient handling of associated 64 bit pointer arithmetic.



    Bye,

    RazzFazz
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