I agree -- Delivering this now is a bit questionable, however. I would expect to see more-or-less the current design moved to 90 nm first, before an increase in the integration level... late-2004 for a PBG5, I would expect to see such a SoC machine in that timeframe.
I'll make it a third agreement with Wizard69's take on this. Next week will be very revealing as to what we can expect to see coming from Apple in the near future. Compliments of IBM. Things are moving rapidly now, and what has already been released by IBM shows great hope for the future of Apple products.
None of us know the constraints which will dictate what we see released or when, but I will speculate that S on C won't be seen for some time, but what we will see RSN is:
Dual 1.8 130nm G5
Dual 2.0 130nm G5
Dual 2.5 90nm G5FX
In the Power Macs
followed by:
Single 1.6 90nm G5FX
Single 1.8 90nm G5FX
Single 2.0 90nm G5FX
in the NEW Macintosh
followed by:
Single 1.6 90nm G5FX
Single 1.8 90nm G5FX
Single 2.0 90nm G5FX
in Powerbooks
The time frame being this year, Winter, Spring, and Summer.
Seeing as the quote was made by the ASCI Division Manager, seems like you're right along with other people in this thread saying the same thing.
Question though, a couple of people have posted that they, their company at least, have already received G5 xServes, presumably with the 970FX, wouldn't this mean the initial run of xServers were using a 0.13µm controller, or were they made with initial non-production run parts. After all Mr. Manner did say they were just now starting to ship production run 0.09µm SOC parts.
Sorry for the run on sentence, but I wasn't an English major.
The G5 xServe uses a completely different controller than the PowerMac. They have more things integrated into xServe controller to accommodate additional functions (that bit of info was courtesy of an Apple employee at MWSF '04 that designed code for the xServe). And no, I didn't get them drunk. The employee saw where I used to work and shared the information freely, although with appropriate ambiguity.
Timing is an issue, such a implementation could be a year or more off. I do have to think though that they are working on such a chip right now.
As to the PowerMacs I see them stay just as they are for awhile longer. There are advantages and disadvantages to having local memory controllers. There is even a questions as to wether or not it ameks sense in the future to implement SMP outside the chip. An argurment could be made for implementing future machines as some sort of NUMA design with SMP chips for each section of the machine. There are a huge number of possibilities for the future, it will be intresting to see how things develop. Its to bad I don't have an electroincs engineering background, I'd be tempted to lead Apple to new frontiers
What I expect fo the first intgrated chip is something that implements differrent functionality with respect to Apples current northbridge. I'm thinking along the lines of the 440 class machines. Rip out the 440's I/O and replace it with Apple standard I/O. In other words a Hypertransport port or two, Firewire, USB and a few SATA ports, along with the memory controller of course. I think this is very doable at 90nm. You would most likely end up with far less power usage as you would get rid of a lot of buffering and level transistions. A PowerBook would be the ideal place to implement such a chip.
Thanks
Dave
Quote:
Originally posted by Programmer
I agree -- Apple finally has a CPU partner who is happy (and capable) of customizing processors for them, and they are using the partner to fab their system controller, and the processor is relatively small compared to what the process technology allows. An obvious step would be to move the custom Apple system controller on-die with the processor and use this for the non-PowerMac lines. This may eventually happen to the PowerMac too, but it is a harder thing to do with a multi-processor machine since then you end up with multiple system controllers. If they go multi-core then they might include the system controller on-chip as well.
Delivering this now is a bit questionable, however. I would expect to see more-or-less the current design moved to 90 nm first, before an increase in the integration level. Cheaper to hammer out the bugs that way. Given the comment from Apple exec a few months back about late-2004 for a PBG5, I would expect to see such a SoC machine in that timeframe.
Often publication lead times make it tricky to assign dates and chronological ordering to these events.
Makes sense, Thanks.
Quote:
Originally posted byMacJedai
The G5 xServe uses a completely different controller than the PowerMac. They have more things integrated into xServe controller to accommodate additional functions (that bit of info was courtesy of an Apple employee at MWSF '04 that designed code for the xServe). And no, I didn't get them drunk. The employee saw where I used to work and shared the information freely, although with appropriate ambiguity.
Also makes sense, Thanks.
I'm placing my bet on the nothbridge theory, not that I really know anything though.
Comments
Originally posted by Programmer
I agree -- Delivering this now is a bit questionable, however. I would expect to see more-or-less the current design moved to 90 nm first, before an increase in the integration level... late-2004 for a PBG5, I would expect to see such a SoC machine in that timeframe.
I'll make it a third agreement with Wizard69's take on this. Next week will be very revealing as to what we can expect to see coming from Apple in the near future. Compliments of IBM. Things are moving rapidly now, and what has already been released by IBM shows great hope for the future of Apple products.
None of us know the constraints which will dictate what we see released or when, but I will speculate that S on C won't be seen for some time, but what we will see RSN is:
Dual 1.8 130nm G5
Dual 2.0 130nm G5
Dual 2.5 90nm G5FX
In the Power Macs
followed by:
Single 1.6 90nm G5FX
Single 1.8 90nm G5FX
Single 2.0 90nm G5FX
in the NEW Macintosh
followed by:
Single 1.6 90nm G5FX
Single 1.8 90nm G5FX
Single 2.0 90nm G5FX
in Powerbooks
The time frame being this year, Winter, Spring, and Summer.
Fall for 3.0 at 90nm
Originally posted by Aphelion
Single 2.0 90nm G5FX
in Powerbooks
Sold right here and now 8)
1.8 for the 15"
1.6 for the 12"
Originally posted by rickag
Seeing as the quote was made by the ASCI Division Manager, seems like you're right along with other people in this thread saying the same thing.
Question though, a couple of people have posted that they, their company at least, have already received G5 xServes, presumably with the 970FX, wouldn't this mean the initial run of xServers were using a 0.13µm controller, or were they made with initial non-production run parts. After all Mr. Manner did say they were just now starting to ship production run 0.09µm SOC parts.
Sorry for the run on sentence, but I wasn't an English major.
The G5 xServe uses a completely different controller than the PowerMac. They have more things integrated into xServe controller to accommodate additional functions (that bit of info was courtesy of an Apple employee at MWSF '04 that designed code for the xServe). And no, I didn't get them drunk. The employee saw where I used to work and shared the information freely, although with appropriate ambiguity.
As to the PowerMacs I see them stay just as they are for awhile longer. There are advantages and disadvantages to having local memory controllers. There is even a questions as to wether or not it ameks sense in the future to implement SMP outside the chip. An argurment could be made for implementing future machines as some sort of NUMA design with SMP chips for each section of the machine. There are a huge number of possibilities for the future, it will be intresting to see how things develop. Its to bad I don't have an electroincs engineering background, I'd be tempted to lead Apple to new frontiers
What I expect fo the first intgrated chip is something that implements differrent functionality with respect to Apples current northbridge. I'm thinking along the lines of the 440 class machines. Rip out the 440's I/O and replace it with Apple standard I/O. In other words a Hypertransport port or two, Firewire, USB and a few SATA ports, along with the memory controller of course. I think this is very doable at 90nm. You would most likely end up with far less power usage as you would get rid of a lot of buffering and level transistions. A PowerBook would be the ideal place to implement such a chip.
Thanks
Dave
Originally posted by Programmer
I agree -- Apple finally has a CPU partner who is happy (and capable) of customizing processors for them, and they are using the partner to fab their system controller, and the processor is relatively small compared to what the process technology allows. An obvious step would be to move the custom Apple system controller on-die with the processor and use this for the non-PowerMac lines. This may eventually happen to the PowerMac too, but it is a harder thing to do with a multi-processor machine since then you end up with multiple system controllers. If they go multi-core then they might include the system controller on-chip as well.
Delivering this now is a bit questionable, however. I would expect to see more-or-less the current design moved to 90 nm first, before an increase in the integration level. Cheaper to hammer out the bugs that way. Given the comment from Apple exec a few months back about late-2004 for a PBG5, I would expect to see such a SoC machine in that timeframe.
Originally posted by Programmer
Often publication lead times make it tricky to assign dates and chronological ordering to these events.
Makes sense, Thanks.
Originally posted byMacJedai
The G5 xServe uses a completely different controller than the PowerMac. They have more things integrated into xServe controller to accommodate additional functions (that bit of info was courtesy of an Apple employee at MWSF '04 that designed code for the xServe). And no, I didn't get them drunk. The employee saw where I used to work and shared the information freely, although with appropriate ambiguity.
Also makes sense, Thanks.
I'm placing my bet on the nothbridge theory, not that I really know anything though.