Doesn't matter. Intel won't bring support of 800 MHz FSB until Santa Rosa and Crestline in early/middle 2007.
@JeffDM: As far as I can discern, the codenames don't have much to do with the place where the chips were designed, but rather use names from the same are for the same type of chip, no matter where they were developed.
Makes sense too! I will report that info. to Steve this evening.
@JeffDM: As far as I can discern, the codenames don't have much to do with the place where the chips were designed, but rather use names from the same are for the same type of chip, no matter where they were developed.
I'm not sure what you are saying.
What I meant is that when chips designed in the West Coast US, many of them bore the code names of rivers found in that region. Chips designed in Israel bore the names of places and people important to those in Israel.
It is very possible Intel will keep the name "Core Duo" and spill it accross all versions,
ie the Core Solo T1300 and the Core Duo T2600 are Yonah, so:
- Merom @ 1.83 Ghz would be "Core Duo T5600" (L2 2MB and FSB 667)
- Merom @ 2.33 Ghz would be "Core Duo T7600" (L2 4MB and FSB 667)
- Conroe @ 1.60 GHz would be "Core Duo E4200" (L2 2MB and FSB 800)
- Conroe @ 2.40 GHz would be "Core Duo E6600" (L2 4MB and FSB 1067)
- Woodcrest @ 3.33 GHz would be "Core Duo E8000 Xeon" (L2 4MB and FSB 1333)
All 64-bit Core will be dualcore minimum. No single core version.
The letter "T" is for a TDP between 25W and 49W, and "E" is for TDB > 50W.
The Pentium brand name has been retired, so no more CPUs with the names Pentium 4 or Pentium M after 2006. They've been replaced with the "Core" brand name. Merom and Conroe will indeed have the numbering convention you allude to.
In addition to E and T, there will also be L and U to signify TDPs of 15 and 5.5 Watts. The Core Duo L2300 (1.5 GHz) and L2400 (1.66 GHz) would make an iBook/Intel a sweet, thin, and long lasting laptop alright. Expensive chips though, who knows if Apple would be willing to eat the margin compared to the T2300 and the Core Solo.
The Xeon brand name has not been retired however. All Woodcrest CPUs would be branded as Xeon 51XX/Xeon MP 71xx processors.
How much difference will the SR chipset bring over a Napa (not including the common denominator merom cpu).. not just in performance, but improved battery life etc?
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
That's not something you can just decide to do partway through. The reason the G5's system bus was so fast was because of how the entire processor architecture was designed; it needed that bus speed to keep everything humming. Core doesn't need that as much, and only really gains higher FSB speeds on very high clock rates.
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
Intel prefers to use half-duplex buses, which by nature have various technical advantages but also the disadvantage of being limited to a lower frequency. Running the Intel FSB protocol at 1.9GHz (for a 3.8GHz processor) just doesn't work. The dual simplex point-to-point "buses" used by IBM, Apple, AMD, Microsoft, and Sony can be clocked much higher (~5GHz), but have inflexible bandwidth allocation.
Also, the clock rate of an FSB tells you nothing, because some are 16 bits wide and some are 64 bits wide. It's best to look at the throughput (in GB/s), where you see that Intel's latest FSB is actually faster than the G5's.
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
Intel's FSB is already damn close to "half the speed of the processor." No need to modify.
I'll need to write a 20-page dissertation about FSB conventions and false advertising to properly explain it. But, I'll try to be shorter than that.
A 2.5 GHz PPC 970mp has an FSB advertized as operating at 1.25 GHz. It actually doesn't run at the clock speed. It runs at 625 MHz double data rate. Moreover, the G5 bus is not a parallel bus like Intel's FSB is. The G5 bus consists of 2 32-bit (4 bytes) unidirectional serial buses, one going to the CPU the going away from the CPU, each operating at 625 MHz double data rate.
Information going one way is limited to 625 MHz * 4 bytes * 2 bytes/Hz = 5000 MB/s. This is the maximum bandwidth that can get to the processor. Since there are 2 unidirectional links that operate at the same time, one can advertize the bus as having a throughput rate of 10,000 MB/s.
In common FSB parlance, a FSB is thought of as a 64-bit parallel bus and single data rate per clock cycle. Information on this sort of bus can flow both directions, but only one direction at a time. For 10,000 MB/s bandwidth, this sort of bus would operate at 1.25 GHz. Hence, the G5 FSB is advertized as 1.25 GHz. [You'd rather have a real 1.25 GHz FSB.]
A 2.66 GHz Conroe will have a 1.066 GHz FSB and a 2.66 GHz Woodcrest will have a 1.33 GHz FSB, half that of the CPU! But as said earlier, the Intel FSB doesn't actually operate at 1.066 or 1.33 GHz. Those are advertized date rate equivalent numbers.
Intel's Conre/Woodcrest (really the Pentium-4 bus) runs quad data rate. For a 2.66 GHz Woodcrest with a 1.33 GHz FSB, the FSB actually runs at 333 MHz quad data rate. It's a 64-bit (8 bytes) parallel bus. So its data bandwidth is 333 MHz * 8 bytes * 4 bytes/Hz = 10,656 MB/s.
Same story, in common FSB parlance, a 1333 MHz FSB would yield 10,656 MB/s bandwidth. Hence, Intel advertizes a 1.33 GHz bus, not a 333 MHz one.
And if you haven't noticed, Woodcrest at 2.66 GHz has a FSB that runs at half the processor clock, 1.33 GHz!
As why they have to do this, maybe another post. I will say that it most situations, the Intel FSB is better than the G5 FSB. I think the G5 would perform better with Intel's FSB, let alone Intel on-chip cache. If the Conroe/Woodcrest FSB used the G5 bus, I'd say it really wouldn't help speed, it'll make it worse.
Now, Intel's existing FSB does have some issues for multi-socket systems. And it can probably only scale to 1.6 GHz data rates. Anything more, Intel will probably have to change it. Octo data rate FSB with on-chip PCIe x32 links for cache coherency traffic anyone?
How much difference will the SR chipset bring over a Napa (not including the common denominator merom cpu).. not just in performance, but improved battery life etc?
4+ GB main memory support.
800 MHz FSB.
802.11n wireless. (I think it is "n").
And the necessary power efficiency techniques so that 35 Watt TDP Merom using all those higher power goodies performs as well as Yonah/Napa.
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
I don't think the Core chips are memory starved, so it's not necessary to do that. The FSB would waste power if you have it set higher than necessary. Also, some G5 chips were set at a third the processor, see the iMac.
Contemplating to get either iMac/MacBook Pro once, it goes into 64bit Merom (and hopefully, OSX Leopard with XP virtualization) ... it will be great to see them in Jul/Aug 06!.
Contemplating to get either iMac/MacBook Pro once, it goes into 64bit Merom (and hopefully, OSX Leopard with XP virtualization) ... it will be great to see them in Jul/Aug 06!.
I am skeptical that Apple would use Itanium in their servers. It would require different code, meaning separate development costs to support it and Itanium is not that well suited for a low end server. Xeon makes much more sense, same code but scalable to more processors, more than enough for the XServes. Besides, Xeon is a workstation and server chip, Xeon DP might be found more in workstations, but Apple hasn't done a four socket server, so Xeon MP isn't necessary yet. It could be in the cards though, if Apple is serious about the enterprise market.
Contemplating to get either iMac/MacBook Pro once, it goes into 64bit Merom (and hopefully, OSX Leopard with XP virtualization) ... it will be great to see them in Jul/Aug 06!.
the Core Duo you mentioned is what the Meroms will be called too. They are codenamed Yonah. I doubt they will keep the MacBooks with the Yonah core very long before moving to Merom. The Xserve will use a Woodcrest Xeon, not an itanium. yes intel made the Itanium, but its is not an x86 compatible chip, and there isnt a version of OSX that can run on it.
Comments
Originally posted by Zandros
Doesn't matter. Intel won't bring support of 800 MHz FSB until Santa Rosa and Crestline in early/middle 2007.
@JeffDM: As far as I can discern, the codenames don't have much to do with the place where the chips were designed, but rather use names from the same are for the same type of chip, no matter where they were developed.
Makes sense too! I will report that info. to Steve this evening.
Originally posted by Zandros
@JeffDM: As far as I can discern, the codenames don't have much to do with the place where the chips were designed, but rather use names from the same are for the same type of chip, no matter where they were developed.
I'm not sure what you are saying.
What I meant is that when chips designed in the West Coast US, many of them bore the code names of rivers found in that region. Chips designed in Israel bore the names of places and people important to those in Israel.
Originally posted by Cosmos 1999
It is very possible Intel will keep the name "Core Duo" and spill it accross all versions,
ie the Core Solo T1300 and the Core Duo T2600 are Yonah, so:
- Merom @ 1.83 Ghz would be "Core Duo T5600" (L2 2MB and FSB 667)
- Merom @ 2.33 Ghz would be "Core Duo T7600" (L2 4MB and FSB 667)
- Conroe @ 1.60 GHz would be "Core Duo E4200" (L2 2MB and FSB 800)
- Conroe @ 2.40 GHz would be "Core Duo E6600" (L2 4MB and FSB 1067)
- Woodcrest @ 3.33 GHz would be "Core Duo E8000 Xeon" (L2 4MB and FSB 1333)
All 64-bit Core will be dualcore minimum. No single core version.
The letter "T" is for a TDP between 25W and 49W, and "E" is for TDB > 50W.
The Pentium brand name has been retired, so no more CPUs with the names Pentium 4 or Pentium M after 2006. They've been replaced with the "Core" brand name. Merom and Conroe will indeed have the numbering convention you allude to.
In addition to E and T, there will also be L and U to signify TDPs of 15 and 5.5 Watts. The Core Duo L2300 (1.5 GHz) and L2400 (1.66 GHz) would make an iBook/Intel a sweet, thin, and long lasting laptop alright. Expensive chips though, who knows if Apple would be willing to eat the margin compared to the T2300 and the Core Solo.
The Xeon brand name has not been retired however. All Woodcrest CPUs would be branded as Xeon 51XX/Xeon MP 71xx processors.
The Celeron brand name, I don't know.
Originally posted by hypoluxa
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
That's not something you can just decide to do partway through. The reason the G5's system bus was so fast was because of how the entire processor architecture was designed; it needed that bus speed to keep everything humming. Core doesn't need that as much, and only really gains higher FSB speeds on very high clock rates.
Originally posted by hypoluxa
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
Intel prefers to use half-duplex buses, which by nature have various technical advantages but also the disadvantage of being limited to a lower frequency. Running the Intel FSB protocol at 1.9GHz (for a 3.8GHz processor) just doesn't work. The dual simplex point-to-point "buses" used by IBM, Apple, AMD, Microsoft, and Sony can be clocked much higher (~5GHz), but have inflexible bandwidth allocation.
Also, the clock rate of an FSB tells you nothing, because some are 16 bits wide and some are 64 bits wide. It's best to look at the throughput (in GB/s), where you see that Intel's latest FSB is actually faster than the G5's.
Originally posted by hypoluxa
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
Intel's FSB is already damn close to "half the speed of the processor." No need to modify.
I'll need to write a 20-page dissertation about FSB conventions and false advertising to properly explain it. But, I'll try to be shorter than that.
A 2.5 GHz PPC 970mp has an FSB advertized as operating at 1.25 GHz. It actually doesn't run at the clock speed. It runs at 625 MHz double data rate. Moreover, the G5 bus is not a parallel bus like Intel's FSB is. The G5 bus consists of 2 32-bit (4 bytes) unidirectional serial buses, one going to the CPU the going away from the CPU, each operating at 625 MHz double data rate.
Information going one way is limited to 625 MHz * 4 bytes * 2 bytes/Hz = 5000 MB/s. This is the maximum bandwidth that can get to the processor. Since there are 2 unidirectional links that operate at the same time, one can advertize the bus as having a throughput rate of 10,000 MB/s.
In common FSB parlance, a FSB is thought of as a 64-bit parallel bus and single data rate per clock cycle. Information on this sort of bus can flow both directions, but only one direction at a time. For 10,000 MB/s bandwidth, this sort of bus would operate at 1.25 GHz. Hence, the G5 FSB is advertized as 1.25 GHz. [You'd rather have a real 1.25 GHz FSB.]
A 2.66 GHz Conroe will have a 1.066 GHz FSB and a 2.66 GHz Woodcrest will have a 1.33 GHz FSB, half that of the CPU! But as said earlier, the Intel FSB doesn't actually operate at 1.066 or 1.33 GHz. Those are advertized date rate equivalent numbers.
Intel's Conre/Woodcrest (really the Pentium-4 bus) runs quad data rate. For a 2.66 GHz Woodcrest with a 1.33 GHz FSB, the FSB actually runs at 333 MHz quad data rate. It's a 64-bit (8 bytes) parallel bus. So its data bandwidth is 333 MHz * 8 bytes * 4 bytes/Hz = 10,656 MB/s.
Same story, in common FSB parlance, a 1333 MHz FSB would yield 10,656 MB/s bandwidth. Hence, Intel advertizes a 1.33 GHz bus, not a 333 MHz one.
And if you haven't noticed, Woodcrest at 2.66 GHz has a FSB that runs at half the processor clock, 1.33 GHz!
As why they have to do this, maybe another post. I will say that it most situations, the Intel FSB is better than the G5 FSB. I think the G5 would perform better with Intel's FSB, let alone Intel on-chip cache. If the Conroe/Woodcrest FSB used the G5 bus, I'd say it really wouldn't help speed, it'll make it worse.
Now, Intel's existing FSB does have some issues for multi-socket systems. And it can probably only scale to 1.6 GHz data rates. Anything more, Intel will probably have to change it. Octo data rate FSB with on-chip PCIe x32 links for cache coherency traffic anyone?
Originally posted by gsxrboy
How much difference will the SR chipset bring over a Napa (not including the common denominator merom cpu).. not just in performance, but improved battery life etc?
4+ GB main memory support.
800 MHz FSB.
802.11n wireless. (I think it is "n").
And the necessary power efficiency techniques so that 35 Watt TDP Merom using all those higher power goodies performs as well as Yonah/Napa.
Originally posted by hypoluxa
Why doesn't Intel make their FSB's half the speed of the processor like IBM did with the G5? Doesn't that help with speed?
I don't think the Core chips are memory starved, so it's not necessary to do that. The FSB would waste power if you have it set higher than necessary. Also, some G5 chips were set at a third the processor, see the iMac.
MacBook, Mac mini - Core Duo
MacBook Pro - Merom
iMac - Conroe
Power Mac - Xeon (woodcrest)
XServe - Itanium (some form???)
Contemplating to get either iMac/MacBook Pro once, it goes into 64bit Merom (and hopefully, OSX Leopard with XP virtualization) ... it will be great to see them in Jul/Aug 06!.
Originally posted by shanmugam
I am interested to know whether Conroe in iMac???
MacBook, Mac mini - Core Duo
MacBook Pro - Merom
iMac - Conroe
Power Mac - Xeon (woodcrest)
XServe - Itanium (some form???)
Contemplating to get either iMac/MacBook Pro once, it goes into 64bit Merom (and hopefully, OSX Leopard with XP virtualization) ... it will be great to see them in Jul/Aug 06!.
I am skeptical that Apple would use Itanium in their servers. It would require different code, meaning separate development costs to support it and Itanium is not that well suited for a low end server. Xeon makes much more sense, same code but scalable to more processors, more than enough for the XServes. Besides, Xeon is a workstation and server chip, Xeon DP might be found more in workstations, but Apple hasn't done a four socket server, so Xeon MP isn't necessary yet. It could be in the cards though, if Apple is serious about the enterprise market.
Originally posted by shanmugam
I am interested to know whether Conroe in iMac???
MacBook, Mac mini - Core Duo
MacBook Pro - Merom
iMac - Conroe
Power Mac - Xeon (woodcrest)
XServe - Itanium (some form???)
Contemplating to get either iMac/MacBook Pro once, it goes into 64bit Merom (and hopefully, OSX Leopard with XP virtualization) ... it will be great to see them in Jul/Aug 06!.
the Core Duo you mentioned is what the Meroms will be called too. They are codenamed Yonah. I doubt they will keep the MacBooks with the Yonah core very long before moving to Merom. The Xserve will use a Woodcrest Xeon, not an itanium. yes intel made the Itanium, but its is not an x86 compatible chip, and there isnt a version of OSX that can run on it.