Generally a longer pipeline allows clock rate to scale better, but has a negative effect on performance at a given clock rate. There are many other factors in keeping a chip's pipelines all as full as possible, and the G5 will no doubt address those aggressively. Don't be disappointed if the G5's pipelines are "only" 10-14 stages long, that's plenty long enough. In the end what matters is how smokin' fast the chip runs the software.
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If the G5's pipeline is 10-14 stages long, and the Pentium 4's is something like 20?, then this would be a good thing, no? It seems like a good piece of engineering on Moto's part, because the G5 would be able to complete more instructions per clock cycle due to it's shorter pipeline (I know, oversimplified and probably wrong, but I'm no electrical engineer).
I think you misunderstood my original post, I was pointing out the short pipeline of the G5 relative to the Pentium 4 as being a good thing, not something to be disappointed about.
Thank you, Eskimo, I hadn't seen that before. It is interesting to note that AMD is using Moto's process technology -- so clearly the deficiences in the G4's clock rate are due to design issues in the G4. After all, the Athlon is on the same process and running @ 1.6 GHz.</strong><hr></blockquote>
Unfortunately no. Not to take anything away from the nice design job AMD did on the K7, while they share research and development of process technology their implementation of that technology is not the same. The word as I hear it from people who work for Motorola is that many of their high end designs just simply do not work when fabricated in their own fabs. They work just fine when they ship them out to someone like TSMC however. Obviously this infuriates the design group and management since they are losing valuable time and profit margins if they have to outsource like that. On the other hand from what I've been told Motorola has an aversion to change unless it involves reformulating their mission statement.
[quote]{I don't know enough to know if this is significant - are 200 MHz ASICs impressive or not?}
<hr></blockquote>
Could very well mean a 200MHz DDR type bus is possible from Apple. They design their own chipset ASICs, that is what those job postings you found are for.
Comments
Longer pipeline != better performance.
Generally a longer pipeline allows clock rate to scale better, but has a negative effect on performance at a given clock rate. There are many other factors in keeping a chip's pipelines all as full as possible, and the G5 will no doubt address those aggressively. Don't be disappointed if the G5's pipelines are "only" 10-14 stages long, that's plenty long enough. In the end what matters is how smokin' fast the chip runs the software.
<hr></blockquote>
If the G5's pipeline is 10-14 stages long, and the Pentium 4's is something like 20?, then this would be a good thing, no? It seems like a good piece of engineering on Moto's part, because the G5 would be able to complete more instructions per clock cycle due to it's shorter pipeline (I know, oversimplified and probably wrong, but I'm no electrical engineer).
I think you misunderstood my original post, I was pointing out the short pipeline of the G5 relative to the Pentium 4 as being a good thing, not something to be disappointed about.
[ 01-18-2002: Message edited by: Junkyard Dawg ]</p>
<strong>
Thank you, Eskimo, I hadn't seen that before. It is interesting to note that AMD is using Moto's process technology -- so clearly the deficiences in the G4's clock rate are due to design issues in the G4. After all, the Athlon is on the same process and running @ 1.6 GHz.</strong><hr></blockquote>
Unfortunately no. Not to take anything away from the nice design job AMD did on the K7, while they share research and development of process technology their implementation of that technology is not the same. The word as I hear it from people who work for Motorola is that many of their high end designs just simply do not work when fabricated in their own fabs. They work just fine when they ship them out to someone like TSMC however. Obviously this infuriates the design group and management since they are losing valuable time and profit margins if they have to outsource like that. On the other hand from what I've been told Motorola has an aversion to change unless it involves reformulating their mission statement.
[quote]{I don't know enough to know if this is significant - are 200 MHz ASICs impressive or not?}
<hr></blockquote>
Could very well mean a 200MHz DDR type bus is possible from Apple. They design their own chipset ASICs, that is what those job postings you found are for.