Quite sure I never said that sign language fit a dictionary's definition of "speech", so STFU.
I pointed out that deaf people use sign language, and therefore the signature was correct in its assumption. It is also correct that deaf people have the ability to speak verbally.
Get a clue.
(Sorry for the rant... I hate it when people post stupid things )
I also think that both the hype around the new cache and new motherboard graphs on Apples site are only a marketing move to make us feel there's something new, where there isn't.
The motherboard is still the same, it's nothing new as far as we can tell by now, the 215MB/sec PCI bus was there before, that's an UMA 1.0 feature already, so it's clear that it's also in UMA 1.5 what we have now.
The Cache also seems to be the same, DDR-SRAM before, and now they say it's DDR-SDRAM, which most certainly is wrong. Caches traditionally are made of SRAMs, not DRAMs, because of latency and transistor count (being higher for DRAMs). That cache is probably the second-msot expensive part of the PowerMacs, and I'm quite sure it's actually SRAM and not SDRAM.
UMA 2.0 has been rumored around for years now, and yet we still have to see it. Think MWNY, either for the G4 or the G5.
<strong>The Cache also seems to be the same, DDR-SRAM before, and now they say it's DDR-SDRAM, which most certainly is wrong. Caches traditionally are made of SRAMs, not DRAMs, because of latency and transistor count (being higher for DRAMs). That cache is probably the second-msot expensive part of the PowerMacs, and I'm quite sure it's actually SRAM and not SDRAM.
</strong><hr></blockquote>
I agree that it's most likely a typo, but you're wrong on the transistor count. An SRAM cell actually needs more components than a DRAM one, this is why SRAM is both more expensive and only available in comparatively small capacities. The big advantage to SRAM is that it is, well, static, and as such doesn't need refresh cycles (and thus draws less power and is faster).
One can argue that Apple will need this headroom with the G4s for future iMacs and iBooks/PowerBook while the PowerMacs will get the G5s.</strong><hr></blockquote>
I agree. I don't know why people keep assuming that G5s can't be imminent because the G4 still has legs. As the G3 was relegated to Powerbook first and later the i Mac and Book, so too would the top of the line G4 to the Powerbook once the 5 goes to Pro line.
The timing seems quite favorable for the Top of line G4 going into the Powerbook products as its die size and energy requirements are being revised probably as we speak. Moreover, I am sure it would be sometime before we see a G5 in anything other than a desktop system, let alone a notebook whenever it hits the channel.
Actually if you think about it, if Apple were to drop the 7460 or whatever the low power, small die sized G4 into the Powerbook @ 1+ GHz and being that the 1+ GHz G3s (destined for iBook) from IBM have been waiting on Big brother to catch up, Apple would suddenly have matched clock for clock in both the Pro- and Sub- notebook catagories alongside AMD and Intel. The 1 and 1.2 Durons were just released this or last week wasn't it.
<strong>It's not impossible that Apple could have a substantially faster Powermac in the works that doesn't include a G5, and since the eweek article doesn't mention the G5, I don't see how the inference should be automatic that this guy's "sources" must be testing G5 prototypes.</strong><hr></blockquote>
It's not impossible, but I tend to think it's unlikely. Remember the claims we've heard: these test systems allegedly wipe the floor with a dual Athlon box, beating it handily. I referred to the mystery system as the G5 because that, supposedly, is the chip that's going to blow the doors off of any Mac currently available. If these rumors of incredible performance turn out to be for a G4 system, fine and dandy, but there's been nothing to suggest that G4s are in line for that kind of performance boost.
<strong>"...triple the performance of the current systems' 133MHz system bus..."
That seems pretty clearly directed at the system bus, not the system itself and yes that IS about 400MHz...
Time for Dorsal to contact us again.</strong><hr></blockquote>
There's no need to be a Dorsal to know that only the G5 (and NOT the G4) will support 400Mhz system-bus. the specs for the 8540 (which is a G5-class processor) looks like that: Rapid IO system bus up to 500Mhz!
however - this has nothing to do with DDR-memory bus. the 8540 again has an extra DDR-Memory controllor built in for 333Mhz DDR Ram... the 4 times 133Mhz system bus can't be the 266 or 333Mhz DDR Ram speeds....
Two Things:
1) The G4 has no support for normal 333Mhz DDR memory - just cache....
The G5 has!
2) Only the G5 with RapidIO can run a system bus with 400Mhz !!!
Well after further review, I think this guy is fairly legit, NMR or not.
Based on what I've found out is that this guy is *not* using rumor sites or places like the Register as his "eyewitnesses." I think he has first-hand relationships with people who have tested the G5 boxes and knows basically the types of technologies that will come with them, though not what configuration as he alluded to in the article.
We shall see I guess. Even if someone has information on prototype machines, that doesn't mean the CPU therein or other technologies therein are ready to be mass-produced anytime soon. I hope so though. It would truly be a nice surprise to have Apple floor us with a truly "Pentium / Athlon - crushing" G5 before summer is out. Spring even.
I'd buy one in a heartbeat if the lower end model had DP, DDR and more USB / Firewire ports than the current models. I don't even need USB 2 or 800Mbps Firewire, as there are few devices out there that could fully utilize their bandwidth anyway. Most of the good Firewire film scanners and such operate at less than 2/3 of IEEE 1394.b's bandwidth as best I can tell.
2) Only the G5 with RapidIO can run a system bus with 400Mhz !!!
The G4 NOT
</strong><hr></blockquote>
Keep in mind that, in current PowerMacs, the G4s system bus is only a bottleneck because all memory accesses pass through it.
Since the G5 supposedly has the memory controller on chip already, all that would go through the RapidIO port is I/O traffic (i.e. FireWire, Ethernet, USB, sound, ...).
Thus, RapidIO bandwidth would hardly have any impact on performance at all beyond the point where it can handle all the I/O traffic (which is much less than that caused by memory accesses).
Hmm, that brings up an interesting question. If the G5 has a memory controller on die then how would they measure the system bus? The speed of RIO to the main controller or the speed between memory controller and CPU core?
<strong>Hmm, that brings up an interesting question. If the G5 has a memory controller on die then how would they measure the system bus? The speed of RIO to the main controller or the speed between memory controller and CPU core?</strong><hr></blockquote>
A system bus is generally considered the part outside of the chip. On-chip busses are generally really really fast so the interesting one to discuss is the interface between the chip and the rest of the mobo.
Its not clear to me whether the G5 communicates with the memory via RapidIO or a dedicated bus out from the memory controller. I had assumed it would all go through the RapidIO (or HyperTransport) system.
Comments
[QB][/QB]<hr></blockquote>
Glurx-
Quite sure I never said that sign language fit a dictionary's definition of "speech", so STFU.
I pointed out that deaf people use sign language, and therefore the signature was correct in its assumption. It is also correct that deaf people have the ability to speak verbally.
Get a clue.
(Sorry for the rant... I hate it when people post stupid things
The motherboard is still the same, it's nothing new as far as we can tell by now, the 215MB/sec PCI bus was there before, that's an UMA 1.0 feature already, so it's clear that it's also in UMA 1.5 what we have now.
The Cache also seems to be the same, DDR-SRAM before, and now they say it's DDR-SDRAM, which most certainly is wrong. Caches traditionally are made of SRAMs, not DRAMs, because of latency and transistor count (being higher for DRAMs). That cache is probably the second-msot expensive part of the PowerMacs, and I'm quite sure it's actually SRAM and not SDRAM.
UMA 2.0 has been rumored around for years now, and yet we still have to see it. Think MWNY, either for the G4 or the G5.
G-News
<strong>The Cache also seems to be the same, DDR-SRAM before, and now they say it's DDR-SDRAM, which most certainly is wrong. Caches traditionally are made of SRAMs, not DRAMs, because of latency and transistor count (being higher for DRAMs). That cache is probably the second-msot expensive part of the PowerMacs, and I'm quite sure it's actually SRAM and not SDRAM.
</strong><hr></blockquote>
I agree that it's most likely a typo, but you're wrong on the transistor count. An SRAM cell actually needs more components than a DRAM one, this is why SRAM is both more expensive and only available in comparatively small capacities. The big advantage to SRAM is that it is, well, static, and as such doesn't need refresh cycles (and thus draws less power and is faster).
Bye,
RazzFazz
[ 01-31-2002: Message edited by: RazzFazz ]</p>
I hope Apple will correct that too
G-News
<strong>
One can argue that Apple will need this headroom with the G4s for future iMacs and iBooks/PowerBook while the PowerMacs will get the G5s.</strong><hr></blockquote>
I agree. I don't know why people keep assuming that G5s can't be imminent because the G4 still has legs. As the G3 was relegated to Powerbook first and later the i Mac and Book, so too would the top of the line G4 to the Powerbook once the 5 goes to Pro line.
The timing seems quite favorable for the Top of line G4 going into the Powerbook products as its die size and energy requirements are being revised probably as we speak. Moreover, I am sure it would be sometime before we see a G5 in anything other than a desktop system, let alone a notebook whenever it hits the channel.
Actually if you think about it, if Apple were to drop the 7460 or whatever the low power, small die sized G4 into the Powerbook @ 1+ GHz and being that the 1+ GHz G3s (destined for iBook) from IBM have been waiting on Big brother to catch up, Apple would suddenly have matched clock for clock in both the Pro- and Sub- notebook catagories alongside AMD and Intel. The 1 and 1.2 Durons were just released this or last week wasn't it.
[ 01-31-2002: Message edited by: ArkAngel ]
[ 01-31-2002: Message edited by: ArkAngel ]</p>
<strong>It's not impossible that Apple could have a substantially faster Powermac in the works that doesn't include a G5, and since the eweek article doesn't mention the G5, I don't see how the inference should be automatic that this guy's "sources" must be testing G5 prototypes.</strong><hr></blockquote>
It's not impossible, but I tend to think it's unlikely. Remember the claims we've heard: these test systems allegedly wipe the floor with a dual Athlon box, beating it handily. I referred to the mystery system as the G5 because that, supposedly, is the chip that's going to blow the doors off of any Mac currently available. If these rumors of incredible performance turn out to be for a G4 system, fine and dandy, but there's been nothing to suggest that G4s are in line for that kind of performance boost.
<strong>"...triple the performance of the current systems' 133MHz system bus..."
That seems pretty clearly directed at the system bus, not the system itself and yes that IS about 400MHz...
Time for Dorsal to contact us again.</strong><hr></blockquote>
There's no need to be a Dorsal to know that only the G5 (and NOT the G4) will support 400Mhz system-bus. the specs for the 8540 (which is a G5-class processor) looks like that: Rapid IO system bus up to 500Mhz!
however - this has nothing to do with DDR-memory bus. the 8540 again has an extra DDR-Memory controllor built in for 333Mhz DDR Ram... the 4 times 133Mhz system bus can't be the 266 or 333Mhz DDR Ram speeds....
Two Things:
1) The G4 has no support for normal 333Mhz DDR memory - just cache....
The G5 has!
2) Only the G5 with RapidIO can run a system bus with 400Mhz !!!
The G4 NOT
greets,
krassy
Based on what I've found out is that this guy is *not* using rumor sites or places like the Register as his "eyewitnesses." I think he has first-hand relationships with people who have tested the G5 boxes and knows basically the types of technologies that will come with them, though not what configuration as he alluded to in the article.
We shall see I guess. Even if someone has information on prototype machines, that doesn't mean the CPU therein or other technologies therein are ready to be mass-produced anytime soon. I hope so though. It would truly be a nice surprise to have Apple floor us with a truly "Pentium / Athlon - crushing" G5 before summer is out. Spring even.
I'd buy one in a heartbeat if the lower end model had DP, DDR and more USB / Firewire ports than the current models. I don't even need USB 2 or 800Mbps Firewire, as there are few devices out there that could fully utilize their bandwidth anyway. Most of the good Firewire film scanners and such operate at less than 2/3 of IEEE 1394.b's bandwidth as best I can tell.
[ 01-31-2002: Message edited by: Moogs ? ]</p>
<strong>
2) Only the G5 with RapidIO can run a system bus with 400Mhz !!!
The G4 NOT
</strong><hr></blockquote>
Keep in mind that, in current PowerMacs, the G4s system bus is only a bottleneck because all memory accesses pass through it.
Since the G5 supposedly has the memory controller on chip already, all that would go through the RapidIO port is I/O traffic (i.e. FireWire, Ethernet, USB, sound, ...).
Thus, RapidIO bandwidth would hardly have any impact on performance at all beyond the point where it can handle all the I/O traffic (which is much less than that caused by memory accesses).
Bye,
RazzFazz
<strong>Hmm, that brings up an interesting question. If the G5 has a memory controller on die then how would they measure the system bus? The speed of RIO to the main controller or the speed between memory controller and CPU core?</strong><hr></blockquote>
A system bus is generally considered the part outside of the chip. On-chip busses are generally really really fast so the interesting one to discuss is the interface between the chip and the rest of the mobo.
Its not clear to me whether the G5 communicates with the memory via RapidIO or a dedicated bus out from the memory controller. I had assumed it would all go through the RapidIO (or HyperTransport) system.