RIO and HT? Are you sure you know what you're talking about?
<hr></blockquote>
Yes I do, After reading my "Long text about RIO & HT" do you? Or was that a bit to technical for you?
[quote]Originally posted by RazzFazz:
Well, my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant.<hr></blockquote>
What about fast paged interleaved memory? That's a little mainframe trick that would do wonders for memory throughtput and latency. Let's have all three and get triple redundancy. Throw in liquid nitrogen cooling and overclock those four puppys to 6 GHz
My post was in response to Outsider's comment below, and the fast paged memory thing was put in to show (with a little bit of light sarcasm) that there are several solutions to his problem with Quads
[quote]Originally posted by Outsider
Dude, a quad G4 machine on a 133MHz MPX bus is about as useful as a 5 headed race horse with 3 legs.<hr></blockquote>
RazFaz, you obviously don't know what I'm talking about, and that's fine - just get an education. But when you say that you don't think that I know what I'm talking about I do take offense. You missed my point. Outsider was making a different point , you were making an attack. If you want to have a War of Wits with me about what I know or don't know be advised that you are bringing a knife to a gun fight. Bye Bye RatFiz
Me dumb, so don't get too angry, but here's an idea. What if Apple could make the caches bigger and faster, yet again, in liu of a significntly faster bus? Apple seems to be conservative, which is fine by me if the machines come with rock solid stability.
So, while Intel and AMD move to 533/1066 Rambus and PC2700/DDR2, Could Apple get similar performance from DDR266 ram and a giant whopper of a fast cache on each proc? Say 512KB of L1 on chip and 4-8MB of L2 on each daughtercard. Perhaps using even faster memory like SRAM (or the cheaper T1 SRAM that we find in GameCube)
Would it be possible to engineer a memory controller to use regular 168pin Dimms in Pairs (like RAID in concept) to effectively double to performance of 266Mhz Ram, without going to newer RAM types. You'd have to plug chips in in pairs, but with the costs of RAM beig pretty decent these days, I don't see it as much of a problem.
Yes I do, After reading my "Long text about RIO & HT" do you? Or was that a bit to technical for you?
</strong><hr></blockquote>
Actually, it wasn't. It also in no way addressed my point about using HT and RIO at the same time would be redundant.
Instead, you also copy'n'pasted technical details that aren't even in any way related to the points in question (or what do, in your opinion, the different layers have to do with the relation between RapidIO and HyperTransport?), and that fact alone makes me doubt you did actually more than just copy and paste here at all.
[quote]<strong>
What about fast paged interleaved memory? That's a little mainframe trick that would do wonders for memory throughtput and latency.
</strong><hr></blockquote>
... and has absolutely nothing to do with my point about having RapidIO and HyperTransport both at once.
[quote]<strong>Let's have all three and get triple redundancy. Throw in liquid nitrogen cooling and overclock those four puppys to 6 GHz
</strong><hr></blockquote>
This doesn't make a lot of sense. I suggest you go <a href="http://www.extremetech.com/article/0,3396,s=1005&a=21813,00.asp"; target="_blank">here</a> and read up on the aspects of RapidIO and HyperTransport, and why having both of them inside the same system is pretty much equivalent to having both EV6 (Athlon-style) and GTL+ (PentiumIII-style) front side buses at once in an x86 processor.
[quote]<strong>
My post was in response to Outsider's comment below, and the fast paged memory thing was put in to show (with a little bit of light sarcasm) that there are several solutions to his problem with Quads
</strong><hr></blockquote>
Look, we all agree that, in case the G5 does not have an integrated memory controller, RapidIO or HyperTransport will facilitate use of high-speed memory technology. All I'm saying is that there's zero advantage in putting both of them into a system at the same time.
[quote]<strong>RazFaz, you obviously don't know what I'm talking about, and that's fine - just get an education.</strong><hr></blockquote>
Look at the post I replied to: "Actually I was thinking it would use fast paged interleaved memory with RapidIO & HyperTransport".
Now, go to the site I linked to above, read it, understand it, realize that RIO and HT are basically two ways of doing pretty much the same thing, and that it would be futile to use them both concurrently in one system.
[quote]<strong>But when you say that you don't think that I know what I'm talking about I do take offense.</strong><hr></blockquote>
Feel free to prove me wrong.
Just enlighten me as to why, in your opinion, using both interconnection methods at once is technically feasible or even a good idea.
[quote]<strong>You missed my point. Outsider was making a different point , you were making an attack.</strong><hr></blockquote>
No, I did not. I did understand what you were trying to say, and then went on and (admittedly maybe not in the most polite way in the world) told you that your proposal, in my opinion, technically doesn't make a lot of sense for the reasons pointed out above. Feel free to show me how it does.
[quote]<strong>If you want to have a War of Wits with me about what I know or don't know be advised that you are bringing a knife to a gun fight. Bye Bye RatFiz</strong><hr></blockquote>
<strong>So, while Intel and AMD move to 533/1066 Rambus and PC2700/DDR2, Could Apple get similar performance from DDR266 ram and a giant whopper of a fast cache on each proc? Say 512KB of L1 on chip and 4-8MB of L2 on each daughtercard.
</strong><hr></blockquote>
This setup would be faster in some situations (where a significant part of the working set fits inside those large caches, but does not fit into the smaller ones), but at the same time be slower in others (streaming data, for example). It all depends on what you want to do.
[quote]<strong>
Would it be possible to engineer a memory controller to use regular 168pin Dimms in Pairs (like RAID in concept) to effectively double to performance of 266Mhz Ram, without going to newer RAM types.</strong><hr></blockquote>
That's what was referred to as bank interleaving earlier on.
Here's another question. What would be a practical limit for L2 caches on a desktop machine? I suppose a cache needs control circuitry on the chip (even if the cache is off chip) so that at some point it just gets too expensive/difficult to make the cache any bigger. Are we near that limit already, bearing in mind that whatever arrangement would have to fit in a line-up not more expensive than the current one. I remember reading about T1 SRAM a few weeks back: it's supposed to offer most of the benefit of true SRAM but remain much cheaper to produce. Would this make a good candidate for an big L2 cache? Supposedly the graphics chip in a Gamecube has a 14MB T1 SRAM cache that offers huge bandwidth to the graphics chip. Can it work for a CPU?
So, would most people be happy with a new Mobo featuring four interleaved 168 pin 266Mhz DDR dimms, and big (fast) L2 caches on each proc?
It sounds plenty fast to me, but then again I know not of what I speak.
Actually I was thinking it would use fast paged interleaved memory with RapidIO & HyperTransport - and that would be an 8 legged horse with a head at both ends
<hr></blockquote></strong>
[sarcasm]
Interleaved memory = 8 legs (in a quad CPU system)
RIO & HT = 2 heads on the same horse
[/sarcasm]
I was making a point (to Outsider) that there are many ways to address the issue of bus speed and bandwidth. (60 in the link you provided). If you didn't then, nor don't now, understand that I wasn't seriously suggesting that my thoughts be applied literally and simultaneously to a Quad G4 motherboard, then I guess that I'll hop on my two headed horse and ride off into the sunset (or into the dawn, depending on bus arbitration).
I'll restate & rewrite my original point for clarity, and to bring the issues back to the topic of this thread:
G4 "tweaks and revs ... when and how?
Apple could release a quad G4 with enhanced IO (take your pick) and they could do it tomorrow, or could have done it last year. In the Architosh survey 55% of high end pro users want quad G4's and want it now, and consider $5K as a reasonable price to pay for such a beast.
You were rude dude, you don't get it, and yet you keep beating a dead horse.
Interleaved memory = 8 legs (in a quad CPU system)
RIO & HT = 2 heads on the same horse
[/sarcasm]
</strong><hr></blockquote>
So if the whole "RIO & HT" thing did not mean "both at once", and I just don't share your sense of humour, I wonder why you didn't just point that fact out after I said the following:
"Well, my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant."
From how I understood your post (and mis-understood your humour), it technically didn't make a lot of sense to me, so I asked "Are you sure you know what you're talking about?".
But instead of pointing out my lack of humour, you first post technical details about RIO and HT. Though technically correct, they didn't address the point I was questioning, so I replied stating explicitly that "my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant."
In response, you again didn't point out that I was obviously just not getting your joke / humour / sarcasm, but instead resorted to using such incredibly funny remarks as "RatFiz" (who's being rude now, again?).
[quote]<strong>You were rude dude, you don't get it, and yet you keep beating a dead horse.
</strong><hr></blockquote>
So instead of just pointing out my mistake, being even more rude seems like a good choice to you?
Well, whatever.
In case I really was just unable to follow your sense of humour, I hereby apologize, and suggest we just get back on topic.
So instead of just pointing out my mistake, being even more rude seems like a good choice to you?
Well, whatever.
In case I really was just unable to follow your sense of humour, I hereby apologize, and suggest we just get back on topic.
Bye,
RazzFazz
</strong><hr></blockquote>
Well, it wasn't humor exactly, and if I had been more careful in my phrasing (ie put an OR in place of the &) I would have been technically correct and we would have had harmony. And I too resorted to rudeness and for that I apologize as well. By the way, the link about RIO & HT you gave was great and I read it with interest, Thank You.
Do you think that there is good chances to see a new mobo for MWNY. Everybody seems to wait a ddr mobo (or better).
Knowing the efficiency of the apple's Engineer to deliver the best of a technology, i think that this mobo will rock.
The next G4 will be 0,15 SOI based (all we know about the future roadmap of Motorola is that point), a 20 % to 30 % increase in speed sounds logical. As the programmer has said, if there is DDR ram the L3 cache is less interesting. So there might be a derived version of the 7455 with DDR memory controler, 512 K L2 and no L3 . Speed of 1,133 ghz to 1,4 ghz (if you supposed that the 7455 is able to go at 1,1 ghz without too many problems).
But if this new mobo is release for MWNY , it means that we will have to wait for the G5 an another year. Apple don't make mobo for only 6 months of live.
Hmm, I wonder if Apple has plans for it... A little bump between now and MWNY would be nice. 1133, 1000 and 867.
edit: OOPS. Just found out that all multipliers on a 7455 after 8 are whole; no half multipliers. 7.5 is the last half multiplier (1GHz)... the next one is 8x (1.066GHz) and then 9x (1.2GHz)... all the way up to the maximum multiplier, 16x (2.133GHz)
Reading the specificiation of the 7410 comparing to the 7450, there is a lot of difference, for sure Intel will have said that the 7450 is the G5 : different pipeline bus, improved altivec unit, four integer unit instead two, gestion of L3 cache.(eleven exucutions unit instead of 8)
Difference between a P2 and P3 : just SSE instructions.
so an improved G4 will be perfect for me, whatever is name.
One weird thing about that 1100MHz G4 part is what bus speed are they basing that figure on? 100MHz? Possibly but that's kinda odd seeing at the 1000 part is a 133mhz bus part. So the figures I com up with are 137.5, 146.6, 157.1, 169.2, 183.3, and 200MHz. 200MHz is a famililiar number because it's the same as the maximum bus speed of the 750FX.
<strong>One weird thing about that 1100MHz G4 part is what bus speed are they basing that figure on? 100MHz? Possibly but that's kinda odd seeing at the 1000 part is a 133mhz bus part. So the figures I com up with are 137.5, 146.6, 157.1, 169.2, 183.3, and 200MHz. 200MHz is a famililiar number because it's the same as the maximum bus speed of the 750FX.</strong><hr></blockquote>
perhaps this chips are selled for the moment for the high embedded market. Mot does not make a lot of publicity about this 1,1 ghz chip, they just talk about a 1 hgz chip.
Comments
RIO and HT? Are you sure you know what you're talking about?
<hr></blockquote>
Yes I do, After reading my "Long text about RIO & HT" do you? Or was that a bit to technical for you?
[quote]Originally posted by RazzFazz:
Well, my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant.<hr></blockquote>
What about fast paged interleaved memory? That's a little mainframe trick that would do wonders for memory throughtput and latency. Let's have all three and get triple redundancy. Throw in liquid nitrogen cooling and overclock those four puppys to 6 GHz
My post was in response to Outsider's comment below, and the fast paged memory thing was put in to show (with a little bit of light sarcasm) that there are several solutions to his problem with Quads
[quote]Originally posted by Outsider
Dude, a quad G4 machine on a 133MHz MPX bus is about as useful as a 5 headed race horse with 3 legs.<hr></blockquote>
RazFaz, you obviously don't know what I'm talking about, and that's fine - just get an education. But when you say that you don't think that I know what I'm talking about I do take offense. You missed my point. Outsider was making a different point , you were making an attack. If you want to have a War of Wits with me about what I know or don't know be advised that you are bringing a knife to a gun fight. Bye Bye RatFiz
So, while Intel and AMD move to 533/1066 Rambus and PC2700/DDR2, Could Apple get similar performance from DDR266 ram and a giant whopper of a fast cache on each proc? Say 512KB of L1 on chip and 4-8MB of L2 on each daughtercard. Perhaps using even faster memory like SRAM (or the cheaper T1 SRAM that we find in GameCube)
Would it be possible to engineer a memory controller to use regular 168pin Dimms in Pairs (like RAID in concept) to effectively double to performance of 266Mhz Ram, without going to newer RAM types. You'd have to plug chips in in pairs, but with the costs of RAM beig pretty decent these days, I don't see it as much of a problem.
<strong>
Yes I do, After reading my "Long text about RIO & HT" do you? Or was that a bit to technical for you?
</strong><hr></blockquote>
Actually, it wasn't. It also in no way addressed my point about using HT and RIO at the same time would be redundant.
Instead, you also copy'n'pasted technical details that aren't even in any way related to the points in question (or what do, in your opinion, the different layers have to do with the relation between RapidIO and HyperTransport?), and that fact alone makes me doubt you did actually more than just copy and paste here at all.
[quote]<strong>
What about fast paged interleaved memory? That's a little mainframe trick that would do wonders for memory throughtput and latency.
</strong><hr></blockquote>
... and has absolutely nothing to do with my point about having RapidIO and HyperTransport both at once.
[quote]<strong>Let's have all three and get triple redundancy. Throw in liquid nitrogen cooling and overclock those four puppys to 6 GHz
</strong><hr></blockquote>
This doesn't make a lot of sense. I suggest you go <a href="http://www.extremetech.com/article/0,3396,s=1005&a=21813,00.asp"; target="_blank">here</a> and read up on the aspects of RapidIO and HyperTransport, and why having both of them inside the same system is pretty much equivalent to having both EV6 (Athlon-style) and GTL+ (PentiumIII-style) front side buses at once in an x86 processor.
[quote]<strong>
My post was in response to Outsider's comment below, and the fast paged memory thing was put in to show (with a little bit of light sarcasm) that there are several solutions to his problem with Quads
</strong><hr></blockquote>
Look, we all agree that, in case the G5 does not have an integrated memory controller, RapidIO or HyperTransport will facilitate use of high-speed memory technology. All I'm saying is that there's zero advantage in putting both of them into a system at the same time.
[quote]<strong>RazFaz, you obviously don't know what I'm talking about, and that's fine - just get an education.</strong><hr></blockquote>
Look at the post I replied to: "Actually I was thinking it would use fast paged interleaved memory with RapidIO & HyperTransport".
Now, go to the site I linked to above, read it, understand it, realize that RIO and HT are basically two ways of doing pretty much the same thing, and that it would be futile to use them both concurrently in one system.
[quote]<strong>But when you say that you don't think that I know what I'm talking about I do take offense.</strong><hr></blockquote>
Feel free to prove me wrong.
Just enlighten me as to why, in your opinion, using both interconnection methods at once is technically feasible or even a good idea.
[quote]<strong>You missed my point. Outsider was making a different point , you were making an attack.</strong><hr></blockquote>
No, I did not. I did understand what you were trying to say, and then went on and (admittedly maybe not in the most polite way in the world) told you that your proposal, in my opinion, technically doesn't make a lot of sense for the reasons pointed out above. Feel free to show me how it does.
[quote]<strong>If you want to have a War of Wits with me about what I know or don't know be advised that you are bringing a knife to a gun fight. Bye Bye RatFiz</strong><hr></blockquote>
Bye,
RazzFazz
EDIT: added emphasis here and there
[ 02-16-2002: Message edited by: RazzFazz ]</p>
<strong>So, while Intel and AMD move to 533/1066 Rambus and PC2700/DDR2, Could Apple get similar performance from DDR266 ram and a giant whopper of a fast cache on each proc? Say 512KB of L1 on chip and 4-8MB of L2 on each daughtercard.
</strong><hr></blockquote>
This setup would be faster in some situations (where a significant part of the working set fits inside those large caches, but does not fit into the smaller ones), but at the same time be slower in others (streaming data, for example). It all depends on what you want to do.
[quote]<strong>
Would it be possible to engineer a memory controller to use regular 168pin Dimms in Pairs (like RAID in concept) to effectively double to performance of 266Mhz Ram, without going to newer RAM types.</strong><hr></blockquote>
That's what was referred to as bank interleaving earlier on.
Bye,
RazzFazz
Here's another question. What would be a practical limit for L2 caches on a desktop machine? I suppose a cache needs control circuitry on the chip (even if the cache is off chip) so that at some point it just gets too expensive/difficult to make the cache any bigger. Are we near that limit already, bearing in mind that whatever arrangement would have to fit in a line-up not more expensive than the current one. I remember reading about T1 SRAM a few weeks back: it's supposed to offer most of the benefit of true SRAM but remain much cheaper to produce. Would this make a good candidate for an big L2 cache? Supposedly the graphics chip in a Gamecube has a 14MB T1 SRAM cache that offers huge bandwidth to the graphics chip. Can it work for a CPU?
So, would most people be happy with a new Mobo featuring four interleaved 168 pin 266Mhz DDR dimms, and big (fast) L2 caches on each proc?
It sounds plenty fast to me, but then again I know not of what I speak.
[quote]<strong>Originally posted by Aphelion:
Actually I was thinking it would use fast paged interleaved memory with RapidIO & HyperTransport - and that would be an 8 legged horse with a head at both ends
<hr></blockquote></strong>
[sarcasm]
Interleaved memory = 8 legs (in a quad CPU system)
RIO & HT = 2 heads on the same horse
[/sarcasm]
I was making a point (to Outsider) that there are many ways to address the issue of bus speed and bandwidth. (60 in the link you provided). If you didn't then, nor don't now, understand that I wasn't seriously suggesting that my thoughts be applied literally and simultaneously to a Quad G4 motherboard, then I guess that I'll hop on my two headed horse and ride off into the sunset (or into the dawn, depending on bus arbitration).
I'll restate & rewrite my original point for clarity, and to bring the issues back to the topic of this thread:
G4 "tweaks and revs ... when and how?
Apple could release a quad G4 with enhanced IO (take your pick) and they could do it tomorrow, or could have done it last year. In the Architosh survey 55% of high end pro users want quad G4's and want it now, and consider $5K as a reasonable price to pay for such a beast.
You were rude dude, you don't get it, and yet you keep beating a dead horse.
[ 02-17-2002: Message edited by: Aphelion ]</p>
<strong>OK RazzFazz, I'll give it one more try:
[sarcasm]
Interleaved memory = 8 legs (in a quad CPU system)
RIO & HT = 2 heads on the same horse
[/sarcasm]
</strong><hr></blockquote>
So if the whole "RIO & HT" thing did not mean "both at once", and I just don't share your sense of humour, I wonder why you didn't just point that fact out after I said the following:
"Well, my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant."
From how I understood your post (and mis-understood your humour), it technically didn't make a lot of sense to me, so I asked "Are you sure you know what you're talking about?".
But instead of pointing out my lack of humour, you first post technical details about RIO and HT. Though technically correct, they didn't address the point I was questioning, so I replied stating explicitly that "my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant."
In response, you again didn't point out that I was obviously just not getting your joke / humour / sarcasm, but instead resorted to using such incredibly funny remarks as "RatFiz" (who's being rude now, again?).
[quote]<strong>You were rude dude, you don't get it, and yet you keep beating a dead horse.
</strong><hr></blockquote>
So instead of just pointing out my mistake, being even more rude seems like a good choice to you?
Well, whatever.
In case I really was just unable to follow your sense of humour, I hereby apologize, and suggest we just get back on topic.
Bye,
RazzFazz
[ 02-17-2002: Message edited by: RazzFazz ]</p>
<strong>
So instead of just pointing out my mistake, being even more rude seems like a good choice to you?
Well, whatever.
In case I really was just unable to follow your sense of humour, I hereby apologize, and suggest we just get back on topic.
Bye,
RazzFazz
</strong><hr></blockquote>
Well, it wasn't humor exactly, and if I had been more careful in my phrasing (ie put an OR in place of the &) I would have been technically correct and we would have had harmony. And I too resorted to rudeness and for that I apologize as well. By the way, the link about RIO & HT you gave was great and I read it with interest, Thank You.
Knowing the efficiency of the apple's Engineer to deliver the best of a technology, i think that this mobo will rock.
The next G4 will be 0,15 SOI based (all we know about the future roadmap of Motorola is that point), a 20 % to 30 % increase in speed sounds logical. As the programmer has said, if there is DDR ram the L3 cache is less interesting. So there might be a derived version of the 7455 with DDR memory controler, 512 K L2 and no L3 . Speed of 1,133 ghz to 1,4 ghz (if you supposed that the 7455 is able to go at 1,1 ghz without too many problems).
But if this new mobo is release for MWNY , it means that we will have to wait for the G5 an another year. Apple don't make mobo for only 6 months of live.
<strong>(if you supposed that the 7455 is able to go at 1,1 ghz without too many problems).
</strong><hr></blockquote>
It is. There's a 1.1GHz part already listed on the motorola site.
<strong>
It is. There's a 1.1GHz part already listed on the motorola site.</strong><hr></blockquote>
Where?
Towards the page bottom under "Orderable Parts" (from xlr8yourmac forum post).
artcat
edit: OOPS. Just found out that all multipliers on a 7455 after 8 are whole; no half multipliers. 7.5 is the last half multiplier (1GHz)... the next one is 8x (1.066GHz) and then 9x (1.2GHz)... all the way up to the maximum multiplier, 16x (2.133GHz)
[ 02-19-2002: Message edited by: Outsider ]</p>
Difference between a P2 and P3 : just SSE instructions.
so an improved G4 will be perfect for me, whatever is name.
[ 02-20-2002: Message edited by: powerdoc ]</p>
<strong>One weird thing about that 1100MHz G4 part is what bus speed are they basing that figure on? 100MHz? Possibly but that's kinda odd seeing at the 1000 part is a 133mhz bus part. So the figures I com up with are 137.5, 146.6, 157.1, 169.2, 183.3, and 200MHz. 200MHz is a famililiar number because it's the same as the maximum bus speed of the 750FX.</strong><hr></blockquote>
perhaps this chips are selled for the moment for the high embedded market. Mot does not make a lot of publicity about this 1,1 ghz chip, they just talk about a 1 hgz chip.