TSMC will use updated 'N7 Pro' 7-nanometer process for 'A13' chip manufacturing

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AppleInsiderAppleInsider
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in iPhone
Apple's "A13" processor will use a 7-nanometer process for its production, but chip foundry TSMC is reportedly planning to use a different enhanced process to the current version it has come up with, named "N7 Pro."

TSMC's offices.
TSMC's offices.


TSMC's use of a 7-nanometer process for the next generation of Apple system-on-chips is not unexpected, with TSMC widely believed to not only continue to be the only supplier of A-series chips in 2019, but also keeping to the same process level. According to one report, TSMC will be making some changes to the process.

The Chinese Commercial Times claims TSMC will move to a 7-nanometer extreme ultraviolet lithography (EUV) process that has the potential for more accurate chip production and more intricate designs, named "N7+." HiSilicon's Kirin 985 chips will be the first to use N7+ in its production, but the Apple-designed "A13" will be the next to go into manufacturing at the firm.

For the A-series chip, TSMC will be bringing out an alternate form of its N7+ process which it calls "N7 Pro." It is unclear exactly what the difference is between N7 Pro and N7+, but it will reportedly be ready for volume production late in the second quarter, in time for A-series production for the fall iPhone refresh.

TSMC has come up with a 5-nanometer design infrastructure that could be used to design future A-series chips and other processors. Current speculation has the "A14" using a 5-nanometer production process for the 2020 iPhones.

Comments

  • Reply 1 of 14
    iOS_Guy80ios_guy80 Posts: 949member
    What happens after the 0-nanometer design infrastructure?
    GeorgeBMacfrantisek
     2Likes 0Dislikes 0Informatives
  • Reply 2 of 14
    radarthekatradarthekat Posts: 3,939moderator
    iOS_Guy80 said:
    What happens after the 0-nanometer design infrastructure?
    What happens at 3nm?  Things should get interesting in a couple years. 

    https://semiengineering.com/big-trouble-at-3nm/
    edited April 2019
     0Likes 0Dislikes 0Informatives
  • Reply 3 of 14
    tnet-primarytnet-primary Posts: 246member
    What does this get us?  Better battery life?
     0Likes 0Dislikes 0Informatives
  • Reply 4 of 14
    wood1208wood1208 Posts: 2,944member
    Like Intel's 14nm-> 14nm+ ->14nm++. Tweaking node and squeeze every bit of performance out of it. TSMC, next 5nm in 2020 or 2021 ? But, like Intel's upcoming Lakefield approach, attention will move to 3D packing to integrate more on SOC than just keep reducing node size. Physics have it's limits.
     0Likes 0Dislikes 0Informatives
  • Reply 5 of 14
    GeorgeBMacgeorgebmac Posts: 11,421member
    iOS_Guy80 said:
    What happens after the 0-nanometer design infrastructure?
    If the math holds,  as you approach zero:  infinity -- Or, in this case, infinite power.
    ... "One chip to rule them all"
     0Likes 0Dislikes 0Informatives
  • Reply 6 of 14
    Solisoli Posts: 10,038member
    What does this get us?  Better battery life?
    To put it as plainly, smaller processes have a lower capacitance which allows transistors to turn on-and-off more quickly while using less energy. There are other advantages, as well as drawbacks, but the pros far outweighs the cons for this application.
    chasm
     1Like 0Dislikes 0Informatives
  • Reply 7 of 14
    MacPromacpro Posts: 19,873member
    iOS_Guy80 said:
    What happens after the 0-nanometer design infrastructure?
    They'd be running anti-matter computers of course!  ;)
     0Likes 0Dislikes 0Informatives
  • Reply 8 of 14
    tshapitshapi Posts: 375member
    GeorgeBMac said:
    iOS_Guy80 said:
    What happens after the 0-nanometer design infrastructure?
    If the math holds,  as you approach zero:  infinity -- Or, in this case, infinite power.
    ... "One chip to rule them all"
    The real question is when will this plateau? How close to 1nm can we get?
     0Likes 0Dislikes 0Informatives
  • Reply 9 of 14
    tshapitshapi Posts: 375member
    What will probably happen is rather than continuening to shrink the die size allle will hit the plateau and start packing more into the SoC such as the modem and the gpu and so on. 
     0Likes 0Dislikes 0Informatives
  • Reply 10 of 14
    tipootipoo Posts: 1,163member
    EUV is a pretty big deal. Its stated gains are better than some whole fab generations. This is fine! 
    chasm
     1Like 0Dislikes 0Informatives
  • Reply 11 of 14
    ryanvannoteryanvannote Posts: 4member
    iOS_Guy80 said:
    What happens after the 0-nanometer design infrastructure?
    Don't worry about that. The computer that invents the design and implements the manufacturing processes will also let us know what to do and how to feel about the upgrade experience. There are some strange quarks about physics, and people won't really entirely understand exactly how it all works at that point. The machines will tell us how they operate and we will have to believe them. So there won't be any drastic changes for the end user looking to upgrade their equipment.
     0Likes 0Dislikes 0Informatives
  • Reply 12 of 14
    Marvinmarvin Posts: 15,558moderator
    tshapi said:
    iOS_Guy80 said:
    What happens after the 0-nanometer design infrastructure?
    If the math holds,  as you approach zero:  infinity -- Or, in this case, infinite power.
    ... "One chip to rule them all"
    The real question is when will this plateau? How close to 1nm can we get?
    According to a VP at Samsung Semiconductor, 1.2nm is the limit for silicon:

    http://www.maltiel-consulting.com/Samsung-5nm_No_Limit_to_Silicon_Scaling_maltiel_semiconductor.html

    "Samsung is optimistic that EUV double patterning (NA=0.25, 0.32, then 0.6) will take patterning to several nanometers in 2014. His presentation of the fundamental laws of physics (based on Boltzmann distribution and Heisenberg's uncertainty principle) predicts a limit of scaling around 1.2 nm."

    Just now they are at 7nm, then 5nm (2020-2021), then 3nm (2022-2023).

    There was an experimental transistor made from a single atom (0.1nm):

    https://www.sciencedaily.com/releases/2012/02/120219191244.htm

    That's the theoretical limit and needed special cooling. Just now performance-per-watt is around 60GFLOP/Watt on 10nm. This allows for 10TFLOPs in average desktops. There's not much practical or commercial need to go beyond 20-30TFLOPs in a personal computer so companies will start to rely more on cloud services over hardware.

    For the next 5-6 years they should be able to keep pushing hardware advances as they are now. Then it will level out at typical upgrade cycles and computing hardware will become like other appliances. Computing hardware won't change much at all in design, functionality or performance like refrigerators and televisions but people will keep buying it, just at a slower rate.
    avon b7
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  • Reply 13 of 14
    chasmchasm Posts: 3,733member
    To answer the question of “how low can we go,” the practical answer is “not very much further,” I believe. There’s always new materials that may help sustain us down to perhaps 3nm, but before we hit that wall I believe the industry will move “sideways” into some level of quantum computing.
     0Likes 0Dislikes 0Informatives
  • Reply 14 of 14
    wizard69wizard69 Posts: 13,377member
    wood1208 said:
    Like Intel's 14nm-> 14nm+ ->14nm++. Tweaking node and squeeze every bit of performance out of it. TSMC, next 5nm in 2020 or 2021 ? But, like Intel's upcoming Lakefield approach, attention will move to 3D packing to integrate more on SOC than just keep reducing node size. Physics have it's limits.
    It is really a new node with the use of extreme UV imaging.  

     0Likes 0Dislikes 0Informatives
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