"I was able to get the board running at 133Mhz FSB easily, which increases the DDR throughput to 2.7GB/s"
<hr></blockquote>
Either this guy's a moron or he made a typo. DDR at 133MHz is 2.1GB/s, not 2.7.
[quote] Anyway, the point of my rant is to figure out what JYD is constantly whining and carrying on about when he whinges about apple not implementing a "true DDR frontside bus" or whatever he was *****ing about. Apple is doing the exact same thing as x86 mobo manufacturers. <hr></blockquote>
No, Apple is not doing the exact same thing as x86 mobo manufacturers, at least not as far as the Athlon and P4 goes. The Athlon's FSB is DDR, and the P4's is QDR. The G4 is only SDR. The Xserve has a DDR pipe from memory to the chipset, and an SDR pipe to the CPU. x86 motherboards (that use DDR SDRAM) have a DDR pipe to the chipset, and either a DDR (Athlon) or QDR (P4) pipe to the CPU. BIG difference.
I think that real DDR G4 are on the way. The Xserve is ready for the new chip, i doubt that apple has developped a new chipset running DDR memory just for the I/O of a server.
The problem is that it will be a new front side bus : the DDR max bus. A DDR 60x bus will be worthless. As the Programmer and other have said before, the Maxbus is very near the DDR athlon front bus, so it's not so easy to develop a DDR front bus who use nearly 100 % of the theoric bandwitch .
If we have waited a so long time for DDR G4 it was because the max bus tech was so efficient. But i am confident in the future the new chipset already exist : we have just to wait the new chip.
I'm not a retard. I know that Athlons don't use 266MHz FSBs. I know that an Athlon's bus runs at 133MHz, but data is sent on the rise and fall of the clock beat, giving it effective 266MHz.
If you're so ****ing smart, then why the **** do I need to say "xxxMHz effective" every time I'm discussing DDR and QDR? You should be smart enough to work out thats what I meant. You evidently are smart enought to work out what I meant.
I thought that RAMBUS was quad pumped, thanks for correcting me.
But my bandwidth figures and points are still correct.
</strong><hr></blockquote>
Yeah, didn't mean to imply otherwise. Guess I should rather have written "Modern motherboards usually use two such channels at once, doubling the throughput to reach the numbers you stated."
Everyone keeps batting around memory clock and FSB like they are indentical. Now, didn't Athlons debut with a 200 Mhz FSB and PC100 (later PC133) memory? FSB and memory clock can be asynchronous. The two don't always run at the same speed. That is how I understand the XServe architecture operating (only in reverse with the FSB clock slower than the memory clock)with the FSB from the G4 to the memory controller running at 133 Mhz and the memory bus (memory contoller to memory and DMA parts) running at 266 (2x133 Mhz).
<strong>I think that real DDR G4 are on the way. The Xserve is ready for the new chip, i doubt that apple has developped a new chipset running DDR memory just for the I/O of a server.
The problem is that it will be a new front side bus : the DDR max bus. A DDR 60x bus will be worthless. As the Programmer and other have said before, the Maxbus is very near the DDR athlon front bus, so it's not so easy to develop a DDR front bus who use nearly 100 % of the theoric bandwitch .
If we have waited a so long time for DDR G4 it was because the max bus tech was so efficient. But i am confident in the future the new chipset already exist : we have just to wait the new chip.</strong><hr></blockquote>
Wonder if the northbridge in xserve has something to do with Thundra Tsi890TM :
The Tsi890TM is a high-performance host bridge for PowerPC connectivity. It features PCI/PCI-X and RapidIO ports, a DDR memory controller, and dual gigabit Ethernet ports. The device also has a 60x/MPX PowerPC bus connection with support for PowerPC?s currently in development.
Tundra is currently engaged with alpha customers and will announce full design support in January 2002. In addition, further RapidIO product announcements will follow in January 2002.
Wonder if the northbridge in xserve has something to do with Thundra Tsi890TM :
The Tsi890TM is a high-performance host bridge for PowerPC connectivity. It features PCI/PCI-X and RapidIO ports, a DDR memory controller, and dual gigabit Ethernet ports. The device also has a 60x/MPX PowerPC bus connection with support for PowerPC’s currently in development.
Tundra is currently engaged with alpha customers and will announce full design support in January 2002. In addition, further RapidIO product announcements will follow in January 2002.
<strong>The device also has a 60x/MPX PowerPC bus connection with support for PowerPC?s currently in development. </strong><hr></blockquote>
Since Apple develops their own chipsets, this device doesn't have anything to do with the Mac. This particular statement, however, is particularly interesting because it clearly implies that there are 60x/MPX PowerPCs currently in development that make changes to the 60x/MPX bus protocols. Unfortunately we can't really draw conclusions from that because back in Nov'01 when this was published the 750fx had not yet been introduced by IBM and thus there was no modified 200MHz 60x bus yet. Hopefully they were also refering to a DDR MPX bus, but that remains guesswork.
The G4's 133 MHz MPX bus is significantly faster than the G3's 133 MHz 60x bus, but I don't know enough about the two designs to say whether it is faster than the 200 MHz 60x bus. It would probably depend on the chipset implementations. My guess is that the G4 would do pretty well, especially when running AltiVec software (which includes some very aggressive cache streaming features that the G3 doesn't have). Simply scaling the numbers I've seen for scalar G4 memory bandwidth vs. vector G4 memory bandwidth from 133 MHz -> 200 MHz, I think you'd see roughly equal performance between a G4 on a 133 MHz MPX and a G3 on a 200 MHz 60x bus. The G4 could, of course, do a lot more calculations on that data.
Apple buys its RAM in large quantities. Very Large. It would make a good deal of economic sense for them to use all DDR Ram on their entire pro line...despite levels of support and implementation. If it works... use it.
My quick observations on the whole thread:
Just because X server is uses 1ghz G4's is in no way a reason there can not be faster Desktops.
In fact, it almost forces the issue.
There is not a 1U server that uses the fastest class CPU in the box from almost any maker. There would be no perceived loss in the industry if there was, say, a 1.2Ghz Desktop. Further, it wouldn't matter if it where G4, G4.5, G5 or G-Whiz.
We will see DDR, it will be on a new controller,
there will be a revised G4 (4.5 as it was called?)
That's my point. The 266 mhz thoroughput is only between CPU and memory. Everything else on the FSB (admittedly, not much) runs at 133 mhz. So again, what is it that Apple is doing that JYD's whingeing about? Apple's 266 mhz ddr with a 133 fsb is THE SAME DEAL as what the x86 world is doing.
The "266 mhz FSB" is a scam, it only means that the memory can transfer as much as if it were a SDR 266 bus (because it's a DDR 133 bus... data is sent on the rising and falling edges of the clock cycle... there's still only ~133 million clock cycles per second... 2x133 = 266) so they call it a "266" or "DDR 266" bus.
So what is it that Apple's doing different to the PC world?</strong><hr></blockquote>
You just don't get it do you? What amazes me about people like you is that obviously, you have no idea how this whole architecture works, but that doesn't stop you from arguing endlessly.
What you don't seem to get, genius, is this:
The G4 CPU does NOT support a DDR frontside bus.
The Athlon DOES.
What this means is this. When the 2.1 GB/s of data comes from the DDR memory banks to the memory controller, it can go TO THE ATHLON PROCESSOR at the same bandwidth, without being choked.
However, on the XServe when the 2.1 GB/s of data comes to the memory controller, it has to stop there and wait. Because the G4 does not support double pumped transfers itself. So it can only transfer one 8 byte chunk per cycle at 133 Mhz, as opposed to the Athlon which can transfer 16 bytes per cycle at 133 Mhz.
You just don't get that DDR support on the motherboard (a la XServe and all other DDR motherboads) and DDR support on the CPU bus are independent of each other.
In fact it doesn't have to be DDR, what matters is bandwidth. The G4 could have a 266 Mhz SDR front side bus for all I care, and that would be fine for using it with 133x2 DDR. BECAUSE IN THAT CASE THE CPU CAN HANDLE THE BANDWIDTH FROM THE MEMORY
Wonder if the northbridge in xserve has something to do with Thundra Tsi890TM :
The Tsi890TM is a high-performance host bridge for PowerPC connectivity. It features PCI/PCI-X and RapidIO ports, a DDR memory controller, and dual gigabit Ethernet ports. The device also has a 60x/MPX PowerPC bus connection with support for PowerPC?s currently in development.
Tundra is currently engaged with alpha customers and will announce full design support in January 2002. In addition, further RapidIO product announcements will follow in January 2002.
Like the Programmer have said (Sorry the Programmer to quote you so often ) This tundra stuff is for the embedded market : it is write also in the title of the web page.
When i read these pages, i become more and more confident in the future of PPC chip. Yes the market of the PPC chip is the embedded market. But the embedded chip market is becoming more and more important and will exceed the desktop market soon. The problem of an embedded chip is that it does not have exactly the same specifications than a desktop chip.
That's why i a m sure and i am ready to bet a bottle of Champagne that we will see a G5 in the future. The G5 will have a new core the e 500 wich his a flexible architecture allowing the conception of customize chip . The first G5 chip is an embedded one : the 8450 , a chip that we will never see in a mac because he lack many things including an fpu unit and with other features like buil in gigaethernet that may be are worthless (i mean a waste of transistors on the chip) for Apple. In a few months when the developpement of the G4 will be finish we will see the G5 .
I think that the 7470 will be the last developpement of the G4 (i doubt that he will include new fpu unit : just a DDR memory controller and some improvements to support the extra amount of bandwitch, perhaps a larger L2 cache if the process is able to go down to SOI 0,13, in the contrary like SOI 0,15 perhaps a larger L3 cache up to 4 MB)
The core already exist like the I/O stuff. They have just to add some new features like new fpu units and others customized options for Apple. The principle goal of the G5 is too lower the cost of R&D of the chip. The G5 will not be a high end specialized chip like the P4 or the Clawhammer, but a flexible technologie able to fit the embedded market and the desktop market.
The G5 : one core, and many options to answers all the wishs, from the embedded market to the desktop one. I dont think that the G5 will be the fastest chip of the universe, but i think that the G5 will bring a future in the PPC desktop chips.
<strong>Why can't the next PM be quaruple-pumped like the current P4?</strong><hr></blockquote>
I doubt anyone reading this forum could answer the technical aspect of this question. There might be some reason MPX can't go QDR, but I suspect it could if Motorola decided to do that. Since their avowed direction is an on-chip memory controller, however, we probably won't see them push the MPX bus that far.
Here's what BadAndy had to say on Ars yesterday about the rumored DDR MPX bus:
[quote]
The bummer is that all the vibes coming out of moto and other competent sources are that the MPXbus will NOT get anything like the overhaul needed to go to DDR rates. The line from Raj Handa (PPC marketing at Moto) is that MPXbus will remain an SDR bus with a possible boost to 166 MHz SDR.
[...]
It is a complex hardware explanation to go through the issues; but basically most of the communication market (which is Moto's absolutely core market for PPC) resolutely loves MPXbus the way it is and has a huge commitment of devices built for it. They really like being able to "glue" their comm-widget du jour right to the CPU's FSB.
Handa's direct comment on the issue is "MPXbus is not a point-to-point bus." What he means by this is that the FSBs capable of DDR traffic rates are very tightly designed and limited, and they JUST connect one or two CPUs (with very short traces, and very careful layout, and the devices themselves do active line terminations ... and in fact sometimes some even trickier things) to the memory controller.... and nothing else. Moto could build these, but what Handa Is saying is that the rest of the PPC marketplace doesn't want it.
It is possible that there might be some hybrid modes, or it is possible that Moto will build G4+ chips with an alternative FSB than MPX ... but my guess is that Motorola is doing what the embedded/hardware oriented system houses ALWAYS do: supporting the long-term continuing customers. They don't want MPXbus to die and Moto won't kill it.
What I think we will see is that serious bandwidth won't come along until "G5" -- and that "G5" isn't here yet.
<hr></blockquote>
So there you have it-- the closest thing we've come to an official statement from Moto is that the MPX bus will remain SDR, with a possible boost to 166MHz.
is a 200MHz FSB == to a 100MHz FSB double-pumped (200Mhz effective)?
IE is it better to have DDR then SDR if they are both running at the same (effective) speeds?
P.S. off topic: Admins: I cant see the thread in the little window on the bottom of the rebly screen... I'm going to go post this in suggestions now.... thnx
<strong>Just to throw a little water on this thread...
Here's what BadAndy had to say on Ars yesterday about the rumored DDR MPX bus:
So there you have it-- the closest thing we've come to an official statement from Moto is that the MPX bus will remain SDR, with a possible boost to 166MHz.</strong><hr></blockquote>
Well, since DDR only adds 10% to 15% speed increases then 166 Mhz MPX bus would probably be faster any way (25% increase in bus speed). That'd be OK w/me.
<strong>Well, since DDR only adds 10% to 15% speed increases then 166 Mhz MPX bus would probably be faster any way (25% increase in bus speed). That'd be OK w/me.</strong><hr></blockquote>
People keep quoting this, but it is bullsh!t !!! The 10-15% quote refers to overall system performance resulting from a doubling of memory bandwidth. Since the measured tasks were not memory bound, their performance did not scale with the increase in memory bandwidth.
Memory bandwidth on a 166 MHz MPX bus will be about 1.25 GB/sec, a far cry from the 2.1 GB/sec of a 133 MHz DDR bus.
For what its worth, I read the comment from Motorola elsewhere as well -- and I believe it. It just makes too much sense. There are three ways out of this situation (assuming Moto is building the chip):
1) A specialized development just for Apple.
2) A PPC using MPX and an on-chip memory controller.
3) A PPC using RapidIO and an on-chip memory controller.
#1 is unlikely. #2 could happen in a shorter time frame than #3, but would just be a stop-gap and I don't expect to see it. #3 has been rumoured for some time now, but most of the rumours place it in Jan'03. This doesn't have to be a G5 as the existing core of the G4 could be used with it.
No cause for optimism, but nonetheless I remain hopeful that what ships in July will improve the current situation significantly.
Comments
"I was able to get the board running at 133Mhz FSB easily, which increases the DDR throughput to 2.7GB/s"
<hr></blockquote>
Either this guy's a moron or he made a typo. DDR at 133MHz is 2.1GB/s, not 2.7.
[quote] Anyway, the point of my rant is to figure out what JYD is constantly whining and carrying on about when he whinges about apple not implementing a "true DDR frontside bus" or whatever he was *****ing about. Apple is doing the exact same thing as x86 mobo manufacturers. <hr></blockquote>
No, Apple is not doing the exact same thing as x86 mobo manufacturers, at least not as far as the Athlon and P4 goes. The Athlon's FSB is DDR, and the P4's is QDR. The G4 is only SDR. The Xserve has a DDR pipe from memory to the chipset, and an SDR pipe to the CPU. x86 motherboards (that use DDR SDRAM) have a DDR pipe to the chipset, and either a DDR (Athlon) or QDR (P4) pipe to the CPU. BIG difference.
The problem is that it will be a new front side bus : the DDR max bus. A DDR 60x bus will be worthless. As the Programmer and other have said before, the Maxbus is very near the DDR athlon front bus, so it's not so easy to develop a DDR front bus who use nearly 100 % of the theoric bandwitch .
If we have waited a so long time for DDR G4 it was because the max bus tech was so efficient. But i am confident in the future the new chipset already exist : we have just to wait the new chip.
I'm not a retard. I know that Athlons don't use 266MHz FSBs. I know that an Athlon's bus runs at 133MHz, but data is sent on the rise and fall of the clock beat, giving it effective 266MHz.
If you're so ****ing smart, then why the **** do I need to say "xxxMHz effective" every time I'm discussing DDR and QDR? You should be smart enough to work out thats what I meant. You evidently are smart enought to work out what I meant.
Barto
<strong>
As I said, Dual Channel.
I thought that RAMBUS was quad pumped, thanks for correcting me.
But my bandwidth figures and points are still correct.
</strong><hr></blockquote>
Yeah, didn't mean to imply otherwise. Guess I should rather have written "Modern motherboards usually use two such channels at once, doubling the throughput to reach the numbers you stated."
Bye,
RazzFazz
1. G4's at 1.5 GHZ
2. FSB of 333 MHZ
3. 800 Mbs Firewire
4. New Case
Am I asking for 2 much here?
<strong>All I want to see:
1. G4's at 1.5 GHZ
2. FSB of 333 MHZ
3. 800 Mbs Firewire
4. New Case
Am I asking for 2 much here?
Yeah, you will only get 800 FW and a new case <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
<strong>I think that real DDR G4 are on the way. The Xserve is ready for the new chip, i doubt that apple has developped a new chipset running DDR memory just for the I/O of a server.
The problem is that it will be a new front side bus : the DDR max bus. A DDR 60x bus will be worthless. As the Programmer and other have said before, the Maxbus is very near the DDR athlon front bus, so it's not so easy to develop a DDR front bus who use nearly 100 % of the theoric bandwitch .
If we have waited a so long time for DDR G4 it was because the max bus tech was so efficient. But i am confident in the future the new chipset already exist : we have just to wait the new chip.</strong><hr></blockquote>
Wonder if the northbridge in xserve has something to do with Thundra Tsi890TM :
The Tsi890TM is a high-performance host bridge for PowerPC connectivity. It features PCI/PCI-X and RapidIO ports, a DDR memory controller, and dual gigabit Ethernet ports. The device also has a 60x/MPX PowerPC bus connection with support for PowerPC?s currently in development.
Tundra is currently engaged with alpha customers and will announce full design support in January 2002. In addition, further RapidIO product announcements will follow in January 2002.
you can finde the whole at:
<a href="http://www.tundra.com/page.cfm?TREE_ID=101036"; target="_blank">http://www.tundra.com/page.cfm?TREE_ID=101036</a>;
regards
Rooster
<strong>
Wonder if the northbridge in xserve has something to do with Thundra Tsi890TM :
The Tsi890TM is a high-performance host bridge for PowerPC connectivity. It features PCI/PCI-X and RapidIO ports, a DDR memory controller, and dual gigabit Ethernet ports. The device also has a 60x/MPX PowerPC bus connection with support for PowerPC’s currently in development.
Tundra is currently engaged with alpha customers and will announce full design support in January 2002. In addition, further RapidIO product announcements will follow in January 2002.
you can finde the whole at:
<a href="http://www.tundra.com/page.cfm?TREE_ID=101036"; target="_blank">http://www.tundra.com/page.cfm?TREE_ID=101036</a>;
</strong><hr></blockquote>
Looks interesting, but I thought Apple said at the XServe launch that the memory controller was a proprietary part they developed in house.
<strong>The device also has a 60x/MPX PowerPC bus connection with support for PowerPC?s currently in development. </strong><hr></blockquote>
Since Apple develops their own chipsets, this device doesn't have anything to do with the Mac. This particular statement, however, is particularly interesting because it clearly implies that there are 60x/MPX PowerPCs currently in development that make changes to the 60x/MPX bus protocols. Unfortunately we can't really draw conclusions from that because back in Nov'01 when this was published the 750fx had not yet been introduced by IBM and thus there was no modified 200MHz 60x bus yet. Hopefully they were also refering to a DDR MPX bus, but that remains guesswork.
The G4's 133 MHz MPX bus is significantly faster than the G3's 133 MHz 60x bus, but I don't know enough about the two designs to say whether it is faster than the 200 MHz 60x bus. It would probably depend on the chipset implementations. My guess is that the G4 would do pretty well, especially when running AltiVec software (which includes some very aggressive cache streaming features that the G3 doesn't have). Simply scaling the numbers I've seen for scalar G4 memory bandwidth vs. vector G4 memory bandwidth from 133 MHz -> 200 MHz, I think you'd see roughly equal performance between a G4 on a 133 MHz MPX and a G3 on a 200 MHz 60x bus. The G4 could, of course, do a lot more calculations on that data.
Apple buys its RAM in large quantities. Very Large. It would make a good deal of economic sense for them to use all DDR Ram on their entire pro line...despite levels of support and implementation. If it works... use it.
My quick observations on the whole thread:
Just because X server is uses 1ghz G4's is in no way a reason there can not be faster Desktops.
In fact, it almost forces the issue.
There is not a 1U server that uses the fastest class CPU in the box from almost any maker. There would be no perceived loss in the industry if there was, say, a 1.2Ghz Desktop. Further, it wouldn't matter if it where G4, G4.5, G5 or G-Whiz.
We will see DDR, it will be on a new controller,
there will be a revised G4 (4.5 as it was called?)
There will not be FW 2 or USB 2
There will be a new case.
I have no idea.
<strong>
That's my point. The 266 mhz thoroughput is only between CPU and memory. Everything else on the FSB (admittedly, not much) runs at 133 mhz. So again, what is it that Apple is doing that JYD's whingeing about? Apple's 266 mhz ddr with a 133 fsb is THE SAME DEAL as what the x86 world is doing.
The "266 mhz FSB" is a scam, it only means that the memory can transfer as much as if it were a SDR 266 bus (because it's a DDR 133 bus... data is sent on the rising and falling edges of the clock cycle... there's still only ~133 million clock cycles per second... 2x133 = 266) so they call it a "266" or "DDR 266" bus.
So what is it that Apple's doing different to the PC world?</strong><hr></blockquote>
You just don't get it do you? What amazes me about people like you is that obviously, you have no idea how this whole architecture works, but that doesn't stop you from arguing endlessly.
What you don't seem to get, genius, is this:
The G4 CPU does NOT support a DDR frontside bus.
The Athlon DOES.
What this means is this. When the 2.1 GB/s of data comes from the DDR memory banks to the memory controller, it can go TO THE ATHLON PROCESSOR at the same bandwidth, without being choked.
However, on the XServe when the 2.1 GB/s of data comes to the memory controller, it has to stop there and wait. Because the G4 does not support double pumped transfers itself. So it can only transfer one 8 byte chunk per cycle at 133 Mhz, as opposed to the Athlon which can transfer 16 bytes per cycle at 133 Mhz.
You just don't get that DDR support on the motherboard (a la XServe and all other DDR motherboads) and DDR support on the CPU bus are independent of each other.
In fact it doesn't have to be DDR, what matters is bandwidth. The G4 could have a 266 Mhz SDR front side bus for all I care, and that would be fine for using it with 133x2 DDR. BECAUSE IN THAT CASE THE CPU CAN HANDLE THE BANDWIDTH FROM THE MEMORY
Get it? Probably not... It's hopeless
<strong>
Wonder if the northbridge in xserve has something to do with Thundra Tsi890TM :
The Tsi890TM is a high-performance host bridge for PowerPC connectivity. It features PCI/PCI-X and RapidIO ports, a DDR memory controller, and dual gigabit Ethernet ports. The device also has a 60x/MPX PowerPC bus connection with support for PowerPC?s currently in development.
Tundra is currently engaged with alpha customers and will announce full design support in January 2002. In addition, further RapidIO product announcements will follow in January 2002.
you can finde the whole at:
<a href="http://www.tundra.com/page.cfm?TREE_ID=101036"; target="_blank">http://www.tundra.com/page.cfm?TREE_ID=101036</a>;
regards
Rooster</strong><hr></blockquote>
Like the Programmer have said (Sorry the Programmer to quote you so often
When i read these pages, i become more and more confident in the future of PPC chip. Yes the market of the PPC chip is the embedded market. But the embedded chip market is becoming more and more important and will exceed the desktop market soon. The problem of an embedded chip is that it does not have exactly the same specifications than a desktop chip.
That's why i a m sure and i am ready to bet a bottle of Champagne that we will see a G5 in the future. The G5 will have a new core the e 500 wich his a flexible architecture allowing the conception of customize chip . The first G5 chip is an embedded one : the 8450 , a chip that we will never see in a mac because he lack many things including an fpu unit and with other features like buil in gigaethernet that may be are worthless (i mean a waste of transistors on the chip) for Apple. In a few months when the developpement of the G4 will be finish we will see the G5 .
I think that the 7470 will be the last developpement of the G4 (i doubt that he will include new fpu unit : just a DDR memory controller and some improvements to support the extra amount of bandwitch, perhaps a larger L2 cache if the process is able to go down to SOI 0,13, in the contrary like SOI 0,15 perhaps a larger L3 cache up to 4 MB)
The core already exist like the I/O stuff. They have just to add some new features like new fpu units and others customized options for Apple. The principle goal of the G5 is too lower the cost of R&D of the chip. The G5 will not be a high end specialized chip like the P4 or the Clawhammer, but a flexible technologie able to fit the embedded market and the desktop market.
The G5 : one core, and many options to answers all the wishs, from the embedded market to the desktop one. I dont think that the G5 will be the fastest chip of the universe, but i think that the G5 will bring a future in the PPC desktop chips.
<strong>Why can't the next PM be quaruple-pumped like the current P4?</strong><hr></blockquote>
I doubt anyone reading this forum could answer the technical aspect of this question. There might be some reason MPX can't go QDR, but I suspect it could if Motorola decided to do that. Since their avowed direction is an on-chip memory controller, however, we probably won't see them push the MPX bus that far.
Here's what BadAndy had to say on Ars yesterday about the rumored DDR MPX bus:
[quote]
The bummer is that all the vibes coming out of moto and other competent sources are that the MPXbus will NOT get anything like the overhaul needed to go to DDR rates. The line from Raj Handa (PPC marketing at Moto) is that MPXbus will remain an SDR bus with a possible boost to 166 MHz SDR.
[...]
It is a complex hardware explanation to go through the issues; but basically most of the communication market (which is Moto's absolutely core market for PPC) resolutely loves MPXbus the way it is and has a huge commitment of devices built for it. They really like being able to "glue" their comm-widget du jour right to the CPU's FSB.
Handa's direct comment on the issue is "MPXbus is not a point-to-point bus." What he means by this is that the FSBs capable of DDR traffic rates are very tightly designed and limited, and they JUST connect one or two CPUs (with very short traces, and very careful layout, and the devices themselves do active line terminations ... and in fact sometimes some even trickier things) to the memory controller.... and nothing else. Moto could build these, but what Handa Is saying is that the rest of the PPC marketplace doesn't want it.
It is possible that there might be some hybrid modes, or it is possible that Moto will build G4+ chips with an alternative FSB than MPX ... but my guess is that Motorola is doing what the embedded/hardware oriented system houses ALWAYS do: supporting the long-term continuing customers. They don't want MPXbus to die and Moto won't kill it.
What I think we will see is that serious bandwidth won't come along until "G5" -- and that "G5" isn't here yet.
<hr></blockquote>
So there you have it-- the closest thing we've come to an official statement from Moto is that the MPX bus will remain SDR, with a possible boost to 166MHz.
is a 200MHz FSB == to a 100MHz FSB double-pumped (200Mhz effective)?
IE is it better to have DDR then SDR if they are both running at the same (effective) speeds?
P.S. off topic: Admins: I cant see the thread in the little window on the bottom of the rebly screen... I'm going to go post this in suggestions now.... thnx
<strong>Just to throw a little water on this thread...
Here's what BadAndy had to say on Ars yesterday about the rumored DDR MPX bus:
So there you have it-- the closest thing we've come to an official statement from Moto is that the MPX bus will remain SDR, with a possible boost to 166MHz.</strong><hr></blockquote>
Well, since DDR only adds 10% to 15% speed increases then 166 Mhz MPX bus would probably be faster any way (25% increase in bus speed). That'd be OK w/me.
<strong>Well, since DDR only adds 10% to 15% speed increases then 166 Mhz MPX bus would probably be faster any way (25% increase in bus speed). That'd be OK w/me.</strong><hr></blockquote>
People keep quoting this, but it is bullsh!t !!! The 10-15% quote refers to overall system performance resulting from a doubling of memory bandwidth. Since the measured tasks were not memory bound, their performance did not scale with the increase in memory bandwidth.
Memory bandwidth on a 166 MHz MPX bus will be about 1.25 GB/sec, a far cry from the 2.1 GB/sec of a 133 MHz DDR bus.
For what its worth, I read the comment from Motorola elsewhere as well -- and I believe it. It just makes too much sense. There are three ways out of this situation (assuming Moto is building the chip):
1) A specialized development just for Apple.
2) A PPC using MPX and an on-chip memory controller.
3) A PPC using RapidIO and an on-chip memory controller.
#1 is unlikely. #2 could happen in a shorter time frame than #3, but would just be a stop-gap and I don't expect to see it. #3 has been rumoured for some time now, but most of the rumours place it in Jan'03. This doesn't have to be a G5 as the existing core of the G4 could be used with it.
No cause for optimism, but nonetheless I remain hopeful that what ships in July will improve the current situation significantly.