G5: The Flood Gates Are Open

Posted:
in Future Apple Hardware edited January 2014
Will we see it in '02? '04? '44? Will it still be PowerPC? Will it be 64-bit? Will "AltiVec" be 256-bit?



And what about that rumor that never spread? Could it have built-in DDR controllers and a direct bus to RAM, making the RAM accessible at a 1:1 ratio?



Talk amongst yourselves...

Comments

  • Reply 1 of 8
    stoostoo Posts: 1,490member
    If it's called "G5", then it has to be a fifth generation PowerPC (whatever "fifth generation means ). Any non-PowerPC processor would have a different nomenclature.
  • Reply 2 of 8
    telomartelomar Posts: 1,804member
    [quote]Originally posted by null:

    <strong>Will it be 64-bit?</strong><hr></blockquote>



    Servers tend to be more inclined to utilise 64-bit processors than desktops due to some of the tasks they are used for... Can't really say much more on that one but even Motorola's ancient roadmaps made mention of a 32-bit and 64-bit part. Even if things have changed since it was initially made.
  • Reply 3 of 8
    bartobarto Posts: 2,246member
    "G5" refers to "5th Generation PowerPC CPUs".



    Generation as in a certain band of technology included in all CPUs labeled G5.



    <a href="http://e-www.motorola.com/collateral/PPCRMAP.pdf"; target="_blank">http://e-www.motorola.com/collateral/PPCRMAP.pdf</a>;

    <a href="http://www-3.ibm.com/chips/products/powerpc/rdmap/roadmap_small.jpg"; target="_blank">http://www-3.ibm.com/chips/products/powerpc/rdmap/roadmap_small.jpg</a>;





    According to IBM and Motorola, G5 CPUs will differ from G4 CPUs in that they use RapidIO and BookE.



    RapidIO is a new system bus, replacing internal PCI and the G4's MPX bus with a high-speed switching architechture.



    BookE is a CPU core co-developed by Motorola and IBM. It is very modular, meaning a whole range of chips can be built. Motorola's 8540 (a G5 CPU) is BookE yet has no AltiVec or FPU units, and integrates gigabit ethernet, PCI-X and DDR-333 all on the CPU! You don't have to redesign to core every time you want to design a new CPU. Just swap bits in and out.



    In otherwords, the back-end and front-end of the G4 are gone. Which means, you guessed it, whether or not they will be used in Apple computers, G5s are completely different from G4s.



    Barto



    [ 05-25-2002: Message edited by: Barto ]</p>
  • Reply 4 of 8
    bartobarto Posts: 2,246member
    Some more...



    There is no mention of an AltiVec II/256/whatever on the roadmap. From what I gather (from Programmer and others), AltiVec rocks, and Motorola would be better off improving other areas of the CPU.



    G5s come in 32bit and 64bit flavors.



    An G5 in an Apple Computer would most likely be 64bit, have an FPU and Altivec and an onboard DDR-333 controller.



    But due to BookE we have no way of knowing what will be on an desktop G5. G5s can be a whole logicboard squished into an (probably oversized) chip, or they can be like a G4, just the basics.



    Barto
  • Reply 5 of 8
    programmerprogrammer Posts: 3,410member
    [quote]Originally posted by null:

    <strong>Will we see it in '02? '04? '44? Will it still be PowerPC? Will it be 64-bit? Will "AltiVec" be 256-bit?



    And what about that rumor that never spread? Could it have built-in DDR controllers and a direct bus to RAM, making the RAM accessible at a 1:1 ratio?



    Talk amongst yourselves...</strong><hr></blockquote>



    Do we really need yet another thread about the G5? Ah well, go with the flow I guess...



    '03 (unless we're really lucky and the 7500 shows at MWNY).

    Of course it'll be a PowerPC.

    The first may not be 64-bit, but eventually it will be.

    I don't think we'll see an "AltiVec2" for a bunch of reasons.

    It will have multiple FPUs.

    It will have an on-chip memory controller -- I don't know what you mean about "the rumour that never spread", this has been discussed at length for &gt;8 months.

    An on-chip memory controller implies a direct connection to RAM.

    RAM will never be accessed at 1:1 speeds unless the processors get a lot slower or RAM gets a lot faster. I don't foresee this happening for quite a while, if ever. RAM will move onto the processor first (or the processor onto RAM, depending on how you look at it).

    RAM may be fast enough and the L2 cache large enough to eliminate the expensive L3 cache, however.

    Other system communication will be via RapidIO or some other point-to-point narrow high speed bus.

    We may eventually see hyper-threading or a multi-core design -- this approach makes better use of superscalar designs, and that has always been the avowed philosophy for the PowerPC.

    If built with the modular approach that Moto (see 8540) and IBM are taking to PowerPC design, then we may see other interesting system-on-chip devices (FireWire, Ethernet, HyperTransport, etc). At the very least the on-chip memory controller should have a DMA system for off-chip I/O to access the processor's RAM. A HyperTransport interface to the graphics system could replace AGP.

    Longer pipelines to acheive higher clock rates.
  • Reply 6 of 8
    powerdocpowerdoc Posts: 8,123member
    a 1 MB on die Cache 256 bits will rock : the L3 cache will be useless in this case. A 512 K L2 cache could be helped by a 4 MB L3 cache .
  • Reply 7 of 8
    macsrgood4umacsrgood4u Posts: 3,007member
    From MOSR:

    Meanwhile, according to Motorola's director of strategic marketing the Apollo processor will "soon" be taken down to a 0.13 micron process and everything in the Apollo family will utilize SOI. As reported previously, they comment that the G5 is " still a long way off".
  • Reply 8 of 8
    serranoserrano Posts: 1,806member
    the g5 is neither a g nor a 5...
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