Cheap small core like 440 is a step toward the cell base computing.
You know what, this sounds very plausable. As for everyone clammoring about, saying the the G5 needs to go into the Powerbook, let me draw you an example from a very unlikely source... Intel.
When the P4 first came out, it had a very similar problem that the current G5 has; it was bulky, hot, and no way capabible of being stuffed into a laptop, even with a shoehorn.
So what did Intel do? They enhanced their fabs (bringing it to 130 process, I think), used a similar instruction set, and called it the Pentium 4M. I remember how everyone chided them for this advance in computing technology, but it really was a good, smart move on their part.
Now, lets bring this back to IBM. Let's don our speculation caps, shall we. The main reason why we are saying that this wouldn't work is because it isn't of the 9xx series. It seems to be a step backward, doesn't make sense, costs too much, etc etc, yadda yadda yadda.
Now, lets say that the initial batch of 440s are a trial run, seeing if it is feasable, etc etc. Finding out how they can do it, and seeing how difficult it would be to mass produce this. Mass production reduces the cost of the chip. Also, lets say that Apple has had a hand in this (HyperTransport) with their memory controller, et al.
All of the sudden, they have a viable chip that can keep pace with the current G5s. Then this chip becomes the G5m (for lack of better wording).
If we were to believe that this chip-set is destined for the PowerBook line-up, then I think that this would be the approach that they would take.
As for the marketing of the chip, what they would do is market it like this... G5m @ 2 GHz (4 x 500Mhz) - 2.8 GHz (4 x 700 MHz). Remember, people have believed the marketing hype from Intel that MHz matters. So why not use it against them with a chip that we could use it with.
Ok then, perhaps you can explain who the "third parties" are that have already done some work that would help Apple create an implementation of this architecture for Mac OS X?
Perhaps you can explain how each core will run a mini-(Mac)OS? And then maybe you can explain exactly how you can split up a single-threaded application across multiple mini-OSes? How do you "cluster" Powerpoint?
I don't know who you are when you are at home, much less on the Battlefront, and I don't care. What I do care about is that you have made statements that you have inside knowledge about topics you don't seem to understand the implications thereof. That in itself is not unusual, but then you post a blurb that seems to contradict this impression, except that it uses english slang and non-asian syllabic cadences you have not previously exhibited. So I have to wonder, whose explanations (or flights of fancy) are you parroting?
Who knows? Maybe you do have sources and maybe it will happen just the way you say. But the greater probability is that you've just thrown something out there based on guesses and wishing and you were just hoping for a reaction from a bunch of folks here who were disappointed that the G5 ran too hot to go into a Powerbook.
first of all there has been work done with MPI for OS X
each core runs a extremely small version of mac os x that only has basic MPI function.
powerpoint would have to be rewritten. the user interface, as in current os x is graphic proccessor. you may split the work , for example, in different thread for user input, memory copy, etc. i dont kno how powerpoint work so i dont comment on.
The 400 series is available as a core. You take your design automation tools, tack on a few functional units, compile and send to the foundry. It no real mystery and those functional units can be derived from a library or a few of your own. I would not be surprised at this moment in time to hear that AltVec exist as source code some place.
I'm not saying it can't be done. I'm saying it doesn't make sense to do it. The 440 was expressly designed to be extensible. A good SoC solution needs to be extensible because in the embedded market, one size rarely fits all plus an extensible design will have longer legs as far as product family lifecycle goes. (You don't have to retool for every new fad in communications technology.)
So yes, you can add VMX and 440 FPU2 units to the 440 quite handily.
Quote:
Actually I thought we started out with 2 core processors but that doesn't really matter. The only thing that bothers me about the MCM is that they where expensive, but maybe that is not a problem at the volumns that Apple would use.
Well he said two MCMs with two 440s each. Which is nonsensical at the outset, since an MCM describes the Power4 and Power5 packaging and IBM does not use the terminology elsewhere, to my knowledge. But leaving that aside, there is the issue that what an MCM provides is interchip communications busses. It's purpose is to allow the cores to communicate, so separating them into pairs with only two per MCM is counterproductive if you know you'll need four cores. So I assumed that all four would be on one MCM.
Quote:
In any event I would suspect that the 440 was used for prototype work. There is a good chance that a follow on to the 400 series may actually make it into the design.
Well, if you want to create imaginary architectures to make Nr9's scenario more plausible, go right ahead.
Quote:
Well that may be his answer but what would happen if a MMU that supports SMP where tacked onto the core.
There would also have to be support in the core for thread locking, etc. (Means more silicon, more heat.)
Quote:
This is unix, there is support for communications between processes already. I don't think you would see a major retooling of the operating system. In any event I'm leaning to a more traditional SMP system on a chip.
This is actually a self contradictory two part objection. Please rest assured that (as Nr9 points out) a distributed architecture would require an entirely new programmatic model despite Mac OS X's unix foundations. It would mean rewritting the OS from the ground up. You would not be able to use the Mach kernel, for instance.
As to the second part of your objection, yes an SMP implementation is possible, just not with the 440 core.
Quote:
Frankly I can't ever recall Nr9 saying that a single thread would run acroos several processors. I'm reasonable sure that was someone else because I responded to that specific post.
Whether he said it or not, it becomes a fundamental requirement as the only alternative is to run it on a slow core effectively undoing any expected perfromance benefit.
Quote:
My position is that it would be easiest for Apple to go the SMP route on the new chip implementation due to the leveraging of existing software. It would certainly give you the best bang for the buck in the short term. But and it is a big but SMP does not scale forever and not all programs can really make use of it. At some point multiple independant processing units that communicate amongst themselves may be a better idea.
Well, in some applications, the advantages of distributed architectures are overwhelming. But that is not to say that this is true in all cases. Yes, it may be true that there are limits to SMP systems but can you tell me what those limits might be? IBM is heavily invested in the Power5 architecture which is carrying SMP down to the thread level (SMT).
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In effect a cluster of SMP units on one motherboard or MCM or SOC.
Sigh. You really can't just jumble up terms like MCM, SoC, SMP and "cluster". Each has a specific meaning in the context of this discussion so you can't posit the integration of seemingly anti-podal or contrasting technologies without a great deal more explanation as to how it would be achieved.
Quote:
This is not a spooky goverment project. It has the potential to solve a number of issue related to low power operation and high performance.
You miss my point. Right now, the only kinds of applications (software) that use the kind of cellular programming model described are high end, highly parallel, high performance applications such as climatological modeling software run by government agencies and academic institutions.
Quote:
Why you believe that a bunch of portin will need to be done is beyond me. Sure some system level stuff will have to be done, but there is no reason at all that all traditional programming models could not be supported. What you would be doing is evolving the machine not building a new one.
You'd think so, wouldn't you? But then, you'd be wrong. It would be extremely difficult for any number of reasons, not the least of which is that "ain't no one been there yet".
Quote:
That is like saying if the 970 comes out with a larger cache its not the 970 anymore.
No, it's more like taking the APU of the PPC 970 and replacing it with a 440 core. Then repeat with the FPUs. And so on.
Quote:
Ok explain what multithread has to do with SMP. Further do you need SMP to support multithreading. <<<<Trick question>>>>.
You got me. I have no clue what you are talking about.
As described, the architecture of the laptop in question is as foreign to Mac OS X applications as the P4 is. (Actually, the P4 is a kissing cousin compared to the implementation described.) So, if Apple were to ship this next week, there would be no software for it.
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These are rumors and wild ass geusses you know
That, of course, is the thrust of my argument.
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Please give up on the seperate code base thought would you. It shows a complete lack of understanding on what is possible. Believe me many things are possible.
Nope, sorry. Not buying it.
Quote:
Even worst what is this talk about a new instruction set!!! we have been talking PPC since the begining of this thread.
No, at least some of us have been discussing the cell architecture under development by the STI group. Whether it is implemented starting from PPC or x86 designs won't matter that much. You could begin with transmeta's architecture, but in the end you will have a bunch of instructions that make no sense to any other architecture. The problem space is too divergent. Hence, a new instruction set.
Now, you might be able to convince me it could be done as an extension to an existing ISA, but you'd have to work pretty hard at it.
Well he said two MCMs with two 440s each. Which is nonsensical at the outset, since an MCM describes the Power4 and Power5 packaging and IBM does not use the terminology elsewhere, to my knowledge. But leaving that aside, there is the issue that what an MCM provides is interchip communications busses. It's purpose is to allow the cores to communicate, so separating them into pairs with only two per MCM is counterproductive if you know you'll need four cores. So I assumed that all four would be on one MCM.
on the first page, i corrected that it was one MCM with two chips with two cores each.
this afternoon I talked with some of my sources. There is an important thing they mentioned to me. The overall design is the same, it has 2 processors per chip with 2 chips for 4 processor 440 design.
however, it also has one additional integer only unit, which is used to boot up Mac OS X and provide I/O functions. The rest of the four processors each run a very small OS and are booted after the small controller 440 is booted.
software written with the new MPI libraries Apple will introduce during WWDC will be offloaded to the four 440 chips. There will be a runtime support to run a single thread as a single MPI thread.(i am not sure how this works, but there will be a performance hit)
the extra core is integer only so it only uses about 1 Watt. it is not likely to improve performance, so it is not include in apple's specs
this afternoon I talked with some of my sources. There is an important thing they mentioned to me. The overall design is the same, it has 2 processors per chip with 2 chips for 4 processor 440 design.
however, it also has one additional integer only unit, which is used to boot up Mac OS X and provide I/O functions. The rest of the four processors each run a very small OS and are booted after the small controller 440 is booted.
Hmmm. Convenient that you were able to get a hold of your sources to address the question of how applications are prioritized.
Well. Now that we have that straightened out...
Quote:
software written with the new MPI libraries Apple will introduce during WWDC will be offloaded to the four 440 chips. There will be a runtime support to run a single thread as a single MPI thread. (i am not sure how this works, but there will be a performance hit)
the extra core is integer only so it only uses about 1 Watt. it is not likely to improve performance, so it is not include in apple's specs
OK, then. If I understand you correctly, after the system starts up, four (4) OS images of some kind will load into memory and the controller chip will start scheduling jobs via some kind of Message Passing Interface (MPI) protocol implementation to the images, each of which controls one 440 core?
So to the controller image, it (the rest of the cores) looks like a network of four nodes and processes can be distributed to each node as needed, with the results returned to the controller chip? And there is a method to dedicate a node to any process or thread that can't be broken or parceled out as a distributed process? Am I right so far?
I never doubted 90nm G5. what i doubt is that 90nm G5 will be suitable for laptop purposes
Yes, I understand. But you see my position is that it will be easier and less costly to implement a 90nm G5 for the Powerbook than it will be to implement a true cell architecture.
And my case has been significantly strengthened by the info released about "Power Tune" which is obviously an industrial strength speed stepping implementation intended for mobile applications. (Preserves battery power, capische?)
And would that tend to weaken your case for the release of a VT "Big Mac mini-me" Powerbook supercomputer? Hmmm, lets think about that shall we?
Hmmm. Convenient that you were able to get a hold of your sources to address the question of how applications are prioritized.
Well. Now that we have that straightened out...
OK, then. If I understand you correctly, after the system starts up, four (4) OS images of some kind will load into memory and the controller chip will start scheduling jobs via some kind of Message Passing Interface (MPI) protocol implementation to the images, each of which controls one 440 core?
So to the controller image, it (the rest of the cores) looks like a network of four nodes and processes can be distributed to each node as needed, with the results returned to the controller chip? And there is a method to dedicate a node to any process or thread that can't be broken or parceled out as a distributed process? Am I right so far?
I am close to the source so I can ask relevant question. It appears that it will be that way.
Well then, I think I can officially say this is bunkum.
What you are describing is pointless. MPI has been around on the Mac for several years in several implementations. It is no magic bullet, and what you describe is just a standard clustering solution. (Except, of course, that you're talking about clustering only four underpowered PPC chips in a laptop.)
This would be a great laptop for running Linpack, it really wouldn't be much use otherwise. And no way is Apple rewriting it's entire OS to ship this laptop, nor would they be developing the prototype processor architecture for desktops in a laptop.
Sorry, but this has nothing to do with cell and is just too unrealistic to be given credence.
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Power Tune is a fake rumor. it does not exist.
Well, I guess that will be news to IBM who will be talking about it Monday, February 18th at Noon at the ISSCC. You can read about it in the ISSCC advance program. (page 59 of the PDF).
However, when Reuters today reported that Blue Gene was "based on microchip technology to be used in gaming consoles due out next year" it set off a torrent of speculation that the supercomputer's processors would be coming soon to living rooms. When contacted by GameSpot, an IBM representative quickly shot the rumor down. "The Blue Gene's chips are totally customized" said the rep. Another IBM official dismissed the Reuters report as "speculative." At the same time, he wouldn't comment whether or not elements of Blue Gene's technology would be incorporated into IBM's forthcoming console processors.
The article then quotes Richard Doherty as saying that the CPUs in Blue Gene/L are close cousins to the Cell. But since Mr. Doherty isn't an IBM employee, that's not as good as confirmation. Nevertheless, the IBM comments are carefully enough phrased that they don't rule out his statement.
I dont know to much about this stuff, but this thread is a great read, wheather the rumor's true or not.
One thoght struck me though. The orighinal source might very well be right about the tech stuff and simultaneously wrong about the PowerBook "detail". what if there's a G5 PB in september but some kind of "future generation reference platform" released to devs at WWDC?
"PowerTune: Advanced Frequency and Power Scaling on 64b PowerPC Microprocessor 12:00 PM
C. Lichtenau1, M. Ringler2, T. Pflueger1, S. Geissler2, R. Hilgendorf1,
J. Heaslip2, U.Weiss1, P. Sandon2, N. Rohrer2 , E. Cohen2, M. Canada2
1IBM, Boeblingen, Germany
2IBM, Essex Junction, VT
PowerTune is a power-management technique for a multi-gigahertz
superscalar 64b PowerPC® processor in a 90nm technology. This paper
discusses the challenges and implementation of a dynamically controlled
clock frequency with noise suppression as well as a synchronization circuit for a multi-processor system."
It seems to be all theory for the moment....Jobs' mentioning the close of 2004 as a date for the PB is really becoming quite probable, whether or not we see a scaled-down 970-derivative or this cell architecture.
It seems to be all theory for the moment....Jobs' mentioning the close of 2004 as a date for the PB is really becoming quite probable, whether or not we see a scaled-down 970-derivative or this cell architecture.
It's not theory. It's implemented in the 90nm version of the PPC970 which is sampling now. Check the advance brochure for IBM's presentation on the 90nm PPC970 which will be their official announcement of the chip.
Comments
Originally posted by jouster
Ars community
heh. community.
Originally posted by Nr9
Cheap small core like 440 is a step toward the cell base computing.
You know what, this sounds very plausable. As for everyone clammoring about, saying the the G5 needs to go into the Powerbook, let me draw you an example from a very unlikely source... Intel.
When the P4 first came out, it had a very similar problem that the current G5 has; it was bulky, hot, and no way capabible of being stuffed into a laptop, even with a shoehorn.
So what did Intel do? They enhanced their fabs (bringing it to 130 process, I think), used a similar instruction set, and called it the Pentium 4M. I remember how everyone chided them for this advance in computing technology, but it really was a good, smart move on their part.
Now, lets bring this back to IBM. Let's don our speculation caps, shall we. The main reason why we are saying that this wouldn't work is because it isn't of the 9xx series. It seems to be a step backward, doesn't make sense, costs too much, etc etc, yadda yadda yadda.
Now, lets say that the initial batch of 440s are a trial run, seeing if it is feasable, etc etc. Finding out how they can do it, and seeing how difficult it would be to mass produce this. Mass production reduces the cost of the chip. Also, lets say that Apple has had a hand in this (HyperTransport) with their memory controller, et al.
All of the sudden, they have a viable chip that can keep pace with the current G5s. Then this chip becomes the G5m (for lack of better wording).
If we were to believe that this chip-set is destined for the PowerBook line-up, then I think that this would be the approach that they would take.
As for the marketing of the chip, what they would do is market it like this... G5m @ 2 GHz (4 x 500Mhz) - 2.8 GHz (4 x 700 MHz). Remember, people have believed the marketing hype from Intel that MHz matters. So why not use it against them with a chip that we could use it with.
Just something to throw out there.
Originally posted by Nr9
heh. how do you tell that its not mine. its mine.
tomb did just just come from battlefront?
Ok then, perhaps you can explain who the "third parties" are that have already done some work that would help Apple create an implementation of this architecture for Mac OS X?
Perhaps you can explain how each core will run a mini-(Mac)OS? And then maybe you can explain exactly how you can split up a single-threaded application across multiple mini-OSes? How do you "cluster" Powerpoint?
I don't know who you are when you are at home, much less on the Battlefront, and I don't care. What I do care about is that you have made statements that you have inside knowledge about topics you don't seem to understand the implications thereof. That in itself is not unusual, but then you post a blurb that seems to contradict this impression, except that it uses english slang and non-asian syllabic cadences you have not previously exhibited. So I have to wonder, whose explanations (or flights of fancy) are you parroting?
Who knows? Maybe you do have sources and maybe it will happen just the way you say. But the greater probability is that you've just thrown something out there based on guesses and wishing and you were just hoping for a reaction from a bunch of folks here who were disappointed that the G5 ran too hot to go into a Powerbook.
each core runs a extremely small version of mac os x that only has basic MPI function.
powerpoint would have to be rewritten. the user interface, as in current os x is graphic proccessor. you may split the work , for example, in different thread for user input, memory copy, etc. i dont kno how powerpoint work so i dont comment on.
i am no parrot no one. my english is best.
Careful there. You're tipping your hand.
Originally posted by wizard69
The 400 series is available as a core. You take your design automation tools, tack on a few functional units, compile and send to the foundry. It no real mystery and those functional units can be derived from a library or a few of your own. I would not be surprised at this moment in time to hear that AltVec exist as source code some place.
I'm not saying it can't be done. I'm saying it doesn't make sense to do it. The 440 was expressly designed to be extensible. A good SoC solution needs to be extensible because in the embedded market, one size rarely fits all plus an extensible design will have longer legs as far as product family lifecycle goes. (You don't have to retool for every new fad in communications technology.)
So yes, you can add VMX and 440 FPU2 units to the 440 quite handily.
Actually I thought we started out with 2 core processors but that doesn't really matter. The only thing that bothers me about the MCM is that they where expensive, but maybe that is not a problem at the volumns that Apple would use.
Well he said two MCMs with two 440s each. Which is nonsensical at the outset, since an MCM describes the Power4 and Power5 packaging and IBM does not use the terminology elsewhere, to my knowledge. But leaving that aside, there is the issue that what an MCM provides is interchip communications busses. It's purpose is to allow the cores to communicate, so separating them into pairs with only two per MCM is counterproductive if you know you'll need four cores. So I assumed that all four would be on one MCM.
In any event I would suspect that the 440 was used for prototype work. There is a good chance that a follow on to the 400 series may actually make it into the design.
Well, if you want to create imaginary architectures to make Nr9's scenario more plausible, go right ahead.
Well that may be his answer but what would happen if a MMU that supports SMP where tacked onto the core.
There would also have to be support in the core for thread locking, etc. (Means more silicon, more heat.)
This is unix, there is support for communications between processes already. I don't think you would see a major retooling of the operating system. In any event I'm leaning to a more traditional SMP system on a chip.
This is actually a self contradictory two part objection. Please rest assured that (as Nr9 points out) a distributed architecture would require an entirely new programmatic model despite Mac OS X's unix foundations. It would mean rewritting the OS from the ground up. You would not be able to use the Mach kernel, for instance.
As to the second part of your objection, yes an SMP implementation is possible, just not with the 440 core.
Frankly I can't ever recall Nr9 saying that a single thread would run acroos several processors. I'm reasonable sure that was someone else because I responded to that specific post.
Whether he said it or not, it becomes a fundamental requirement as the only alternative is to run it on a slow core effectively undoing any expected perfromance benefit.
My position is that it would be easiest for Apple to go the SMP route on the new chip implementation due to the leveraging of existing software. It would certainly give you the best bang for the buck in the short term. But and it is a big but SMP does not scale forever and not all programs can really make use of it. At some point multiple independant processing units that communicate amongst themselves may be a better idea.
Well, in some applications, the advantages of distributed architectures are overwhelming. But that is not to say that this is true in all cases. Yes, it may be true that there are limits to SMP systems but can you tell me what those limits might be? IBM is heavily invested in the Power5 architecture which is carrying SMP down to the thread level (SMT).
In effect a cluster of SMP units on one motherboard or MCM or SOC.
Sigh. You really can't just jumble up terms like MCM, SoC, SMP and "cluster". Each has a specific meaning in the context of this discussion so you can't posit the integration of seemingly anti-podal or contrasting technologies without a great deal more explanation as to how it would be achieved.
This is not a spooky goverment project. It has the potential to solve a number of issue related to low power operation and high performance.
You miss my point. Right now, the only kinds of applications (software) that use the kind of cellular programming model described are high end, highly parallel, high performance applications such as climatological modeling software run by government agencies and academic institutions.
Why you believe that a bunch of portin will need to be done is beyond me. Sure some system level stuff will have to be done, but there is no reason at all that all traditional programming models could not be supported. What you would be doing is evolving the machine not building a new one.
You'd think so, wouldn't you? But then, you'd be wrong. It would be extremely difficult for any number of reasons, not the least of which is that "ain't no one been there yet".
That is like saying if the 970 comes out with a larger cache its not the 970 anymore.
No, it's more like taking the APU of the PPC 970 and replacing it with a 440 core. Then repeat with the FPUs. And so on.
Ok explain what multithread has to do with SMP. Further do you need SMP to support multithreading. <<<<Trick question>>>>.
You got me. I have no clue what you are talking about.
Please, go here for info you might need.
Again explain no applications for a laptop.
As described, the architecture of the laptop in question is as foreign to Mac OS X applications as the P4 is. (Actually, the P4 is a kissing cousin compared to the implementation described.) So, if Apple were to ship this next week, there would be no software for it.
These are rumors and wild ass geusses you know
That, of course, is the thrust of my argument.
Please give up on the seperate code base thought would you. It shows a complete lack of understanding on what is possible. Believe me many things are possible.
Nope, sorry. Not buying it.
Even worst what is this talk about a new instruction set!!! we have been talking PPC since the begining of this thread.
No, at least some of us have been discussing the cell architecture under development by the STI group. Whether it is implemented starting from PPC or x86 designs won't matter that much. You could begin with transmeta's architecture, but in the end you will have a bunch of instructions that make no sense to any other architecture. The problem space is too divergent. Hence, a new instruction set.
Now, you might be able to convince me it could be done as an extension to an existing ISA, but you'd have to work pretty hard at it.
http://www.appleinsider.com/news/
and the story about the new 90nm PPC970 with... wait for it...
Power Tune!
Originally posted by Tomb of the Unknown
Well he said two MCMs with two 440s each. Which is nonsensical at the outset, since an MCM describes the Power4 and Power5 packaging and IBM does not use the terminology elsewhere, to my knowledge. But leaving that aside, there is the issue that what an MCM provides is interchip communications busses. It's purpose is to allow the cores to communicate, so separating them into pairs with only two per MCM is counterproductive if you know you'll need four cores. So I assumed that all four would be on one MCM.
on the first page, i corrected that it was one MCM with two chips with two cores each.
however, it also has one additional integer only unit, which is used to boot up Mac OS X and provide I/O functions. The rest of the four processors each run a very small OS and are booted after the small controller 440 is booted.
software written with the new MPI libraries Apple will introduce during WWDC will be offloaded to the four 440 chips. There will be a runtime support to run a single thread as a single MPI thread.(i am not sure how this works, but there will be a performance hit)
the extra core is integer only so it only uses about 1 Watt. it is not likely to improve performance, so it is not include in apple's specs
Originally posted by Nr9
this afternoon I talked with some of my sources. There is an important thing they mentioned to me. The overall design is the same, it has 2 processors per chip with 2 chips for 4 processor 440 design.
however, it also has one additional integer only unit, which is used to boot up Mac OS X and provide I/O functions. The rest of the four processors each run a very small OS and are booted after the small controller 440 is booted.
Hmmm. Convenient that you were able to get a hold of your sources to address the question of how applications are prioritized.
Well. Now that we have that straightened out...
software written with the new MPI libraries Apple will introduce during WWDC will be offloaded to the four 440 chips. There will be a runtime support to run a single thread as a single MPI thread. (i am not sure how this works, but there will be a performance hit)
the extra core is integer only so it only uses about 1 Watt. it is not likely to improve performance, so it is not include in apple's specs
OK, then. If I understand you correctly, after the system starts up, four (4) OS images of some kind will load into memory and the controller chip will start scheduling jobs via some kind of Message Passing Interface (MPI) protocol implementation to the images, each of which controls one 440 core?
So to the controller image, it (the rest of the cores) looks like a network of four nodes and processes can be distributed to each node as needed, with the results returned to the controller chip? And there is a method to dedicate a node to any process or thread that can't be broken or parceled out as a distributed process? Am I right so far?
Originally posted by Nr9
I never doubted 90nm G5. what i doubt is that 90nm G5 will be suitable for laptop purposes
Yes, I understand. But you see my position is that it will be easier and less costly to implement a 90nm G5 for the Powerbook than it will be to implement a true cell architecture.
And my case has been significantly strengthened by the info released about "Power Tune" which is obviously an industrial strength speed stepping implementation intended for mobile applications. (Preserves battery power, capische?)
And would that tend to weaken your case for the release of a VT "Big Mac mini-me" Powerbook supercomputer? Hmmm, lets think about that shall we?
Originally posted by Tomb of the Unknown
Hmmm. Convenient that you were able to get a hold of your sources to address the question of how applications are prioritized.
Well. Now that we have that straightened out...
OK, then. If I understand you correctly, after the system starts up, four (4) OS images of some kind will load into memory and the controller chip will start scheduling jobs via some kind of Message Passing Interface (MPI) protocol implementation to the images, each of which controls one 440 core?
So to the controller image, it (the rest of the cores) looks like a network of four nodes and processes can be distributed to each node as needed, with the results returned to the controller chip? And there is a method to dedicate a node to any process or thread that can't be broken or parceled out as a distributed process? Am I right so far?
I am close to the source so I can ask relevant question. It appears that it will be that way.
Power Tune is a fake rumor. it does not exist.
Originally posted by Nr9
It appears that it will be that way.
Well then, I think I can officially say this is bunkum.
What you are describing is pointless. MPI has been around on the Mac for several years in several implementations. It is no magic bullet, and what you describe is just a standard clustering solution. (Except, of course, that you're talking about clustering only four underpowered PPC chips in a laptop.)
This would be a great laptop for running Linpack, it really wouldn't be much use otherwise. And no way is Apple rewriting it's entire OS to ship this laptop, nor would they be developing the prototype processor architecture for desktops in a laptop.
Sorry, but this has nothing to do with cell and is just too unrealistic to be given credence.
Power Tune is a fake rumor. it does not exist.
Well, I guess that will be news to IBM who will be talking about it Monday, February 18th at Noon at the ISSCC. You can read about it in the ISSCC advance program. (page 59 of the PDF).
It can distribute all thread.
WWDC will tell developer to write their app in MPI.
cell is basically just a clustering solution anyways.
my sources did not mention Power Tune and there is no indication it will be used in an Apple product.
However, when Reuters today reported that Blue Gene was "based on microchip technology to be used in gaming consoles due out next year" it set off a torrent of speculation that the supercomputer's processors would be coming soon to living rooms. When contacted by GameSpot, an IBM representative quickly shot the rumor down. "The Blue Gene's chips are totally customized" said the rep. Another IBM official dismissed the Reuters report as "speculative." At the same time, he wouldn't comment whether or not elements of Blue Gene's technology would be incorporated into IBM's forthcoming console processors.
The article then quotes Richard Doherty as saying that the CPUs in Blue Gene/L are close cousins to the Cell. But since Mr. Doherty isn't an IBM employee, that's not as good as confirmation. Nevertheless, the IBM comments are carefully enough phrased that they don't rule out his statement.
there is nothing new, except very high bandwidth, very low power core, lots of cores.
this is what is new. 4 core laptop using cellular computing.
One thoght struck me though. The orighinal source might very well be right about the tech stuff and simultaneously wrong about the PowerBook "detail". what if there's a G5 PB in september but some kind of "future generation reference platform" released to devs at WWDC?
"PowerTune: Advanced Frequency and Power Scaling on 64b PowerPC Microprocessor 12:00 PM
C. Lichtenau1, M. Ringler2, T. Pflueger1, S. Geissler2, R. Hilgendorf1,
J. Heaslip2, U.Weiss1, P. Sandon2, N. Rohrer2 , E. Cohen2, M. Canada2
1IBM, Boeblingen, Germany
2IBM, Essex Junction, VT
PowerTune is a power-management technique for a multi-gigahertz
superscalar 64b PowerPC® processor in a 90nm technology. This paper
discusses the challenges and implementation of a dynamically controlled
clock frequency with noise suppression as well as a synchronization circuit for a multi-processor system."
It seems to be all theory for the moment....Jobs' mentioning the close of 2004 as a date for the PB is really becoming quite probable, whether or not we see a scaled-down 970-derivative or this cell architecture.
Originally posted by fred_lj
It seems to be all theory for the moment....Jobs' mentioning the close of 2004 as a date for the PB is really becoming quite probable, whether or not we see a scaled-down 970-derivative or this cell architecture.
It's not theory. It's implemented in the 90nm version of the PPC970 which is sampling now. Check the advance brochure for IBM's presentation on the 90nm PPC970 which will be their official announcement of the chip.