What I really want to know is how much this chip is going to cost. If its cheap for Apple to put 2 or 4 of these in a machine, then how much will it matter that an expensive P4 (P5) out performs it? Hmmm.... The current Wind-Tunnel G4s raised a few eyebrows when it first came out do to the new case design. These things were designed to disapate heat! A HUGE (7 lbs) heat sink w/ matching fan, a small case fan, 2 fans on the power supply, and a ton of ventalation in the back. WAY more cooling that those 2 little G4s require. I think Apple is trying to avoid the fiasco it had with the Sawtooth (1st gen) G4s where they just slapped a G4 onto a G3 mobo. This time around, I believe they're releasing a new mobo first and then put a new proc in it down the road. I've also read stuff in forums suggesting that the power supply for the Wind-Tunnel had way more juice than the system currently demands. Can anyone out there do the math on this? We know how much power the PPC 970 eats. Can we figure out how much heat the Wind-Tunnel case is designed to disapate? What about how much power the power supply is putting? With these numbers, can we figure out how many PPC 970 the Wind-Tunnel case could power and cool? I've been suffering with a 266MHz G3 iMac, and I refuse to upgrade until Apple comes out with a system that really is worth that premium they charge, and a G4 is not it.</strong><hr></blockquote>
The current "wind-tunnel" PowerMacs are designed for the 1.25GHz G4. Period. End of story.
If this iteration of the G4 didn't need the cooling and power the case and PSU (Power Supply Unit) provides, then Apple could have simply used a lower power PSU, which would be cheaper. Why then would Apple use more expensive PSUs when they could get cheaper ones, therefore raising their profit margins? What benefit would there be to Apple to ship PSUs that are overkill for their purpose? <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
BTW, the 970 will require a motherboard redesign, just like any new generation CPU. Reasons? Incompatible bus, different voltages, etc.
<strong>Also, there is more to this whole 970 thing than has been announced (and what has been announced is much more impressive than some naysayers would believe).</strong><hr></blockquote>
Well, when do you think the whole thing will become evident?
I suspect that the current "Snort-Snout" Powermacs are designed for more than the dual 1.25 GHz G4s. Apple will probably bump them to dual 1.5 GHz G4s without a major case redesign.
Wouldn't it be cool if on the next Powermac revision, NONE of the Powermac models were below 1 GHz? Apple would finally have "broke through" the GHz barrier! It would be an event to remember!
<strong>No reason to change the case then.</strong><hr></blockquote>
You introduce the first mass-market 64-bit workstation using the same ol' boring ElCaptain case? Nah, I don't think it'd be a smart move marketing-wise. Granted, the current case is practically perfect (efficient, easily accessible, now also decently cooled and somewhat expandable) but I have this feeling that the intro of the PPC 970 will "reshape" the Macintosh experience in many senses...
As for the current case designed with hotter CPUs in mind:
1) given the wattage of the PPC 970 I don't think it'll be significantly hotter than a pair of 7455s
2) many people complained about the noise of the original QuickSilver enclosure, and the new WindTunnel might simply be the solution to that problem (more air flow -> fans at lower RPMs -> quieter system)
"Wouldn't it be cool if on the next Powermac revision, NONE of the Powermac models were below 1 GHz? Apple would finally have "broke through" the GHz barrier! It would be an event to remember! "
You introduce the first mass-market 64-bit workstation using the same ol' boring ElCaptain case? Nah, I don't think it'd be a smart move marketing-wise. </strong><hr></blockquote>
[quote]Unless the current memory controller was built with the new bus in mind already and just needs to be enabled differently. and daughter-cards for CPU's tend to isolate most of the rest of the issues as well, as long as the bus is ready. Do we really know? <hr></blockquote>
From a 166MHz single data rate bus to a 900MHz (450MHz DDR) one, still using single channel PC2700? I hope not :eek: The fastest bus it will have been designed to use is probably 200MHz MPX, which isn't that much of a leap forward from 166.
Rapid IO/the 970 bus will require different chipsets from the current one.
Do you know the exact capabilities of the current controller and it's next iteration, including any potential unused functionality? I don't and don't think anyone actively posting here does either, or if they do it's not likely they will say so for awhile.
What we do know is the current design suggests a desire to insulate the memory and PCI bus subsystems design ever farther from the main CPU design. Those types of modularizations tend to reduce the complexity of future changes if they were done with an eye on those future changes.
The 970 may require a radical new MB architecture, or maybe it won't. That really depends on what Apple engineers were doing with the past 2 years of relative stagnation leading up to the Xserve architecture, years they would have had engineering knowledge of the 970 to use as data for design work. If they didn't fold the future 970 possibilities into their work at all it was relatively wasted time, if they did then the current architecture could be an excellent stepping stone.</strong><hr></blockquote>
You bring up an interesting prospect. Technically Apple has complete control over the design of their ASICs. Theoretically (and practically) they can design a ApplePi/RIO/HT controller that uses the same traces to the CPU card as the MPX controller that has the same pin out as the one it replaces. The 970 uses 2 32bit buses and MPX is a single 64bit bus. there should be enough traces to accommodate the 2 ApplePi buses, maybe even an abundance. The motherboards already support DDR RAM..
You bring up an interesting prospect. Technically Apple has complete control over the design of their ASICs. Theoretically (and practically) they can design a ApplePi/RIO/HT controller that uses the same traces to the CPU card as the MPX controller that has the same pin out as the one it replaces. The 970 uses 2 32bit buses and MPX is a single 64bit bus. there should be enough traces to accommodate the 2 ApplePi buses, maybe even an abundance. The motherboards already support DDR RAM..
Unless I am misunderstanding what your point was.</strong><hr></blockquote>
Except that it appears that the 970's bus is differential. The evidence being:
A) The 970 has 161 signal pins (out 576), and only one interface of 64 bits in total, so likely the interface uses 128 datapins for differential signalling, maybe another 8 for bus control, and 25 for processor control signals.
Running 450MHz signals single ended at relatively high voltages would be a nightmare in terms of signal radiation/interference and power dissipation.
Therefore, the new processor requires twice as many traces for a single processor, four times for a dual, unless you change the system architecture, which would beg the question.
I also do not believe that Apple would put a whole different unused bus on the chip just to bump up the volume a bit when they change processor, when it will waste a lot of die space and push up the cost of the chip.
Nor do I believe that Apple would do this from a performance or logistical point of view, any implementation of the bus this early would be likely low performance (and married to a then underperforming memory interface), and untested against final silicon 970, almost certainly requiring a review or redesign before being used in anger.
Except that it appears that the 970's bus is differential. The evidence being:
A) The 970 has 161 signal pins (out 576), and only one interface of 64 bits in total, so likely the interface uses 128 datapins for differential signalling, maybe another 8 for bus control, and 25 for processor control signals.
Running 450MHz signals single ended at relatively high voltages would be a nightmare in terms of signal radiation/interference and power dissipation.
Therefore, the new processor requires twice as many traces for a single processor, four times for a dual, unless you change the system architecture, which would beg the question.
I also do not believe that Apple would put a whole different unused bus on the chip just to bump up the volume a bit when they change processor, when it will waste a lot of die space and push up the cost of the chip.
Nor do I believe that Apple would do this from a performance or logistical point of view, any implementation of the bus this early would be likely low performance (and married to a then underperforming memory interface), and untested against final silicon 970, almost certainly requiring a review or redesign before being used in anger.
michael</strong><hr></blockquote>
I would argue points A and B but I realize that it would be easier to have in development 2 boards, one for the G4 and one for the 970, rather than design a board that could support 2 buses (a nightmare I'd imagine). But you never know with Apple...
All this talk about VMX units avoids the pivotal question:
How many cycles does the PPC 970 need to execute X number of Y VMX operators. For example if I had four permute functions in a row, how many cycles would it take to execute?
One of the advantages of VMX (and PowerPC in general) is the ability to predict in advance how long it will take to execute instructions in a particular order (excluding branch operators).
One of the more interesting aspects I would be interested in is how does the PPC 970 manage flushing memory to and from main, AGP, and peripheral. Having to copy memory via the CPU is inefficient. Also would there be any point to an external cache if memory can be accessed at 6.4GB/sec.
This PDF from motorola says that the MPC7455 only has a 133mhz bus. The supposed new MPC7457 has a 166mhz-200mhz bus. Then I have to ask what is apple using now? Granted these are the embedded versions but they are still G4's. How do we know for sure that the current PowerMacs don't have MPC7457s in them. After all the MPC7455 is only supposed to go up to 1Ghz but we are at 1.25Ghz. If the new PowerMacs do indeed have MPC7457's already in them then the new MPC7457-RM may be out in Jan. What do you think? I can't find any where that the MPC7455 has a faster than 133mhz bus or goes over 1Ghz. Could apple have hacked it?
\tSo I suspect that early next year according to these motorola documents that we will see a 200Mhz Bus 1,1.25, and 1.5GHz machines. But that MPC7457-RM according to motorola will go over 2ghz.
\t\tAny way I just thought all of this was interesting.
This PDF from motorola says that the MPC7455 only has a 133mhz bus. The supposed new MPC7457 has a 166mhz-200mhz bus. Then I have to ask what is apple using now? Granted these are the embedded versions but they are still G4's. How do we know for sure that the current PowerMacs don't have MPC7457s in them. After all the MPC7455 is only supposed to go up to 1Ghz but we are at 1.25Ghz. If the new PowerMacs do indeed have MPC7457's already in them then the new MPC7457-RM may be out in Jan. What do you think? I can't find any where that the MPC7455 has a faster than 133mhz bus or goes over 1Ghz. Could apple have hacked it?
\tSo I suspect that early next year according to these motorola documents that we will see a 200Mhz Bus 1,1.25, and 1.5GHz machines. But that MPC7457-RM according to motorola will go over 2ghz.
\t\tAny way I just thought all of this was interesting.</strong><hr></blockquote>
the answer is on page 2 of your pdf-document:
7455 will add_ 150/166Mhz 60x/MPX bus * -> shipped initial with 133Mhz MPX....
so apple is using currently the 7455 with 133 oand with 166Mz MPX bus... so what? ...
further information: the 7457 will add 200Mhz MPX bus...!
but i also must say that these pdf-motorola-documents say 1.8Gig on one and 1.3Gig on the other ...
I think thats because the embedded version of the MPC7457 will only go to 1.3 but the desktop version, that apple uses, will go to 1.8. The frist page is just about the embedded market. So it looks like 2Q-03 we will see 1.8ghz G4s with 200Mhz bus's. 4Q-03 maybe we'll see the 970.
Here is another good article about the PPC 970. It was written by my friend David K. Every (remember him from MacWEEK?) and focusses on a few things that the ArsTech article left out. (remember him from MacWEEK?)
Comments
<strong>Speculation:
( <a href="http://slashdot.org/comments.pl?sid=43568&threshold=0&commentsort=0&ti d=136&mode=thread&cid=4552400" target="_blank">reposted from /. </a> )
What I really want to know is how much this chip is going to cost. If its cheap for Apple to put 2 or 4 of these in a machine, then how much will it matter that an expensive P4 (P5) out performs it? Hmmm.... The current Wind-Tunnel G4s raised a few eyebrows when it first came out do to the new case design. These things were designed to disapate heat! A HUGE (7 lbs) heat sink w/ matching fan, a small case fan, 2 fans on the power supply, and a ton of ventalation in the back. WAY more cooling that those 2 little G4s require. I think Apple is trying to avoid the fiasco it had with the Sawtooth (1st gen) G4s where they just slapped a G4 onto a G3 mobo. This time around, I believe they're releasing a new mobo first and then put a new proc in it down the road. I've also read stuff in forums suggesting that the power supply for the Wind-Tunnel had way more juice than the system currently demands. Can anyone out there do the math on this? We know how much power the PPC 970 eats. Can we figure out how much heat the Wind-Tunnel case is designed to disapate? What about how much power the power supply is putting? With these numbers, can we figure out how many PPC 970 the Wind-Tunnel case could power and cool? I've been suffering with a 266MHz G3 iMac, and I refuse to upgrade until Apple comes out with a system that really is worth that premium they charge, and a G4 is not it.</strong><hr></blockquote>
The current "wind-tunnel" PowerMacs are designed for the 1.25GHz G4. Period. End of story.
If this iteration of the G4 didn't need the cooling and power the case and PSU (Power Supply Unit) provides, then Apple could have simply used a lower power PSU, which would be cheaper. Why then would Apple use more expensive PSUs when they could get cheaper ones, therefore raising their profit margins? What benefit would there be to Apple to ship PSUs that are overkill for their purpose? <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
BTW, the 970 will require a motherboard redesign, just like any new generation CPU. Reasons? Incompatible bus, different voltages, etc.
<strong>Also, there is more to this whole 970 thing than has been announced (and what has been announced is much more impressive than some naysayers would believe).</strong><hr></blockquote>
Well, when do you think the whole thing will become evident?
Wouldn't it be cool if on the next Powermac revision, NONE of the Powermac models were below 1 GHz? Apple would finally have "broke through" the GHz barrier! It would be an event to remember!
<strong>No reason to change the case then.</strong><hr></blockquote>
You introduce the first mass-market 64-bit workstation using the same ol' boring ElCaptain case? Nah, I don't think it'd be a smart move marketing-wise. Granted, the current case is practically perfect (efficient, easily accessible, now also decently cooled and somewhat expandable) but I have this feeling that the intro of the PPC 970 will "reshape" the Macintosh experience in many senses...
As for the current case designed with hotter CPUs in mind:
1) given the wattage of the PPC 970 I don't think it'll be significantly hotter than a pair of 7455s
2) many people complained about the noise of the original QuickSilver enclosure, and the new WindTunnel might simply be the solution to that problem (more air flow -> fans at lower RPMs -> quieter system)
ZoSo
Lemon Bon Bon
<strong>
You introduce the first mass-market 64-bit workstation using the same ol' boring ElCaptain case? Nah, I don't think it'd be a smart move marketing-wise. </strong><hr></blockquote>
Beige G3 --> PM 3400 etc. case
G3 PowerBook --> PB 5300 case
Get 'em to buy the processor.
Then get 'em buy the new machine.
From a 166MHz single data rate bus to a 900MHz (450MHz DDR) one, still using single channel PC2700? I hope not :eek: The fastest bus it will have been designed to use is probably 200MHz MPX, which isn't that much of a leap forward from 166.
Rapid IO/the 970 bus will require different chipsets from the current one.
<strong>
Do you know the exact capabilities of the current controller and it's next iteration, including any potential unused functionality? I don't and don't think anyone actively posting here does either, or if they do it's not likely they will say so for awhile.
What we do know is the current design suggests a desire to insulate the memory and PCI bus subsystems design ever farther from the main CPU design. Those types of modularizations tend to reduce the complexity of future changes if they were done with an eye on those future changes.
The 970 may require a radical new MB architecture, or maybe it won't. That really depends on what Apple engineers were doing with the past 2 years of relative stagnation leading up to the Xserve architecture, years they would have had engineering knowledge of the 970 to use as data for design work. If they didn't fold the future 970 possibilities into their work at all it was relatively wasted time, if they did then the current architecture could be an excellent stepping stone.</strong><hr></blockquote>
You bring up an interesting prospect. Technically Apple has complete control over the design of their ASICs. Theoretically (and practically) they can design a ApplePi/RIO/HT controller that uses the same traces to the CPU card as the MPX controller that has the same pin out as the one it replaces. The 970 uses 2 32bit buses and MPX is a single 64bit bus. there should be enough traces to accommodate the 2 ApplePi buses, maybe even an abundance. The motherboards already support DDR RAM..
Unless I am misunderstanding what your point was.
<strong>
You bring up an interesting prospect. Technically Apple has complete control over the design of their ASICs. Theoretically (and practically) they can design a ApplePi/RIO/HT controller that uses the same traces to the CPU card as the MPX controller that has the same pin out as the one it replaces. The 970 uses 2 32bit buses and MPX is a single 64bit bus. there should be enough traces to accommodate the 2 ApplePi buses, maybe even an abundance. The motherboards already support DDR RAM..
Unless I am misunderstanding what your point was.</strong><hr></blockquote>
Except that it appears that the 970's bus is differential. The evidence being:
A) The 970 has 161 signal pins (out 576), and only one interface of 64 bits in total, so likely the interface uses 128 datapins for differential signalling, maybe another 8 for bus control, and 25 for processor control signals.
Therefore, the new processor requires twice as many traces for a single processor, four times for a dual, unless you change the system architecture, which would beg the question.
I also do not believe that Apple would put a whole different unused bus on the chip just to bump up the volume a bit when they change processor, when it will waste a lot of die space and push up the cost of the chip.
Nor do I believe that Apple would do this from a performance or logistical point of view, any implementation of the bus this early would be likely low performance (and married to a then underperforming memory interface), and untested against final silicon 970, almost certainly requiring a review or redesign before being used in anger.
michael
<strong>
Except that it appears that the 970's bus is differential. The evidence being:
A) The 970 has 161 signal pins (out 576), and only one interface of 64 bits in total, so likely the interface uses 128 datapins for differential signalling, maybe another 8 for bus control, and 25 for processor control signals.
Therefore, the new processor requires twice as many traces for a single processor, four times for a dual, unless you change the system architecture, which would beg the question.
I also do not believe that Apple would put a whole different unused bus on the chip just to bump up the volume a bit when they change processor, when it will waste a lot of die space and push up the cost of the chip.
Nor do I believe that Apple would do this from a performance or logistical point of view, any implementation of the bus this early would be likely low performance (and married to a then underperforming memory interface), and untested against final silicon 970, almost certainly requiring a review or redesign before being used in anger.
michael</strong><hr></blockquote>
I would argue points A and B but I realize that it would be easier to have in development 2 boards, one for the G4 and one for the 970, rather than design a board that could support 2 buses (a nightmare I'd imagine). But you never know with Apple...
How many cycles does the PPC 970 need to execute X number of Y VMX operators. For example if I had four permute functions in a row, how many cycles would it take to execute?
One of the advantages of VMX (and PowerPC in general) is the ability to predict in advance how long it will take to execute instructions in a particular order (excluding branch operators).
One of the more interesting aspects I would be interested in is how does the PPC 970 manage flushing memory to and from main, AGP, and peripheral. Having to copy memory via the CPU is inefficient. Also would there be any point to an external cache if memory can be accessed at 6.4GB/sec.
This PDF from motorola says that the MPC7455 only has a 133mhz bus. The supposed new MPC7457 has a 166mhz-200mhz bus. Then I have to ask what is apple using now? Granted these are the embedded versions but they are still G4's. How do we know for sure that the current PowerMacs don't have MPC7457s in them. After all the MPC7455 is only supposed to go up to 1Ghz but we are at 1.25Ghz. If the new PowerMacs do indeed have MPC7457's already in them then the new MPC7457-RM may be out in Jan. What do you think? I can't find any where that the MPC7455 has a faster than 133mhz bus or goes over 1Ghz. Could apple have hacked it?
\tSo I suspect that early next year according to these motorola documents that we will see a 200Mhz Bus 1,1.25, and 1.5GHz machines. But that MPC7457-RM according to motorola will go over 2ghz.
\t\tAny way I just thought all of this was interesting.
Page 2 says that the 7455 introduces a 150/166MHz bus, and the 7457 will intro a 200Mhz bus.
Apple uses a part with a GHz rating tested on Apple or simulated Apple hardware.
The Dual 867 uses a 133MHz bus
The Dual 1GHz and 1.25GHz use 166MHz busses.
I think I speak for everyone here... To hell with Motorola!
Barto
[ 10-31-2002: Message edited by: Barto ]</p>
<strong><a href="http://e-www.motorola.com/brdata/PDFDB/docs/PPCSALESFACT.pdf"; target="_blank">http://e-www.motorola.com/brdata/PDFDB/docs/PPCSALESFACT.pdf</a>;
This PDF from motorola says that the MPC7455 only has a 133mhz bus. The supposed new MPC7457 has a 166mhz-200mhz bus. Then I have to ask what is apple using now? Granted these are the embedded versions but they are still G4's. How do we know for sure that the current PowerMacs don't have MPC7457s in them. After all the MPC7455 is only supposed to go up to 1Ghz but we are at 1.25Ghz. If the new PowerMacs do indeed have MPC7457's already in them then the new MPC7457-RM may be out in Jan. What do you think? I can't find any where that the MPC7455 has a faster than 133mhz bus or goes over 1Ghz. Could apple have hacked it?
\tSo I suspect that early next year according to these motorola documents that we will see a 200Mhz Bus 1,1.25, and 1.5GHz machines. But that MPC7457-RM according to motorola will go over 2ghz.
\t\tAny way I just thought all of this was interesting.</strong><hr></blockquote>
the answer is on page 2 of your pdf-document:
7455 will add_ 150/166Mhz 60x/MPX bus * -> shipped initial with 133Mhz MPX....
so apple is using currently the 7455 with 133 oand with 166Mz MPX bus... so what? ...
further information: the 7457 will add 200Mhz MPX bus...!
but i also must say that these pdf-motorola-documents say 1.8Gig on one and 1.3Gig on the other ...
<img src="graemlins/oyvey.gif" border="0" alt="[No]" /> <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
<a href="http://www.igeek.com/browse.php?id=1101"; target="_blank">http://www.igeek.com/browse.php?id=1101</a>;
--
Ed M.