Datamuncher

Its better to look at SoC density at a macro level than a micro level when comparing process density between TSMC, Intel and others. A quick comparison of the 16nm (16FFC) A10 vs. the 14nm Quad Skylake shows that TSMC/Apple squeeze in a much higher transistor density. Skylake has higher performance but does less in terms of an SoC (the PCH is a separate chip, plus A10 includes things like a sensor hub as well).

Quad-core + GPU GT2 Core i7 Skylake K       1.75B Transistors       122mm^2 Apple A10                                                         3.3B Transistors         125mm^2    The head of manufacturing has already done analysis about how Apple/TSMC has managed to obtain greater transistor density. - Apple uses a higher percentage of SRAM in their SoCs (though other research indicates that Intel mis-categorized some of Apple's reg. files as SRAM) - Intel uses a higher percentage of cells that are larger than the minimum process geometries for performance (tall cells). - Intel acknowledges that the Apple A8 (TSMC 20nm) and Apple A9 (16nm TSMC and 14nm Samsung) have greater RAW TRANSISTOR DENSITY than similar Broadwell (14nm) or Skylake (14nm) SoCs - Intel has created their own notion, a normalized transistor density, that shows them somewhat ahead, but requires some questionable reverse engineering of exactly what types of logic and memory Apple has included in each block of their SoCs. See foils 19 and 20. http://files.shareholder.com/downloads/INTC/0x0x862743/F8C3E42B-7DA9-4611-BB51-90BED3AA34CD/2015_InvestorMeeting_Bill_Holt_WEB2.pdf ;