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MacWorld in New York - 2002 is Apple's year - Page 4

post #121 of 620
My money is on Nvidia also. Given their recent hint.

So, Programmer, the e500, if it can have 'more than one core' could be dual core?

:confused:

If...Apple wishes it?

Lemon Bon Bon <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
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post #122 of 620
I took this:
<strong>And rumor is that e500 core will soon be joined by another high performance core.
</strong>
to be a reference to the previous comment about collaboration with another company.

Another core? A different core?! <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />

Screed ...mayhaps I'm reading this incorrectly.
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post #123 of 620
"Another core? A different core?! "

Different? And what would that 'other' and 'different' core do?

In effect, Apple can lego build their ripost to Itanic 2 and Sledgehammer?

Dorsal, are you saying that the e500 is similar in performance to the G4 bar the fact it is 64 bit? Extra integer? No extra fpu units? The altivec? No 256 bit version? Will its frequency start at the oft stated 2 gighz?

So...the way forward is to increase frequency? And maybe stick two of them together...dual core?

Sounds exciting but...with a note of caution on a same mhz performance. But if it starts at 2 gig then...that offsets that..? Can 7 stage pipeline stretch to 2 gighz frequency? The Hammer is doing better on same frequency...up to 40%!

Modularity. So. It's looking like San Fran if the e500 is sampling now?

Lemon Bon Bon <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />

[ 06-17-2002: Message edited by: Lemon Bon Bon ]</p>
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post #124 of 620
This is what i fond about the e500 core on the motorola web site:
Developper Forum July 21-24, 2002
Motorola and IBM have announced the embedded version of the PowerPC architecture (Book E), and implementations are beginning to emerge. This session will address the impact on user applications and real-time operating systems, and the advantages of migrating to Book E. These issues and others about the coming transition will be answered by the designer of and principal contributor to the PowerPC Programming Environments Manual.

Interesting...
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post #125 of 620
the e500 can be dual core (maybe quad, octo?)
There is a diagram on motorola web site. Look for the MPC8540FACT.pdf
That diagram shows that each core has in own bus memory ! If we keep in mind that the e500 core is 600-1000 Mhz, we can have this:
1.2 / 2.0 / 2.4 / 4.0 Ghz WOW! (just for dual and quad).

[ 06-17-2002: Message edited by: jeromba ]</p>
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post #126 of 620
[quote]Originally posted by jeromba:
<strong>the e500 can be dual core (maybe quad, octo?)
There is a diagram on motorola web site. Look for the MPC8540FACT.pdf
That diagram shows that each core has in own bus memory ! If we keep in mind that the e500 core is 600-1000 Mhz, we can have this:
1.2 / 2.0 / 2.4 / 4.0 Ghz WOW! (just for dual and quad).

[ 06-17-2002: Message edited by: jeromba ]</strong><hr></blockquote>

If myy understanding of multi-core chips is correct, they are basically a MP design on one die. You would have a 600 mhz-1 Ghz for all of those chips, just like you have a Dual 1 Ghz MP tower, not a 2 Ghz tower now.
post #127 of 620
yes sorry you're right but that's the name of it that do me wrong... e500 core...
some pics to clear some minds:



[ 06-17-2002: Message edited by: jeromba ]</p>
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post #128 of 620
So...

Dorsal posts with what is a reasonably pragmatic, reasonably expected G4 system at NY.

Then he goes and spoils it by posting some desirable G5 snippet. With no clue about timeframe.

Drat.
post #129 of 620
Just for fun, I'll add my 2 cents to the topics in this thread.

Dorsal

I remain neutral on my opinion of his actual knowledge of future Apple products. All I know is his past posts have included a range of Mobos for his company to review. When he's correct on one of his vague predictions, people begin the chant... Dorsal, Dorsal... Don't get me wrong, I enjoy reading his posts as much as the next person. It's just that I've seen a wide range of products he supposedly tested. These wide range of motherboards also seem to reflect what has been discussed as possibilities anyway. My point - though his posts are generally interesting, I've seen nothing substantial to make me believe he truly has inside information. If his prediction of Apple working with another company (such as nVidia -N Force ), then I might start to take his posts more seriously. Until then, it's sheer entertainment for me.

Workstation graphics

The difference between high end graphics cards (like Oxygen) and high end consumer cards (nVidia Geforce 4 Ti) are diminishing very quickly. That is, the consumer cards are advancing at a much faster rate. The main difference used to be the much larger amount of texture memory and the onboard TC&L engines, etc.

Also, someone posted that games use something like 10,000 polygons per scene and pro scenes use something like 100,000 polygons. The thing is, the newer game engines are using polygon counts in the 100,000 range. The older Quake 3 and UT used closer to 10,000 polygons per scene. However, I read an article that was talking about the game engine in Unreal 2 (and UT 2003). One tree in the scene used more polygons than an entire scene in the previous generation game engine. The same is true with engine used in the upcoming Doom 3.

Jobs/Apple Doomed

Finally, those that think Jobs is going to have objects thrown at him for coming out with "only" dual 1.2 GHZ G4s, etc. have obviously never been to a Macworld event. RDF is in full force. It even works on PC types (trust me, I've seen it). Seriously though, this type of nonsense is said both before and after just about every Macworld event. Apple is not doomed for being behind in MHZ. Anyone that understands the fundamental difference between PCs and Macs knows this. Companies don't just flip flop on hardware platforms based on what someone else is doing. If Apple were to truly stagnate for any long period of time, then, they might be in trouble. However, even during the 18 month G4 stagnation, Apple was able to hold out by offering multiple processors, etc.

Steve
post #130 of 620
The other 'core': IBM's 'Cell' Project.

TING5
Suckfuldotwhatever, dude.

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It's the FSB, not the proc speed that is the problem. Your fire engine isn't worth sh:t no matter how big the pump is if it uses a garden hose to put out fires. Let's at...
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post #131 of 620
With the kind of power described here, it is obvious that Apple will have a replacement for powermacs but that they might leap in price. That would leave room for an SE iMac with either a 17 or 19" screen to fill the low end of the pro-market. If the chip is really that modular then it will allow Apple to introduce a "SuperMac" with maybe 4 or 8 cores to take the market straight out from under SGI's feet.



[ 06-17-2002: Message edited by: Addison ]</p>
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post #132 of 620
[quote]Originally posted by There is no g5:
<strong>The other 'core': IBM's 'Cell' Project.

TING5</strong><hr></blockquote>

<a href="http://www.eetimes.com/story/OEG20010313S0113" target="_blank">IBM, Sony, Toshiba team on processor architecture for broadband</a>

[quote]<strong>Sony Computer Entertainment Inc. (SCEI), IBM Corp. and Toshiba Corp. announced a major partnership aimed at creating a processor architecture code-named Cell that will be optimized for multimedia packet processing over the broadband network.</strong><hr></blockquote>

<img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />

[quote]<strong>The goal is to have the first Cell products ready by 2004 or 2005, based on a "10S" 100-nm (0.10-micron) process technology that moves to commercial production early in 2003 at IBM.</strong><hr></blockquote>

<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />

Screed
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post #133 of 620
Keep in mind that everything Dorsal said is publiclly available. Perfect example is that diagram from Motorola's site.

Not discounting what Dorsal is saying...just trying to keep things in perspective.
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post #134 of 620
<strong>There will be an e500 core based desktop processor based on Apple's requirements. The e500 core is a 7 stage pipeline design very similar to the 7455 core (they both get about 2300MIPS). The execution units are very similar, in quantity and performance.</strong>

Well, I would say that the e500 and the 7455 core are "similar", although not "very similar"... Did you really get MPC7500 prototypes as you reported a few months ago? I have only seen block diagrams and text so far, and I couldn't find anyone who could confirm the 7500 is really sampling. Maybe we should note that the e500 (as I know it) is a pure 32 bit design, 64 bits will be introduced with an e500 successor.

<strong>There is an Altivec add on built for the e500.</strong>

As far as I can say Altivec has been implemented as APU, connected to the e500 via OCEAN. It seems the same is true for the FPU, it looks like the FPU is not part of the e500 itself. I hope this doesn't affect the performance in a negative way.

<strong>Apple's implimentation has dual RIO ports and a memory controller. The interconnect is the e500 native OCEAN and this is a wide/fast bus, only for on die interconnects.</strong>

On the block diagrams I saw the memory controller was the same as the 8540 controller, this means 266/333 Mhz DDR on a 133/166 Mhz Bus.

<strong>Multiprocessing in handled via RapidIO's 16 bit variant. It connects to a RapidIO hub (RIOH) that serves as the central hub for various RIO devices, such as peripheral controllers, PCI controllers, other PowerPC processors, network processors, etc. The hub controls the bit width and frequency, and this is determined by the distance from the hub (trace length). If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency. To connect to a PCI controller you can keep the 16 bit wide port or if pin out is an issue you may need to drop it to 8 bit and run it at a lower frequency such as 500MHz. RIO is capable of over 7GBps bandwidth running at 16bit.</strong>

This will rock, hehe...

<strong>The beauty of Book E is the modularity. The way Motorola designed it was so a customer can pick and choose the components.</strong>

Right, customers can even design their own circuits an connect them as APUs via the OCEAN crossbar switch.

<strong>this was as long as the customer had the money to spend as I imagine this is not an inexpensive proposistion. But it is an ideal solution for Apple. They can choose the size of the L2 cache, number of e500 cores, kind of memory controllers available, if they wanted a PCI controller also embedded...</strong>

Ethernet is also available as component, although I do not believe this will be implemented directly into the CPU.

<strong>And rumor is that e500 core will soon be joined by another high performance core.</strong>

As far as I know they're working on a high performance 64 bit version of the core, but I have no information about when this could be ready (I even can't say when the e500 based 7500 will be ready, I guess Dorsal can tell us more about possible release dates).
post #135 of 620
[quote]Originally posted by SteveS:
<strong>Workstation graphics

The difference between high end graphics cards (like Oxygen) and high end consumer cards (nVidia Geforce 4 Ti) are diminishing very quickly. That is, the consumer cards are advancing at a much faster rate. The main difference used to be the much larger amount of texture memory and the onboard TC&L engines, etc.
</strong><hr></blockquote>

From what I have heard, a large part of the difference between high-end workstation graphics cards and the consumer versions comes down to the drivers. Pro cards have their drivers certified by a third-party QC certification entity for things like CAD accuracy need to be very free of bugs. Some cards' drivers are specially tuned for certain applications. An example of this is the ATI Mobility Fire GL 7800 (used in the IBM A-series mobile workstations), which is in fact the same card as the Radeon Mobility 7500, but with certified drivers, optimized for optimum OpenGL performance. Presumably, this is at the expense of performance in other areas, which is not suitable for consumer/prosumer use (including 2D graphics).

As for the use/need for 64-bit processors, while I agree that it is unnecessary for most people, it is crucial for marketing and market-share. Apple can once again claim to be leading in hardware innovation, and if it results in leading-edge benchmarks in high-end database and scientific computing, then IT-folks will have a new respect for Apple products and will be less likely to spout crap about Apple products being underpowered. It's hard to make that argument when someone can retort with high-end computing benchmarks.
post #136 of 620
[quote]Originally posted by haderach:
<strong>
Well, I would say that the e500 and the 7455 core are "similar", although not "very similar"... Did you really get MPC7500 prototypes as you reported a few months ago? I have only seen block diagrams and text so far, and I couldn't find anyone who could confirm the 7500 is really sampling. Maybe we should note that the e500 (as I know it) is a pure 32 bit design, 64 bits will be introduced with an e500 successor.
</strong><hr></blockquote>

Hmmm... you're right. For some reason I thought that the e500 was 64-bit, but I can't find anything to indicate that it is. It makes sense then that the new core will be the 64-bit one. I wonder if IBM is designing the 64-bit core? That would be odd, wouldn't it...

The OCEAN cross-bar is capable of 128 Gb/sec (=16 GB/sec), which doesn't seem all that fast... but its on-chip so its speed will be a function of clock rate and the highest they mention is 1 GHz. At 2 GHz it'll be twice as fast. Its also not clear if that is the point-to-point speed, or the overall net throughput through the entire cross-bar. It should be fast enough for now, however. It sounds like it could let Apple put multiple FPUs and VPUs onto the chip. This kind of an architecture should really suit Apple well since it can custom build its own designs.

A multi-core design would have more than one e500 core connected via the OCEAN switch. They'd probably share the on-chip bus/cache/memory controller.

I doubt we'll see it this year though (although I'd love to be surprised on this one!).
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post #137 of 620
[quote]Originally posted by Jonathan Brisby:
<strong> In this way we will create a new bread of human,</strong><hr></blockquote>

Soylent Green ?
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post #138 of 620
[quote]Originally posted by Dorsal M:
<strong> If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency.</strong><hr></blockquote>

Let's look at that again.

[quote]Originally posted by Dorsal M:
<strong> If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency.</strong><hr></blockquote>

Does this mean a 2GHz chip? It can't! Can it?
post #139 of 620
[quote]Originally posted by BobtheTomato:
<strong>Soylent Green ?</strong><hr></blockquote>

"You gotta eat all the old people! Eat all the old people. . ."
post #140 of 620
hmmm... Digital dna
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post #141 of 620
[quote]Originally posted by DaveLee:
<strong>So...

Dorsal posts with what is a reasonably pragmatic, reasonably expected G4 system at NY.

Then he goes and spoils it by posting some desirable G5 snippet. With no clue about timeframe.

Drat.</strong><hr></blockquote>


I don't understand why this "spoils" it?
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post #142 of 620
[quote]Originally posted by speechgod:
<strong>

Does this mean a 2GHz chip? It can't! Can it?</strong><hr></blockquote>

No, it means a 2 GHz bus. It is asynchronous from the chip, remember? It would be a switch to have the bus at a higher clock rate than the chip, wouldn't it? But its 4x narrower, so the next speed up is on the order of "only" 4x.
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post #143 of 620
From Motorola 'The Programming Environments Manual': The PowerPC architecture is a 64-bit architecture with a 32-bit subset. This manual
describes the architecture from a 32-bit perspective. Although some 64-bit resources are
discussed, this manual does not completely describe details of the 64-bitonly features of
the architecture, in particular with respect to the memory management model, registers, and
instruction set.
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post #144 of 620
Once more onto the breach...

In short, the e500 core sucks. In a little more detail, the MPC 8540 really sucks for Apple.

Dorsal M looks to be talking from whitepapers to me, and all that doesn't even seem correct. From a MIPS point view the 8540 gets 2300 MIPS at 1 GHz on 0.13u process. The 7455 get 2300 MIPS at 1 GHz on a 0.18u SOI process. This is telling me that the 8540 is 4 stage execution pipeline, not 7. I can guarantee that a 7455 when manufactured on a 0.13u process will clock 50% higher than the 8540 and therefore have 50% greater performance. There is nothing to gain from the 8540 for Apple. Nothing. If Apple wants a low Watt processor, IBM's 750fx will be fine, and is already shipping, as well as a 1 GHz 7455 of which a 1 GHz 8540 purports to match in performance 6 months from now.

If there is a 4-way superscaler out-of-order superpipelined (10+ stages) Book E base PPC coming out, then it holds promise for Apple. The MPC 8540 and e500 which it's based do not.
post #145 of 620
Does the E500 core have an FPU, or would that be a seperate addition to the overall chip like Altivec? I'm just curious, because if it's included in the core, a multi-core chip would then have an automatic increase in FPU performance.

Just a thought.
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post #146 of 620
Quote from above: "Sony Computer Entertainment Inc. (SCEI), IBM Corp. and Toshiba Corp. announced a major partnership aimed at creating a processor architecture code-named Cell that will be optimized for multimedia packet processing over the broadband network."

This processor is supposed to become the CPU of the PlayStation3. But who knows ...
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post #147 of 620
Ack! Bad post.

[ 06-17-2002: Message edited by: THT ]</p>
post #148 of 620
Yep read that 2 somewhere...

what I remember :

Cell-processor will be suitable for computers though and allow you to combine the power of multiple PS3 processors over networks (maybe pc's)

speed of this new processors would be way faster then anything we can see today (think 'bout 100s of time faster)
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post #149 of 620
and the countdown to Kormac showing up starts...

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post #150 of 620
<strong>Originally posted by haderach:
There is an Altivec add on built for the e500.

As far as I can say Altivec has been implemented as APU, connected to the e500 via OCEAN. It seems the same is true for the FPU, it looks like the FPU is not part of the e500 itself. I hope this doesn't affect the performance in a negative way.</strong>

It doesn't make sense for APUs to be connected by the Ocean fabric. APUs have to be directly connected to the e500's dispatch unit, completion unit and registers. So they must be inside the e500 core itself.

The e500 then has another unit outside of it that controls access to L2 cache and the memory controller. It is this unit that connects the e500 core to the Ocean fabric. The Ocean fabric then acts as a network for all the I/O on the CPU. Ie, PCI, Ethernet, DMA, RapidIO, etc.

<strong>RIO is capable of over 7GBps bandwidth running at 16bit.

This will rock, hehe...</strong>

RapidIO is 4 bytes per clock per channel and seems to have limit of 1 GHz in the spec. For a 16 bit 1 GHz RapidIO bus that's 16 bit x 2 (it's DDR) x 1 GHz = 4 GBytes/s. One can probably increase the bandwidth more by adding more buses. But the RapidIO devices coming out in the near future probably won't clock over 500 MHz.

<strong>The beauty of Book E is the modularity. The way Motorola designed it was so a customer can pick and choose the components.

Right, customers can even design their own circuits an connect them as APUs via the OCEAN crossbar switch.</strong>

I don't think so.

The Ocean fabric connects I/O, not processor execution units. It can maybe connect multiple e500 cores together, but I really doubt that.
post #151 of 620
I have not been following the G5 discussion too closely, so please forgive me for my question:

Will the G5 (64-bit version) be similar in construction to the AMD hammers in that it will basically still be a 32-bit processor with an added 64-bit unit?
post #152 of 620
[quote]Originally posted by THT:
Dorsal M looks to be talking from whitepapers to me, and all that doesn't even seem correct. <hr></blockquote>

[quote]Originally posted by Bodhi:
Keep in mind that everything Dorsal said is publiclly available. Perfect example is that diagram from Motorola's site.

Not discounting what Dorsal is saying...just trying to keep things in perspective.
<hr></blockquote>

You know, I'm not trying to pick on the guy, since he's about the only that keeps this place exciting nowadays. How many people can get pages and pages of replies on just a couple of posts?

However, speaking as a pathological liar, you have to keep your story straight (honest-- I wouldn't be making this up).

Let's do a little karaoke while I type along:

When that shark bites

The original Dorsal was supposed to be testing hardware.

With its teeth babe

His posts were about how fast the widgets went, and what widgets were lying around the board.

Scarlet billows start to spread...

Now the posts are more like design papers (white papers).

...Oh the line forms on the right, babe.

I'm not sure what this all means, but I've always had this thing about being shark bait. I'm beginning to think Dorsal is blowing bubbles.

BTW: Haven't you ever wondered what really happened to Miss Lotte Lenya?
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post #153 of 620
"It sounds like it could let Apple put multiple FPUs and VPUs onto the chip. "

<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />

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post #154 of 620
[quote]Originally posted by ZoSo:
<strong>
The Hammer family will not only be a 64-bit family--it's already (see the early tests on the prototypes) a huge accomplishment efficiency-wise. The Opteron is already 40% (or so THG quoted some e-zine saying) faster than an Athlon at the same clock speed executing non-optimized 32-bit code. :eek:

That's no 64-bit myth, that's a hell of great design... Apple simply can't afford to be left behind on this issue, period. We need a 64-bit PowerPC CPU, because so the market dictates.</strong><hr></blockquote>

A large portion of the Hammer-series' performance gain has come through the use of an on-chip memory controller and other architechtural changes/improvements. The addition of 64-bit instructions hasn't been to improve performance for your average consumer it has been added so AMD could go after new markets.

AMD originally planned the Hammer series to target servers and workstations with the old Athlon core remaining along side it for some time in the consumer sector. Unfortunately the old Athlon core has basically hit the end of its usefulness and can't go any further. Now what would have been the Clawhammers will take over there forcing the chip to have much greater adoption in the mainstream.

Intel is simply doing the same thing but actually has a 2nd chip with some life left in it. McKinley and its more evolved counterparts aren't going to be aimed at the consumer space in the near future, the PIV is there for that. Later there will be a move to switch people over but you have a while before it happens.

Now if Apple wants to go after the 64-bit marketspace then that's fine they will need a 64-bit chip to do so. They may or may not decide to go there that's a matter for management.

If all they will continue to do is aim at the consumer space 64-bit computing isn't necessary or useful yet. If Apple doesn't release a 64-bit chip until 2003 or 2004 it will not be doomed and in fact it won't really matter in the least to their current markets except from a marketing point of view.

All that said when they do release their next generation chip there is no reason it shouldn't be designed with a 64-bit future in mind even if they only do it for marketing reasons.

[quote]Marketing is everything (look at the consoles).<hr></blockquote>
Consoles are largely about the game developers that are onside for a certain console. In Japan a lot of people have bought PS2 consoles simply due to Square's development for the platform.

When the Xbox came out they released it with a series of big Xbox only titles to try and lure people to buy the console for just certain titles. Nintendo did the same thing with the Gamecube.

It's no big secret if you want to play games any current generation console can do the job but if you want to play certain games often only one console has rights to them. That's what drives the console market more than anything. Certainly what motivated my buying.

Edit: Added console stuff.

[ 06-17-2002: Message edited by: Telomar ]

[ 06-18-2002: Message edited by: Telomar ]</p>
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post #155 of 620
[quote]Originally posted by RolandG:
<strong>Will the G5 (64-bit version) be similar in construction to the AMD hammers in that it will basically still be a 32-bit processor with an added 64-bit unit?</strong><hr></blockquote>

I think it will indeed be made in a fab on a Silicon wafer
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post #156 of 620
[quote]Originally posted by THT:
<strong>The Ocean fabric connects I/O, not processor execution units. It can maybe connect multiple e500 cores together, but I really doubt that.</strong><hr></blockquote>

I haven't seen anything particularly detailed about OCEAN -- do you have any reference materials? If it was sufficiently fast it should be possible to pass instructions to and from on-chip units for dispatch & retirement. This is what Dorsal was implying, but unless we have some real documentation on OCEAN its hard to verify / deny. I said earlier that this thread might be the make/break thread for Dorsal, but perhaps it will be this particular post that proves he does or doesn't know what the hell he's talking about.
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post #157 of 620
[quote]Originally posted by Dorsal M:
<strong>
The PowerMac G4 as we know it will be retired. Well the architecture will at least. We will see changes to the system bus, processor and general layout. Motorola has been hard at work with the 130nm G4. It will scale nicely (at least 1.5GHz by the summer) and have improved bus features. Memory access will be stellar. And you'll see why. not only will DDR SDRAM make a debut but it will not connect to the processor iin a conventional manner. More to come. Cache will also be increased on the processor level. Twice what is seen now. You will see a collaboration with another hardware company, but this will not surprise some of you in the know.

More to come.</strong><hr></blockquote>

This jibes with what I've heard as well, but as I understand it, this motherboard has been unfortunately delayed, and a stop-gap DDR motherboard is what we'll see first. We shall see...
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post #158 of 620
we've had delays and stopgaps for what, 10 years now?

great, wtf am I doing here.

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post #159 of 620
[quote]Originally posted by moki:
<strong>This jibes with what I've heard as well, but as I understand it, this motherboard has been unfortunately delayed, and a stop-gap DDR motherboard is what we'll see first. We shall see...</strong><hr></blockquote>

But what is the difference between the "real" mobo and the "stop-gap" one? Is it the processor &lt;-&gt; memory connection or the chipset DSPs you were talking about?
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post #160 of 620
I hear that Apple will put out an RDF on the AGP so the PCI is 8x faster than the DDR on the UMA, but only if the 3GIO is ready from the OEM at a good MSRP. Then again I heard this on the D/L from someone at MOSR so I guess I'm SOL.

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