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Will Apple's G5 come from IBM? - Page 5

post #161 of 1258
This article is written as if the chip is ready to go!
post #162 of 1258
[quote]Originally posted by Appleworm:
<strong>I've just take a couple of minutes on motorola website about PowerPC ISA.

Looking at the roadmap you can see G5 is 85xx rapidIO, extensible architecture...

There are 2 85xx processors :
8540 (one year old)
8560 (PowerQUICC III not for us)

First intersting point the MIPS are the same with the 7455 : 2315@1GHz (8540) vs 2310@1GHz (7455)

The 8540 is based on Book E, has RapidIO DDR memory controller @ 333MHz, it's .13 CMOS no SOI, SIMD,... All the technologies are ther


Will new mac with the 8540 (or a derivative of it) and new MB be faster than the 7455 G4 PM ?

So, does this 8540 processor sound like the "G5" we will in the next weeks ?


<a href="http://e-www.motorola.com/webapp/sps/site/overview.jsp?nodeId=03M943030450467M983989030230" target="_blank">roadmap</a>
<a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8560&nodeId=03M9430304504 67M98657" target="_blank">8560 PwQUICC III</a>
<a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=03M9430304504 67M98657" target="_blank">8540</a>

Aw </strong><hr></blockquote>
There will not be any 8450 chips in a mac, as you stated a DDR memory controlled 7455 will be faster at equal mhz than a 8450. The G5 is strictly an embedded chips, not suited for desktop computers. The G4 was already an embedded chips, but at his time worthing to be included in a powermac.

The future of Mac is the new chip from IBM, precisions will be revealed in october during the microprocessor forum.
post #163 of 1258
FYI

<a href="http://www.heise.de/newsticker/data/as-09.08.02-000/" target="_blank">http://www.heise.de/newsticker/data/as-09.08.02-000/</a>

This article claims the SIMD Unit is _NOT_ altivec compatible!

End of Line
post #164 of 1258
From the news.com article:
[quote]Big Blue plans to design the new desktop PowerPC chip using technology from its Power4 processor for servers.<hr></blockquote>
[quote]The chip's heritage--the Power4 design--suggests that it will be a high-performance processor. Though it's unclear what clock speed the new PowerPC will offer, IBM has been gunning for 2GHz. The company said last year that it intended to hit that speed target by the end of 2002.<hr></blockquote>

Does not sound like it's ready to go.

OR

1.4 - 1.5 are ready now and 2.0 for Q1

Screed ...Thank God I'm broke!

[ 08-09-2002: Message edited by: sCreeD ]</p>
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post #165 of 1258
Perhaps but...

[quote] The new chip, which Big Blue will unveil at this fall's Microprocessor Forum, is designed to deliver higher clock speeds and 64-bit processing to desktop computers and also to entry-level servers. <hr></blockquote>

[quote] "It's a really hefty processor in terms of performance," said Kevin Krewell <hr></blockquote>

Gives the impression it is pretty much done from the way it is written (but I agree that 2.0 GHz is not likely to happen).
post #166 of 1258
Remember that this CPU has i) a process shrink, ii) a different design from G4 (inc. a deeper pipeline ), so 2GHz may be possible.

[ 08-09-2002: Message edited by: Stoo ]</p>
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post #167 of 1258
That would be nice.

'2GHz IBM Power4l-PC'



[ 08-09-2002: Message edited by: DaveLee ]</p>
post #168 of 1258
[quote]Originally posted by DaveLee:
<strong>Perhaps but...

Gives the impression it is pretty much done from the way it is written (but I agree that 2.0 GHz is not likely to happen).</strong><hr></blockquote>

Well they are probably taped out, or at least getting close if they are going to ship in quantity next year.
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post #169 of 1258
posted from Tron

<a href="http://www.heise.de/newsticker/data/as-09.08.02-000/" target="_blank">http://www.heise.de/newsticker/data/as-09.08.02-000/</a>

This article claims the SIMD Unit is _NOT_ altivec compatible!

but if you read it, stay that the only one that have something to say is Apple.

from the articule:

AltiVec-Befehle können die neuen Prozessoren aber per Software in althergebrachter Weise emulieren

translation:

AltiVec-Commands can emulate the new processors however by software in traditional way

and:

Doch von IBM-Desktops mit PowerPC ist derzeit weit und breit nichts zu sehen. Hier kommt wohl dem Dritten im Bunde des ehemaligen PowerPC-Triumvirats, Apple, eine wesentliche Rolle zu

In English:

But of IBM Desktops with power PC at present far and broadly nothing is to be seen. Here a substantial role probably comes third in the federation of the former PowerPC Triumvirats, Apple

ciao
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post #170 of 1258
[quote]Originally posted by InstanGlueck:
<strong>

But of IBM Desktops with power PC at present far and broadly nothing is to be seen. Here a substantial role probably comes third in the federation of the former PowerPC Triumvirats, Apple

ciao</strong><hr></blockquote>

Well I'm glad we've cleared that up!
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post #171 of 1258
When Apple wanted to move to a new chip from the G3 they went to BOTH IBM and Mot. IBM demoed a G3 at around 600MHz I believe and gave Apple the roadmap for the G3 which may or may not have included MP support and L3 cache support. Mot demoed what we know is the G4, basically a G3 with a slightly better bus system and most importantly...AltiVec. BUT at the time Mot only had it running at a top speed of 400MHz. IBM's arguement was that their ability to hit higher clock speeds would compensate for the lack of AltiVec. Apple went with AltiVec and then we had the 500MHz debacle.

Now I am sure that IBM looks at the eMac/iMac/Powerbook/Power Mac/Xserve and soon to be iBook and sees a lot of chip business it couldf steal from Mot.

[ 08-09-2002: Message edited by: Bodhi ]</p>
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post #172 of 1258
[quote] This article claims the SIMD Unit is _NOT_ altivec compatible! <hr></blockquote>

Weellllll... Here's the relevant bit from the article, translated courtesy Google:

[quote] This is not AltiVec compatible (with an own 128-bittigen unit), but works directly with the 64-bittigen CPU registers, probably compatibly to the extension for Embedded (Book E), agreed upon with Motorola. <hr></blockquote>

It seems that they believe IBM's SIMD won't be compatable with Altivec because it uses existing registers, which isn't the case. It's possible IBM 's SIMD instructions are equivelent to Altivec instructions, just using the existing scalar registers instead of a dedicated register set.

Let's think about this. We know IBM had a hand in developing VMX (?), which is either Altivec, or Altivec is based on (Programmer-- help please!). It stands to reason that IBM would use VMX, which they helped create, as their own SIMD implementation.

Besides, there are many benefits to IBM implementing an Altivec-compatible SIMD instuction set. Programmers don't have to learn a new instruction set with its own optimization requirements. Programs written with Altivec code will run on their new processor, hopefully with little or no modification. Basically, IBM gets access to code, compilers, and programmers who are already familiar with using the instruction set if they go with SIMD instructions that are Altivec compatible.
post #173 of 1258
I am not a technical geek, but i do not see how a normal integer or FP unit can make SIMD operation : one operation on multiple data : 4 * 32 8 * 16 or 16 * 8.
The integer unit or the FP unit of both power4 core or book e core are not able to make Single Instruction Multiple Data, they make Single Insturction Unique Data.

I think that The WMX will be a different design than the Altivec unit of mot, just like the mmx or SSE unit of AMD is different from the one of INTEL, but both are compatible.
post #174 of 1258
If this chip is supposed to be announced at the microprocessor forum in october would they release the chip in powermacs, before its officially announced? I doubt it.

Proably going to get at least 1 more round of g4's before we get this
post #175 of 1258
[quote]Originally posted by Powerdoc:
<strong>I am not a technical geek, but i do not see how a normal integer or FP unit can make SIMD operation : one operation on multiple data : 4 * 32 8 * 16 or 16 * 8.
The integer unit or the FP unit of both power4 core or book e core are not able to make Single Instruction Multiple Data, they make Single Insturction Unique Data.

I think that The WMX will be a different design than the Altivec unit of mot, just like the mmx or SSE unit of AMD is different from the one of INTEL, but both are compatible.</strong><hr></blockquote>

Think two FPU's
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post #176 of 1258
And this in from

<a href="http://www.silicon.com/public/door?6004REQEVENT=&REQINT1=55033&REQSTR1=silicon.c om" target="_blank">silicon.com</a>

This thread is making me all warm and fuzzy...
post #177 of 1258
Sill question but..

Will this new CPU be dual-core or only single-core? :confused:

As I understand this, a cpu contains 2 cores, and 4 & 4 CPUs are placed into 1 package?
post #178 of 1258
"This is not AltiVec compatible (with an own 128-bittigen unit), but works directly with the 64-bittigen CPU registers, probably compatibly to the extension for Embedded (Book E), agreed upon with Motorola."

Ok,how do they know this is not "altivec" when nothing has been published about this chip...not even its name?
post #179 of 1258
[quote]Originally posted by cthulu:
<strong>
Ok,how do they know this is not "altivec" when nothing has been published about this chip...not even its name?</strong><hr></blockquote>

Because, suddenly they all got sources.. <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
post #180 of 1258
post #181 of 1258
[quote]Originally posted by InstanGlueck:
<strong>posted from Tron

<a href="http://www.heise.de/newsticker/data/as-09.08.02-000/" target="_blank">http://www.heise.de/newsticker/data/as-09.08.02-000/</a>

This article claims the SIMD Unit is _NOT_ altivec compatible!

but if you read it, stay that the only one that have something to say is Apple.

from the articule:

AltiVec-Befehle können die neuen Prozessoren aber per Software in althergebrachter Weise emulieren

translation:

AltiVec-Commands can emulate the new processors however by software in traditional way
</strong><hr></blockquote>

Emulation for AltiVec sounds like a bad idea!

[quote]<strong>

and:

Doch von IBM-Desktops mit PowerPC ist derzeit weit und breit nichts zu sehen. Hier kommt wohl dem Dritten im Bunde des ehemaligen PowerPC-Triumvirats, Apple, eine wesentliche Rolle zu

In English:

But of IBM Desktops with power PC at present far and broadly nothing is to be seen. Here a substantial role probably comes third in the federation of the former PowerPC Triumvirats, Apple

ciao</strong><hr></blockquote>

Danke fuer die Uebersetzung aber ich denke mein Deutsch reicht aus, um zu erkennen dass es sich hier nur um Spekulation seitens Heise handelt.

In English:

Thx for the translation but I think my German is sufficient enough, to realize that this is only speculation from heise.



End of Line

PS: Gruesse aus Wien!
post #182 of 1258
[quote]Originally posted by heinzel:
<strong>... posted this in another thread already:
From the <a href="http://www.mdronline.com/mpf/conf.html#day1_2" target="_blank">Microprocessor Forum homepage</a>:
Breaking Through Compute Intensive Barriers - IBM's New 64-bit PowerPC Microprocessor
Peter Sandon, Senior Processor Architect, Power PC Organization, IBM Microelectronics
IBM is disclosing the technical details of a new 64-bit PowerPC microprocessor designed for desktops and entry-level servers. Based on the award winning Power4 design, this processor is an 8-way superscalar design that fully supports Symmetric MultiProcessing. The processor is further enhanced by a vector processing unit implementing over 160 specialized vector instructions and implements a system interface capable of up to 6.4GB/s.

Emphasis added. Altivec comprises 162 instructions - will IBM finally implement it? Are there any other desktop OSs on PowerPC apart from MacOSX? AIX maybe?

Interestingly, there are no anouncements by Motorola on the MPF homepage... . Maybe the G4 will be Moto's last desktop-capable processor for real?</strong><hr></blockquote>

I predict that this new processor will be a birthday present for Mac OS X. While IBM's new plant is up now it won't be fully ramped up until early next year. Even if this chips exists today it would be too expensive for Apple to use in desktops before late March. We might see it in the Xserve a litle sooner. Until then all I expect is speedbumped G4s.

Maddan
post #183 of 1258
[quote]Originally posted by User Tron:

<strong>Emulation for AltiVec sounds like a bad idea!</strong><hr></blockquote>

It depends on how IBM decided to do it. Velocity Engine programmers use a macro language to program the unit instead of banging on bare metal, so there's currently "emulation" in the sense that the instruction codes are translated into the AltiVec ISA. Right now, as I understand it, that translation is trivial. 1 macro becomes 1 instruction.

As long as the translation of the Velocity Engine macro language to the IBM ISA isn't especially difficult or cumbersome (e.g., the vector permute function doesn't map to a long series of bit-twiddling ops in the integer units!) it should work fine.
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post #184 of 1258
[quote]I would not read ANYTHING into the Oct 15 date for the presentation other than that is when those PowerPoint slides will be complete.<hr></blockquote>

-except for the .pdf with that pic. that was going around noting one MASSIVE heat sink in next weeks supposed new towers. <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />


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post #185 of 1258
Actually, there are several interesting passages in the article from <a href="http://www.heise.de," target="_blank">www.heise.de,</a> and being a Dane I have translated them here:

"... and it furthermore includes a SIMD-extension offering 160 commands. This is not AltiVec compatible (that is, with its own 128-bit unit [bus?]); instead it addresses the 64-bit CPU registers directly, apparently making it compatible with the extension for Embedded [processors] (Book E) which was planned in cooperation with Motorola. Motorola just recently presented the communication processors MPC8560 and MPC8540, and they also include such a new SIMD extension ....."

"Thus, IBM's stubborn refusal to include an AltiVec unit makes sense, if better-performing SIMD possibilities in a 64-bit unit were in the works, and they didn't want to introduce temporary, non-compatible solutions. However, in the new processors the AltiVec-commands can be emulated in software in the traditional manner."

The words in square brackets [] are my additions, attempting to clarify the text further...

Does anyone know more about the "new SIMD extension" in the two Motorola communications processors? Any comments when comparing it to AltiVec?

engpjp

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post #186 of 1258
[quote]Originally posted by engpjp:
<strong>Actually, there are several interesting passages in the article from <a href="http://www.heise.de," target="_blank">www.heise.de,</a> and being a Dane I have translated them here:
</strong><hr></blockquote>

this is why i love europe... a dane living in turkey translates a german article about two american companies to english for the rest of the world to understand.
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post #187 of 1258
Is it that IBM didn't want to include Altivec or the fact that the Altivec Apple and Mot wanted to use wasn't 64-bit clean. That would make sense as to why IBM told them other guys to sod off.

There,s discussion at Ars by BadAndy relevent to 64-bit altivec in the IBM thread.
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post #188 of 1258
[quote]Originally posted by AirSluf:
<strong>There is a big difference between announcing a produce from a marketing standpoint, and presenting technology at Conferences. Formal announcements usually are made outside of Conferences unless the conference also happens to be a major marketing tradeshow that coincides with your desired release date anyway.

I would not read ANYTHING into the Oct 15 date for the presentation other than that is when those PowerPoint slides will be complete.
</strong><hr></blockquote>Just to give more context to this, the 750fx Sahara was first introduced at the microprocessor forum last October, and then found its way into iBooks in May of the next year, about 7 months later. And I'm sure other time frames have varied wildly. I.e., who can tell how far away this thing is?
post #189 of 1258
[quote]Originally posted by engpjp:
<strong>"... and it furthermore includes a SIMD-extension offering 160 commands. This is not AltiVec compatible (that is, with its own 128-bit unit [bus?]); instead it addresses the 64-bit CPU registers directly, apparently making it compatible with the extension for Embedded [processors] (Book E) which was planned in cooperation with Motorola...."
</strong><hr></blockquote>

Book E does not specify any SIMD-unit... I've searched through the Book E paper.

And Im pretty sure the SIMD used in Motorola embedded PPC is not a 160+ instruction extension. Maybe I could try to find more info about that.
post #190 of 1258
hmmm, I've tried to count the number of vector instructions the e500 supports..

<a href="http://e-www.motorola.com/brdata/PDFDB/docs/EREF_CH3.pdf" target="_blank">http://e-www.motorola.com/brdata/PDFDB/docs/EREF_CH3.pdf</a>

Actually.. its ~186 vector instructions (+- 2).. <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" /> <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" />

Some of the instructions are pretty strange.. Like the one at page 148.

[ 08-09-2002: Message edited by: blabla ]</p>
post #191 of 1258
The Motorola SIMD design for their "G5" embedded processors, which are Book "E", use the integer registers to hold the data for the SIMD operations. These registers are half (or a quarter) the size of the AltiVec registers, dramatically reducing the usefulness of this kind of implementation... not to mention they are the same 32 registers instead of the additional 32 registers that AltiVec uses. This style of SIMD implementation is what IBM used in the Gekko for Nintendo -- each 64-bit FPU register held 2 single precision floats -- but that design was a gross hack instead of the impressive general purpose vector engine that is the AltiVec unit.

Its possible IBM has chosen to go this route, but I really hope not... and I don't believe so. First of all there are several explicit references to VMX, and that is AltiVec. Second, this new desktop processor is not embedded and thus probably not Book "E" compliant. Third, emulating the AltiVec unit on top of something using the integer registers simply isn't possible to do efficiently since it would clobber the data used by the integer unit.

I think that site is just blowing smoke, and until there is real evidence to the contrary I'm going to continue to believe that IBM has implemented a VMX unit. It is possible that this might internally involve cracking the VMX instructions and feeding them to multiple execution units, but as long as that is at least as fast it doesn't really matter.


I've also seen comments that the description of the new processor is 8-way superscalar meaning it has 8 execution units... there is another (more common) meaning for "N-way" superscalar, and that is the number of instructions dispatched per clock cycle. The G4 has more than 4 execution units, but is classified as 4-way. Moto's G5 has more than 2 units, but is classified as 2-way. I think this is more likely, and therefore the new IBM processor will dispatch up to 8 instructions per clock to some number of execution units... probably a rather large number of units (i.e. &gt; 8).

All just speculation, of course, but it is more in line with the expected number of transistors than much of the other speculation out there.
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post #192 of 1258
<strong>Originally posted by Programmer:
I've also seen comments that the description of the new processor is 8-way superscalar meaning it has 8 execution units... there is another (more common) meaning for "N-way" superscalar, and that is the number of instructions dispatched per clock cycle.</strong>

The meaning of superscalar has always been the number of instructions dispatched per clock cycle. This other way is more symptomatic of market-droid naming conventions or common misconceptions then anything else.

8-way superscalar though, shazam! That better be one efficient compiler!
post #193 of 1258
Its been a long time since there's been so much exitement on these boards. My personal take, reading the the runes is that ;
a) There will be a a proper Altivec/VMX VPU on board (Bad Andy suggests that a 64bit split/emulation/fudge would not hack it)
b) The '64bit' chip being presented in October is NOT the chip that Apple will use; there will be 32 bit variant embargoed until Apple announce (six-seven months?) and OSX will migrate to 64 bit in due course.

This all leaves Apple with a bit of a medium term PR headache and I suspect the 'iPower5' (whatever) will be going into a higher tier box ($5-6K, 2U rackmount?) for the 3D render, recording studio, film editing, too much money crowd (like me, yummm). The G4 will continue for at least another 18 months.
post #194 of 1258
[quote]Originally posted by vinney57:
<strong>Its been a long time since there's been so much exitement on these boards. My personal take, reading the the runes is that ;
a) There will be a a proper Altivec/VMX VPU on board (Bad Andy suggests that a 64bit split/emulation/fudge would not hack it)
b) The '64bit' chip being presented in October is NOT the chip that Apple will use; there will be 32 bit variant embargoed until Apple announce (six-seven months?) and OSX will migrate to 64 bit in due course.

This all leaves Apple with a bit of a medium term PR headache and I suspect the 'iPower5' (whatever) will be going into a higher tier box ($5-6K, 2U rackmount?) for the 3D render, recording studio, film editing, too much money crowd (like me, yummm). The G4 will continue for at least another 18 months.</strong><hr></blockquote>

I don't think they'd waste their effort building a 32-bit version of it. More likely Apple wouldn't tell anyone it was a 64-bit CPU until 10.3 ships and suddenly flips the "64-bit mode" bit for any application that wants to be 64-bit. Oh look, 64-bit code.

Or they've had MacOSX running on POWER4s and PPC620s for the last 3 years and the 64-bit support is already there (perhaps Cocoa only?).

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post #195 of 1258
[quote]Originally posted by Programmer:
<strong>

I don't think they'd waste their effort building a 32-bit version of it. More likely Apple wouldn't tell anyone it was a 64-bit CPU until 10.3 ships and suddenly flips the "64-bit mode" bit for any application that wants to be 64-bit. Oh look, 64-bit code.

Or they've had MacOSX running on POWER4s and PPC620s for the last 3 years and the 64-bit support is already there (perhaps Cocoa only?).

</strong><hr></blockquote>

64 bit + Jaguar = No booting into OS 9? Could that be the reason?

 

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post #196 of 1258
[quote]b) The '64bit' chip being presented in October is NOT the chip that Apple will use; there will be 32 bit variant embargoed until Apple announce (six-seven months?) and OSX will migrate to 64 bit in due course.<hr></blockquote>

Im pretty sure it will be backwards compatible with 32bit apps, wasnt that a design element in the original PowerPC ISA?
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post #197 of 1258
If this is the next chip to be featured in the towers then I agree that we're realistically looking at the second quarter of 2003 as the soonest that these things could be ready in quantity if they're having their debutante ball in October.

I harbor huge doubts as to anything fast coming for pros in the foreseeable future. But I'm just being a grump.

D
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post #198 of 1258
[quote]Originally posted by drewprops:
<strong>
I harbor huge doubts as to anything fast coming for pros in the foreseeable future. But I'm just being a grump.

D</strong><hr></blockquote>

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post #199 of 1258
i'm pretty sure the answer to my question is in here somewhere but its too much ot read...

Assuming apple adopts this and IBM produces it what is the earliest this will see the light of day on our desktop? february update to the powermac line? or march? or is that too early?

I would like to know because if this is the g5 then i don't wanna buy the last g4 towers to be released this month
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post #200 of 1258
[quote]Originally posted by O and A:
<strong>I would like to know because if this is the g5 then i don't wanna buy the last g4 towers to be released this month</strong><hr></blockquote>

First don't expect anyone here to KNOW for sure and say so... AI is filled with some pretty good people but what it comes down to is either people reading your request knows and can't say or they don't know but will give you a best guess and if that's the case it's just that a guess....

Second... don't get too crazy about buying a computer. If you need a faster machine then buy it.... Otherwise wait. It really is that simple. You say you don't wanna buy this next round of computers if new ones are gonna come out Jan/Feb/Mar of next year with a new CPU.... Then when those new systems do ship do you buy? After all this IS the 1st gen of a whole new system and it could very well have 'issues' ... now do you wait again for the next rev of the 'new boxes'?

You see where I'm going with this... you can wait forever doing that.

If you need a new box then buy it if not just wait till you do... Seach the boards (when you are ready) just to make sure a newer box isn't 'right around the corner' (like where we are right now) and then buy.

Trust me... No matter when you buy your system 6 to 9 months later a BETTER and CHEAPER box is sure come out. It's been that way FOREVER.

Dave
Apple Fanboy: Anyone who started liking Apple before I did!
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Apple Fanboy: Anyone who started liking Apple before I did!
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