A feature of the G5 is a builtin memory controller so we wouldn't needs a new N/Sbridge combo but a PCI/peripheral controller instead. This way you can segregate the memory bus speed (be it 266MHz or 333MHz) and the RIO bus (be it 400MHz or 500MHz) to the master controller.
<strong>As for a selling link, as far as I'm concerned that web page makes it clear which MPC8XXX chips are available right now. So that's the proof that it is available now.</strong><hr></blockquote>
How does that make it clear? I'd love to eat my words, but I still think the G5 is months away. That table does not prove a thing. Until you point me to a page where I can actually order the thing that says it is in stock and shipping, I simply can not believe it.
As for it being 600-1600 MHz, why are you believing Geek.com over Motorola's page? And I didn't say you were wrong, I said (although I was not clear enough, granted) geek.com was wrong.
Those speeds are for the G5 family, which probably means the lower clock speeds are referring to the embedded G5, or the MPC8540. In no way did I or geek.com for that matter say the 8540 would go up to 1600 MHz in the first quarter.
I shall continue searching for conclusive evidence, but as far as I know the second half release is wrong. Also, don't the embedded versions of processors usually appear AFTER the regular desktop ones? I may be wrong but can someone answer this.
<strong>A feature of the G5 is a builtin memory controller so we wouldn't needs a new N/Sbridge combo but a PCI/peripheral controller instead. This way you can segregate the memory bus speed (be it 266MHz or 333MHz) and the RIO bus (be it 400MHz or 500MHz) to the master controller.</strong><hr></blockquote>
Moto PPC developer in an interview told that only adding a greater ammount of L3 cashe will not bring a linear increase in performance, that´s also one of the reasons, why they decided to incorporate a main memory controller on die. G5 will not have L3 cashe.
Anyway the present U-North incorporates:
- data/adress connection to G4
- main memory controler and of course PCI bridge
To connect with G5 at least the RapidIo switch must be added to the U-North, the main memory controller is of course obsolete.
[quote] Samples of the MPC8540 are expected to be available in the second half of 2002.<hr></blockquote>
Ya know, I know for a fact that this same link has been posted many times here...
[quote]Also, don't the embedded versions of processors usually appear AFTER the regular desktop ones? I may be wrong but can someone answer this.<hr></blockquote>
There's no hard and fast rule for it. The plain fact is, an embedded part has been announced, and NOTHING ELSE. Everything else is just conjecture.
Comments
<strong>As for a selling link, as far as I'm concerned that web page makes it clear which MPC8XXX chips are available right now. So that's the proof that it is available now.</strong><hr></blockquote>
How does that make it clear? I'd love to eat my words, but I still think the G5 is months away. That table does not prove a thing. Until you point me to a page where I can actually order the thing that says it is in stock and shipping, I simply can not believe it.
As for it being 600-1600 MHz, why are you believing Geek.com over Motorola's page? And I didn't say you were wrong, I said (although I was not clear enough, granted) geek.com was wrong.
So, by saying I'm wrong, you're wrong.
I shall continue searching for conclusive evidence, but as far as I know the second half release is wrong. Also, don't the embedded versions of processors usually appear AFTER the regular desktop ones? I may be wrong but can someone answer this.
<strong>A feature of the G5 is a builtin memory controller so we wouldn't needs a new N/Sbridge combo but a PCI/peripheral controller instead. This way you can segregate the memory bus speed (be it 266MHz or 333MHz) and the RIO bus (be it 400MHz or 500MHz) to the master controller.</strong><hr></blockquote>
Moto PPC developer in an interview told that only adding a greater ammount of L3 cashe will not bring a linear increase in performance, that´s also one of the reasons, why they decided to incorporate a main memory controller on die. G5 will not have L3 cashe.
Anyway the present U-North incorporates:
- data/adress connection to G4
- main memory controler and of course PCI bridge
To connect with G5 at least the RapidIo switch must be added to the U-North, the main memory controller is of course obsolete.
rooster
<a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655" target="_blank">http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655</a>
I'm going to find proof that it's shipping now.
<strong>Sometimes we need to finish following the yellow brick road all the way to the end. try this link and scroll to the bottom.
<a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655" target="_blank">http://e-www.motorola.com/webapp/sps/site/prod_ summary.jsp?code=MPC8540&nodeId=01M98655</a>
I'm going to find proof that it's shipping now.</strong><hr></blockquote>
Hmmm...?
<img src="confused.gif" border="0">
<a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655" target="_blank">http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655</a>
It's in Moto's official press release for the 8540:
<a href="http://www.motorola.com/mediacenter/news/detail/0,1958,568_322_23,00.html" target="_blank">http://www.motorola.com/mediacenter/news/detail/0,1958,568_32 2_23,00.html</a>
Here's the relevant quote:
[quote] Samples of the MPC8540 are expected to be available in the second half of 2002.<hr></blockquote>
Ya know, I know for a fact that this same link has been posted many times here...
[quote]Also, don't the embedded versions of processors usually appear AFTER the regular desktop ones? I may be wrong but can someone answer this.<hr></blockquote>
There's no hard and fast rule for it. The plain fact is, an embedded part has been announced, and NOTHING ELSE. Everything else is just conjecture.
Jet