Well, I think they got the details wrong. Do we know if the 970 has HT buses (even a variant?).
Have you noticed that the Apple PI-BUS is 6.4 Gb/s just like HyperTransport? That's no coincidence. That is because the Apple PI-BUS is an implementation of HyperTransport.
So you will most certainly see PPC970 ship on a HyperTransport motherboard.
Have you noticed that the Apple PI-BUS is 6.4 Gb/s just like HyperTransport? That's no coincidence. That is because the Apple PI-BUS is an implementation of HyperTransport.
So what is different about it? Or is Apple PI just a marketing name? Why wouldn't IBM release that info. Surely it is a significant advantage for the processor? "Look we support HT, we've done lots of work to make it easy for you to hook these babies up!".
Its not that I don't believe you becuase I consider it likely to be true, but there is no solid data saying there is a connection between processors.
Quote:
So you will most certainly see PPC970 ship on a HyperTransport motherboard.
Which is not in doubt, and not the same thing as saying the connection between processors is HT. The motherboard to me will be an HT motherboard if HT is used to connect any system components together (like ethernet controller etc).
Two days after purchasing Lotus Development Corporation, IBM announced it would strengthen its efforts in the Internet arena. The company said it would release software products for Web design and administration, as well as enhanced security software. Microsoft would follow suit within the next several months, also increasing its efforts in Web technologies.
IBM's change in emphasis was an extension of chairman Lou Gerstner's turnaround strategy, announced in March 1994, which shifted the company's focus to networking and client-server computing. The company had since undergone a remarkable turnaround, from a struggling company with consistent losses, to a cash surplus of $10.5 billion.
No way. Having the memory controller chip with both processor busses connected to it is the most efficient method (in this instance).
Except that's not how the PowerPC 970 works. The 970's unidirectional bus and SMP functions require a companion chip.
May it be noted that I have said before that Apple could put multiple companion chips and 970s on a daughtercard. One connection to a master companion chip, or maybe some kind of switch, and then connections to other chips.
Whether this would be integrated into a single slice of silicon, I don't know.
Except that's not how the PowerPC 970 works. The 970's unidirectional bus and SMP functions require a companion chip.
May it be noted that I have said before that Apple could put multiple companion chips and 970s on a daughtercard. One connection to a master companion chip, or maybe some kind of switch, and then connections to other chips.
Whether this would be integrated into a single slice of silicon, I don't know.
Barto
We're saying about the same thing but using different terminology. Substitute companion chip for memory controller and our statements essentially gel.
There is no stipulation for a companion chip to only have one 970 processor connected, only that a 970 processor have a companion chip. So two processors sharing a companion chip (or memory controller) is a definate design possability. So I think the design still stands.
Just out of interest can I ask why you thnk uni-directional matters?
So what is different about it? Or is Apple PI just a marketing name? Why wouldn't IBM release that info. Surely it is a significant advantage for the processor?
There is...i can't be arsed looking around for it. Do a search on the web if you have the time...or just wait 10 days.
The Apple PI bus IS HyperTransport interconnect that can be and will be used to multiprocessing and I/O on the same interconnect. Apple will produce a typical HyperTransport switch as a companion chip to do the needful. It may even use the same bus for memory.
Unlike the Athlon-64 which has two HT interconnects or the Opteron which has 3 HT interconnectd as well as integrated Memory controller/bus, i think the PPC970 just has the one Apple PI interconnect for everything.
It appears that the PPC 980 will have more HT interconnect. Two most likely with maybe a direct bus for memory. Though not sure of these details, these are likely possiblities.
There is...i can't be arsed looking around for it. Do a search on the web if you have the time...or just wait 10 days.
The Apple PI bus IS HyperTransport interconnect that can be and will be used to multiprocessing and I/O on the same interconnect. Apple will produce a typical HyperTransport switch as a companion chip to do the needful. It may even use the same bus for memory.
Unlike the Athlon-64 which has two HT interconnects or the Opteron which has 3 HT interconnectd as well as integrated Memory controller/bus, i think the PPC970 just has the one Apple PI interconnect for everything.
It appears that the PPC 980 will have more HT interconnect. Two most likely with maybe a direct bus for memory. Though not sure of these details, these are likely possiblities.
I'd love to see more info on this -- just basing it on the throughput being 6.4 GB/sec is not sufficient because that can be just coincidence. The new Intel and 970 FSBs are also 6.4 GB/sec, and that doesn't mean they are all HyperTransport either. If the 970's FSB is actually HyperTransport why didn't they just come out and say it, and I think there is something about it that they did say which means that it isn't HT (can't remember offhand what that was...).
And remember that Hyper Transport can still be used on the motherboard even though it is not used to connect the processor top the companion chip. HT will probably be used as the connection between the companion chip and any number of peripheral chips and other companion chips that in turn are connected to other 970s.
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days
g
These kid's today... Whatya gonna do? Back in my day we'd have already seen tons of fakes hoaxes and more 'a friend of a friend' yarns than you could shake a stick at...
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days
And remember that Hyper Transport can still be used on the motherboard even though it is not used to connect the processor top the companion chip. HT will probably be used as the connection between the companion chip and any number of peripheral chips and other companion chips that in turn are connected to other 970s.
A thought (or two)
If HyperTransport is being used to connect processors together, and given that the PPC970 doesn't use a HT bus, we have a companion chip of some kind connected to each processor in a multi-processor configuration.
This arrangement fits in very neatly with a NUMA architecture (each companion chip having it's own memory controller), giving scaleable memory bandwidth with increasing number of processors, makes machines with more than two processors simpler to design. It also means that, if the next generation chip comes with an onboard memory controller, the general design of the system remains the same, just change the two-chip 970+companion unit to a single (PPC980?) processor chip.
However, a NUMA architecture (also combined with a shift to 64 bits) will require a completely rewritten memory manager, especially if you want to get decent performance by making sure of memory locality when allocating. It would almost certainly not be worth the effort of retrofitting such a new memory manager to 10.2 for use over a very short period. So dual processor machines only appear when 10.3 appears (this will also, happily, be when the processor production has ramped up further and more processors are available.
If the 970's FSB is actually HyperTransport why didn't they just come out and say it, and I think there is something about it that they did say which means that it isn't HT (can't remember offhand what that was...).
If HyperTransport is being used to connect processors together, and given that the PPC970 doesn't use a HT bus, we have a companion chip of some kind connected to each processor in a multi-processor configuration.
I'm sure i found a better source than this before which says that the ApplePI-BIU is in fact a supercharged HyperTransport link.
The reason it seems it may not have been just called HyperTransport is because it predates HyperTransport (or Apple's involvement in the consortium) and secondly because HyperTransport is quite a broad specification encompassing a variety of technology (which Apple PI-BIU complies with).
Thats it, I'm convinced they will be showing and announcing the 970. I'm guessing shipping within a month or less. Why else would they broadcast WWDC? They can't show Panther without the new hardware, right? If they talk about the 970 and then don't announce a ship date, well the sales of systems will go negative as people begin throwing their Apple computers at Apple stores nation wide.
Comments
Originally posted by JRG
Well, I think they got the details wrong. Do we know if the 970 has HT buses (even a variant?).
Have you noticed that the Apple PI-BUS is 6.4 Gb/s just like HyperTransport? That's no coincidence. That is because the Apple PI-BUS is an implementation of HyperTransport.
So you will most certainly see PPC970 ship on a HyperTransport motherboard.
Originally posted by rmendis
Have you noticed that the Apple PI-BUS is 6.4 Gb/s just like HyperTransport? That's no coincidence. That is because the Apple PI-BUS is an implementation of HyperTransport.
So what is different about it? Or is Apple PI just a marketing name? Why wouldn't IBM release that info. Surely it is a significant advantage for the processor? "Look we support HT, we've done lots of work to make it easy for you to hook these babies up!".
Its not that I don't believe you becuase I consider it likely to be true, but there is no solid data saying there is a connection between processors.
So you will most certainly see PPC970 ship on a HyperTransport motherboard.
Which is not in doubt, and not the same thing as saying the connection between processors is HT. The motherboard to me will be an HT motherboard if HT is used to connect any system components together (like ethernet controller etc).
1995 IBM announces Internet plans
Two days after purchasing Lotus Development Corporation, IBM announced it would strengthen its efforts in the Internet arena. The company said it would release software products for Web design and administration, as well as enhanced security software. Microsoft would follow suit within the next several months, also increasing its efforts in Web technologies.
IBM's change in emphasis was an extension of chairman Lou Gerstner's turnaround strategy, announced in March 1994, which shifted the company's focus to networking and client-server computing. The company had since undergone a remarkable turnaround, from a struggling company with consistent losses, to a cash surplus of $10.5 billion.
Originally posted by JRG
No way. Having the memory controller chip with both processor busses connected to it is the most efficient method (in this instance).
Except that's not how the PowerPC 970 works. The 970's unidirectional bus and SMP functions require a companion chip.
May it be noted that I have said before that Apple could put multiple companion chips and 970s on a daughtercard. One connection to a master companion chip, or maybe some kind of switch, and then connections to other chips.
Whether this would be integrated into a single slice of silicon, I don't know.
Barto
Originally posted by Barto
Except that's not how the PowerPC 970 works. The 970's unidirectional bus and SMP functions require a companion chip.
May it be noted that I have said before that Apple could put multiple companion chips and 970s on a daughtercard. One connection to a master companion chip, or maybe some kind of switch, and then connections to other chips.
Whether this would be integrated into a single slice of silicon, I don't know.
Barto
We're saying about the same thing but using different terminology. Substitute companion chip for memory controller and our statements essentially gel.
There is no stipulation for a companion chip to only have one 970 processor connected, only that a 970 processor have a companion chip. So two processors sharing a companion chip (or memory controller) is a definate design possability. So I think the design still stands.
Just out of interest can I ask why you thnk uni-directional matters?
Originally posted by JRG
So what is different about it? Or is Apple PI just a marketing name? Why wouldn't IBM release that info. Surely it is a significant advantage for the processor?
There is...i can't be arsed looking around for it. Do a search on the web if you have the time...or just wait 10 days.
The Apple PI bus IS HyperTransport interconnect that can be and will be used to multiprocessing and I/O on the same interconnect. Apple will produce a typical HyperTransport switch as a companion chip to do the needful. It may even use the same bus for memory.
Unlike the Athlon-64 which has two HT interconnects or the Opteron which has 3 HT interconnectd as well as integrated Memory controller/bus, i think the PPC970 just has the one Apple PI interconnect for everything.
It appears that the PPC 980 will have more HT interconnect. Two most likely with maybe a direct bus for memory. Though not sure of these details, these are likely possiblities.
Originally posted by rmendis
There is...i can't be arsed looking around for it. Do a search on the web if you have the time...or just wait 10 days.
The Apple PI bus IS HyperTransport interconnect that can be and will be used to multiprocessing and I/O on the same interconnect. Apple will produce a typical HyperTransport switch as a companion chip to do the needful. It may even use the same bus for memory.
Unlike the Athlon-64 which has two HT interconnects or the Opteron which has 3 HT interconnectd as well as integrated Memory controller/bus, i think the PPC970 just has the one Apple PI interconnect for everything.
It appears that the PPC 980 will have more HT interconnect. Two most likely with maybe a direct bus for memory. Though not sure of these details, these are likely possiblities.
I'd love to see more info on this -- just basing it on the throughput being 6.4 GB/sec is not sufficient because that can be just coincidence. The new Intel and 970 FSBs are also 6.4 GB/sec, and that doesn't mean they are all HyperTransport either. If the 970's FSB is actually HyperTransport why didn't they just come out and say it, and I think there is something about it that they did say which means that it isn't HT (can't remember offhand what that was...).
g
Originally posted by thegelding
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days
g
These kid's today... Whatya gonna do?
Originally posted by thegelding
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days
g
Oh, alright then PBg5
Originally posted by Rhumgod
Oh, alright then PBg5
St. Ives protect us from that monstrosity.
Originally posted by MacUsers
there are not even mock-ups to the powermac designs from all the rumors and stories
Well, there's no shortage of pixel wranglers here...
*cracks whip*
Originally posted by 709
St. Ives protect us from that monstrosity.
Pretty bad, huh? JI would commit ritual suicide rather than put something like that in the public's lap.
Originally posted by Outsider
And remember that Hyper Transport can still be used on the motherboard even though it is not used to connect the processor top the companion chip. HT will probably be used as the connection between the companion chip and any number of peripheral chips and other companion chips that in turn are connected to other 970s.
A thought (or two)
If HyperTransport is being used to connect processors together, and given that the PPC970 doesn't use a HT bus, we have a companion chip of some kind connected to each processor in a multi-processor configuration.
This arrangement fits in very neatly with a NUMA architecture (each companion chip having it's own memory controller), giving scaleable memory bandwidth with increasing number of processors, makes machines with more than two processors simpler to design. It also means that, if the next generation chip comes with an onboard memory controller, the general design of the system remains the same, just change the two-chip 970+companion unit to a single (PPC980?) processor chip.
However, a NUMA architecture (also combined with a shift to 64 bits) will require a completely rewritten memory manager, especially if you want to get decent performance by making sure of memory locality when allocating. It would almost certainly not be worth the effort of retrofitting such a new memory manager to 10.2 for use over a very short period. So dual processor machines only appear when 10.3 appears (this will also, happily, be when the processor production has ramped up further and more processors are available.
michael
Originally posted by Programmer
If the 970's FSB is actually HyperTransport why didn't they just come out and say it, and I think there is something about it that they did say which means that it isn't HT (can't remember offhand what that was...).
The 970 bus is elastic while HT is not.
Originally posted by mmicist
If HyperTransport is being used to connect processors together, and given that the PPC970 doesn't use a HT bus, we have a companion chip of some kind connected to each processor in a multi-processor configuration.
I'm sure i found a better source than this before which says that the ApplePI-BIU is in fact a supercharged HyperTransport link.
The reason it seems it may not have been just called HyperTransport is because it predates HyperTransport (or Apple's involvement in the consortium) and secondly because HyperTransport is quite a broad specification encompassing a variety of technology (which Apple PI-BIU complies with).
http://www.architosh.com/news/2002-1...7457-rm2.phtml
praise the goddesses....