Of course it is -- the pipeline is over twice as long and it has 80 physical registers instead of 48.
Thanks for the confirmation. I did not knew for the physical registers, for the pipeline, i knew that one of the unit have a deeper pipeline (7 instead of 4 for the 7450).
However it's strange that only one unit of the VMX engine have a deeper pipeline and not the others (some have only one stage, and one is shorter than the 7450). Can we assume that the 4 stage pipeline of the mot unit was a factor of limitation in fréquencie ?
However it's strange that only one unit of the VMX engine have a deeper pipeline and not the others (some have only one stage, and one is shorter than the 7450). Can we assume that the 4 stage pipeline of the mot unit was a factor of limitation in fréquencie?
Different operations run at different speeds. For instance, an integer add is much faster than a floating point divide. You could slow the frequency down so that every operation can finish in one tick (issueing and completing an instruction must be done at a tick), but a better solution is to allow slow operations to take more than one tick. This allows you to run multiple fast operations in the same time that a slow operation would take. You run the fast operations through a short pipeline and the slow operations through a long one.
You can optimize even more though, suppose that a slow operation takes 2.4 times as long as the fastest one. One tick allows the CPU to complete the fastest operation completely. The slow operation will take 2.4 ticks, but will have to wait until the next tick (at 3) to complete. You will lose 0.6 tick in which another slow operation could have been started. You want to minimize this by chopping up the fastest operation in stages as well (and thus increasing the clock-speed). Upping the clock-speed has some nasty consequences however (power consumption, clock management), so you don't want to go too far into chopping things up. Conventional wisdom was to have a fairly short pipeline, but the P4 has changed that. It turns out that the increased frequency more than makes up for reduced performance per tick.
Conventional wisdom was to have a fairly short pipeline, but the P4 has changed that. It turns out that the increased frequency more than makes up for reduced performance per tick.
There is no such thing as conventional wisdom saying a fairly short pipeline is best for processors. If there is, I think it's wrong. I wonder if there is even a conventional wisdom for it?! I don't think there is.
Lengthening pipeline depth decreases IPC (instructions per cycle), but there are mechanisms (OOOE, good branch prediction, more execution resources, larger dispatch/completion width, better compilers, SMT and probably speculative SMT in the future) that can increase IPC to that of short pipeline processor. They cost transistors which translate to larger die size which translate to more cost. High clock rate and more transistors translate to more power consumption which translate to more cost.
In the case of Intel, they could make the Pentium 4 affordable. They are the best CPU manufacturer in the world with the best economies of scale, and they were able to get to 0.18 micron and 0.13 micron tech first, and will be the first to get to 0.09 micron. All this manufacturing prowess made the 170 sq mm 0.18 micron P4 a doable solution for Intel.
Not only that, Intel did the very same thing with the P6 microarchitecture (the PPro, P2, P3, et al). It was a 10 stage execution pipeline processor at a time when PowerPC processors were at 4 stages (603, 604, 750, 7400).
It annoys me that the 970 will use a ball grid array rather than pins. The ball grid means the CPU must be soldered to a card or module or directly to the motherboard. If they used a pin grid, CPU upgrades would be a matter of buying a processor and popping it in a ZIF socket. This would eliminate the aftermarket CPU upgrade manufacturers and their price markups.
It would be great then if you could buy the 970 from a retailer like NewEgg.com, and since other retailers would be selling the same chip, prices would fall much more rapidly. Also, if the 970 is as great as some are making it out to be, perhaps motherboards will be manufactured by companies other than Apple, to run Linux or whatnot. A CPU with pins would mean that the motherboards could use any 970, not just the ones soldered to a processor module made to work with that specific model. This would eliminate confusion and aid acceptance for the new chip. In other words, pins rather than balls might help make the 970 a commodity chip, lowering its price, making it more appealing, and making everyone happier.
Here are some desktop pictures I made from the IBM PPC 970 die photos. They make pretty cool desktop pics, let me know if anyone wants a resolution I didn't create.
I think they might look a bit better with lower contrast and maybe a blur filter, but I'll leave that to people with more photoshop skills than I have.
Daughtercards are way more upgradeable than ZIF. If the pin count or voltage requirement changes for a ZIF chip, you're f***ed. If the same happens to a daughtercard, you can still upgrade assuming the bus is still compatible.
Also, you can upgrade to dual processors easily with a daughtercard, and the heatsink is shared for better thermal dispersion than ZIF. Apple could theoretically put the PowerPC 970's companion chips on a daughtercard. Said daughtercard would then be upgradeable for years and years.
Apple could concievably "lock out" upgrading of a daughtercard, especially if they used their own companion chip on a daughtercard just to piss people off. But then, Apple could lock out upgrading with whatever solution they go for.
Also, BGA is a more reliable connection than PGA, helping IBM to achieve the flying fast bus used by the 970.
Here are some desktop pictures I made from the IBM PPC 970 die photos. They make pretty cool desktop pics, let me know if anyone wants a resolution I didn't create.
You really want your own private lecture, don't you? Fortunately for me, Arstechnica has a pretty thorough coverage of CPU theory. You might want to start with Understanding the Microprocessor
you might also do a search somewhere in here for Eskimo's series of posts about making the microprocessor. I think he re-posted them after the great black-out, either in Future Hardware, Current Hardware or General Discussion.
Comments
Originally posted by Programmer
Of course it is -- the pipeline is over twice as long and it has 80 physical registers instead of 48.
Thanks for the confirmation. I did not knew for the physical registers, for the pipeline, i knew that one of the unit have a deeper pipeline (7 instead of 4 for the 7450).
However it's strange that only one unit of the VMX engine have a deeper pipeline and not the others (some have only one stage, and one is shorter than the 7450). Can we assume that the 4 stage pipeline of the mot unit was a factor of limitation in fréquencie ?
Originally posted by Powerdoc
However it's strange that only one unit of the VMX engine have a deeper pipeline and not the others (some have only one stage, and one is shorter than the 7450). Can we assume that the 4 stage pipeline of the mot unit was a factor of limitation in fréquencie?
Different operations run at different speeds. For instance, an integer add is much faster than a floating point divide. You could slow the frequency down so that every operation can finish in one tick (issueing and completing an instruction must be done at a tick), but a better solution is to allow slow operations to take more than one tick. This allows you to run multiple fast operations in the same time that a slow operation would take. You run the fast operations through a short pipeline and the slow operations through a long one.
You can optimize even more though, suppose that a slow operation takes 2.4 times as long as the fastest one. One tick allows the CPU to complete the fastest operation completely. The slow operation will take 2.4 ticks, but will have to wait until the next tick (at 3) to complete. You will lose 0.6 tick in which another slow operation could have been started. You want to minimize this by chopping up the fastest operation in stages as well (and thus increasing the clock-speed). Upping the clock-speed has some nasty consequences however (power consumption, clock management), so you don't want to go too far into chopping things up. Conventional wisdom was to have a fairly short pipeline, but the P4 has changed that. It turns out that the increased frequency more than makes up for reduced performance per tick.
Originally posted by wfzelle
Conventional wisdom was to have a fairly short pipeline, but the P4 has changed that. It turns out that the increased frequency more than makes up for reduced performance per tick.
There is no such thing as conventional wisdom saying a fairly short pipeline is best for processors. If there is, I think it's wrong. I wonder if there is even a conventional wisdom for it?! I don't think there is.
Lengthening pipeline depth decreases IPC (instructions per cycle), but there are mechanisms (OOOE, good branch prediction, more execution resources, larger dispatch/completion width, better compilers, SMT and probably speculative SMT in the future) that can increase IPC to that of short pipeline processor. They cost transistors which translate to larger die size which translate to more cost. High clock rate and more transistors translate to more power consumption which translate to more cost.
In the case of Intel, they could make the Pentium 4 affordable. They are the best CPU manufacturer in the world with the best economies of scale, and they were able to get to 0.18 micron and 0.13 micron tech first, and will be the first to get to 0.09 micron. All this manufacturing prowess made the 170 sq mm 0.18 micron P4 a doable solution for Intel.
Not only that, Intel did the very same thing with the P6 microarchitecture (the PPro, P2, P3, et al). It was a 10 stage execution pipeline processor at a time when PowerPC processors were at 4 stages (603, 604, 750, 7400).
It would be great then if you could buy the 970 from a retailer like NewEgg.com, and since other retailers would be selling the same chip, prices would fall much more rapidly. Also, if the 970 is as great as some are making it out to be, perhaps motherboards will be manufactured by companies other than Apple, to run Linux or whatnot. A CPU with pins would mean that the motherboards could use any 970, not just the ones soldered to a processor module made to work with that specific model. This would eliminate confusion and aid acceptance for the new chip. In other words, pins rather than balls might help make the 970 a commodity chip, lowering its price, making it more appealing, and making everyone happier.
http://people.ambrosiasw.com/~andrew/970/
You rule so much I'm not even going to mention the fact that I'm still bitter there's no Avara 2.
Barto
Originally posted by Barto
You rule moki. You have teh l33t skillz.
I think they might look a bit better with lower contrast and maybe a blur filter, but I'll leave that to people with more photoshop skills than I have.
Daughtercards are way more upgradeable than ZIF. If the pin count or voltage requirement changes for a ZIF chip, you're f***ed. If the same happens to a daughtercard, you can still upgrade assuming the bus is still compatible.
Also, you can upgrade to dual processors easily with a daughtercard, and the heatsink is shared for better thermal dispersion than ZIF. Apple could theoretically put the PowerPC 970's companion chips on a daughtercard. Said daughtercard would then be upgradeable for years and years.
Apple could concievably "lock out" upgrading of a daughtercard, especially if they used their own companion chip on a daughtercard just to piss people off. But then, Apple could lock out upgrading with whatever solution they go for.
Also, BGA is a more reliable connection than PGA, helping IBM to achieve the flying fast bus used by the 970.
Barto
Originally posted by moki
Here are some desktop pictures I made from the IBM PPC 970 die photos. They make pretty cool desktop pics, let me know if anyone wants a resolution I didn't create.
http://people.ambrosiasw.com/~andrew/970/
Cool pics Moki! Can you make a 1280*960 one too?
Originally posted by NETROMac
Cool pics Moki! Can you make a 1280*960 one too?
okay, it's up there now (same URL)
Originally posted by moki
okay, it's up there now (same URL)
Thanks moki, you're the best
Originally posted by moki
okay, it's up there now (same URL)
Any chance of 1280x854? If not I'll just scale the 1440x900.
http://homepage.mac.com/vgink/970desktop2_1024x768.jpg
CV
Try putting skin over the frame of an early 20th century aircraft.
You dope the fabric with a liquid.
Edit: That liquid is refered to as "dope"
I wish dope was a liquid...
Originally posted by wfzelle
You really want your own private lecture, don't you? Fortunately for me, Arstechnica has a pretty thorough coverage of CPU theory. You might want to start with Understanding the Microprocessor
you might also do a search somewhere in here for Eskimo's series of posts about making the microprocessor. I think he re-posted them after the great black-out, either in Future Hardware, Current Hardware or General Discussion.
I read them before the first black out.