However, in the x86 camp, the advance in clockspeed has been faster than 2x in 18 month for some time now.
I'll just refer you to Eugene's posts on clockspeed changes for the past 18 months in the x86 world. Suffice to say AMD has advanced around 35% and Intel has advanced only around 40%. In fact Intel has maintained only around 55% improvement over the whole life of the PIV going from 1.4 - 3.0 GHz in around 25 months. That reduces to 40% if you add the 3.2 GHz update. Neither manufacturer is even close to achieving what you suggest though.
I'm not sure where people are getting the belief that clockspeed advances anywhere near 100% in anything close to 18 months but it doesn't and never has in recent history.
I'm not sure where people are getting the belief that clockspeed advances anywhere near 100% in anything close to 18 months but it doesn't and never has in recent history.
Of course, then again the prototype for the 970 probably started to appear 2 years ago already.
Actually, make that about one year ago (as far as Apple messing with 970 singles and duals). There were initial problems w/ Apple PI. IBM was none too happy about it either.
There seems to be an awful lot of people assuming an awful lot about the 980, its existance, and the timeframe of its supposed introduction. I suggest we bask in the glow of the 970 for a while and wait for this year's Microprocessor conference in October where we might hear a little more from IBM about their 9xx plans.
Sorry to hear about the WWDC part .
I concur about the MPF '04. It should be a very good time then, with exhilarating speed soon afterwards. I can't help but hope for IBM's success in getting the 90nm process underway, though. Definitely good times ahead. I find myself having to hold myself back from orderring a G5 now, but I have to pay off some bills first, darn it!
Actually, make that about one year ago (as far as Apple messing with 970 singles and duals). There were initial problems w/ Apple PI. IBM was none too happy about it either.
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
BA over in Ars has speculated that the move to .09 might bring an integrated memory controller, which would certainly solve the problem (if only by making it IBMs problem rather than Apples).
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
Well, they could eliminate the problem by integrating the 970 into the system controller. Why not? IBM is fabbing them both on the same process, after all!
Seriously, I wouldn't have guessed that they'd get a 500MHz clock under control, let alone manage that and fairly long paths to 8 slots of 128-bit DDR400. We've seen some really good work by Apple engineers here, and I wouldn't be shocked to discover that they'd had guidance from IBM engineers who are intimately familiar with the issues involved in building boards for the POWER4.
Quote:
BA over in Ars has speculated that the move to .09 might bring an integrated memory controller, which would certainly solve the problem (if only by making it IBMs problem rather than Apples).
Any comments on how prepared Apple is for that?
Well, if the memory controller ends up on board, the question becomes: which protocol replaces the Elastic Bus as an interface to the system controller? If it's HyperTransport, Apple's all set, because they've got HT all over the place on their newest boards. If it's RapidIO, they have a little extra work to do; but I have an odd feeling that a memory controller-sporting 970 will talk to the rest of the board via HyperTransport. That's the more appropriate connection technology for a workstation-grade CPU.
So with all these new chips in the pipeline do you guys rekon the motherboard design will have to be changed too, or is it just a question of upping the FSB for each rev?
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
Remember that Steve Jobs himself said that the G5 would be at 3GHz in 12 months.
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
BA over in Ars has speculated that the move to .09 might bring an integrated memory controller, which would certainly solve the problem (if only by making it IBMs problem rather than Apples).
Any comments on how prepared Apple is for that?
Note that IBM are already making the system controller (although Apple design it), on the same process as the 970. To do anything much other than taking the circuitry of the interface from the 970 and using it directly in the system controller would probably be foolish, and that automatically gives you a matching system.
It does seem that a jump from 2.0 ghz to 3.0 ghz would be a pretty amazing job. I don't think that th 970 is an interim chip at all. While I am not optimistic of it reaching 2.5 on the 130nm process. 2.2 or 2.3 wouldn't surprise me though. I really think the 90nm process will be the big key to take it to 3.0 and above.
And in defense of what Steve really said and what people are repeating. Steve said 3.0 "within" 12 months. Not in 12 months. Within implies 12 months or less.
Did a quick scan for the history of intel product release cycles, and this is what I came up with. It isn't precise, but should be generally accurate.
Pentium 4 1.4 & 1.5 around November 2000
Pentium 4 1.7 GHz Q1/2001
Pentium 4 2.0 Q2 or Q3/2001
Pentium 2.8 3rd quarter 2002
Pentium 3.2 2nd quarter 2003
Doesn't look like they ever quite doubled in 18 months, but they did come close. However since the release of the 2.8, things have slowed down a lot. Their move to 90nm will give them a little more legs, but with 3.2 just being released and 3.4 to 3.5 being a couple quarters down the road, even with the new process, they are going to be tasked hard to to keep pace with IBM using current designs.
I won't count Intel out by any means, but it should be a very interesting year. Especially once the G5's ship and get in the hands of real people.
DDR II is possible, quad-pumped and can take higher frequencies than DDR I. I'm not too familiar with all these coming kinds of memorytech, but I know for certain that DDR I is ending it's life, and something better will aid the G5's in the need for a ton of bandwidth.
I believe memory-speeds are a bigger problem now, than it will be in 12 months.
It does seem that a jump from 2.0 ghz to 3.0 ghz would be a pretty amazing job. I don't think that th 970 is an interim chip at all.
50% in one year is very good for PPC! That's a bigger percentage jump than from the G4 clock to the current highend G5 clock!
What's more. What is that from now? A whole 1 gig 970 more than a 2 gig 970.
Okay. That's 1 gig 970 more per chip. So in dual formations(!) a 3 gig 970 is giving us an extra 2 gig in 970 performance over what we have now..!
Put that into a G4 context. The percentage equivalent is insane. What is that? A 2 gig 970 is 4 gig G4! So over the next year, we're going to get the equivalent rise of 4 gig!!!! 3.4 integer G4, 5.4 fpu G4! In one year! Put like that... (Can somebody figure the percentage rise...?)
...that '50%' leap for PPC 970 to 3 gig is going to do alot more for PPC than Prescott will for Intel.
50% in one year is very good for PPC! That's a bigger percentage jump than from the G4 clock to the current highend G5 clock!
What's more. What is that from now? A whole 1 gig 970 more than a 2 gig 970.
Okay. That's 1 gig 970 more per chip. So in dual formations(!) a 3 gig 970 is giving us an extra 2 gig in 970 performance over what we have now..!
Put that into a G4 context. The percentage equivalent is insane. What is that? A 2 gig 970 is 4 gig G4! So over the next year, we're going to get the equivalent rise of 4 gig!!!! 3.4 integer G4, 5.4 fpu G4! In one year! Put like that... (Can somebody figure the percentage rise...?)
...that '50%' leap for PPC 970 to 3 gig is going to do alot more for PPC than Prescott will for Intel.
...den you got de bus...
Lemon Bon Bon
haha lemon bon bon ur posts are always so positive toward apple and like a 'we apple users rock' vibe to em...haha
That's right, LBB! The G5 will probably do more for the mac than the Prescott will for the x86-platform. A very good point is the bus, which is alot more static, staying at the same frequency when the core is getting faster, and it will be a bottleneck compared to the G5's buses. Then we've got these dual configurations. I believe the Prescott equivalents to the XEON will still use a shared-bus topology.
Everyone talking about quad G5s and dual dualcore G5s, remember one thing:
Two dual core G5s sounds good, but each core will be sharing the current frontside bus with the other core. This will be similar to the situation with the current dual G4s. Granted, the G5 bus does have a butt-load more bandwidth than the G4 bus, but it will still be an issue.
Everyone talking about quad G5s and dual dualcore G5s, remember one thing:
Two dual core G5s sounds good, but each core will be sharing the current frontside bus with the other core. This will be similar to the situation with the current dual G4s. Granted, the G5 bus does have a butt-load more bandwidth than the G4 bus, but it will still be an issue.
Will that really be an issue, if RAM-bandwidth can't keep up with the Elastic-bus' advances? Now, the memory is capaple of supplying with 6.4GB/s, but the processors eats 14.2GB/s. Making these dual-core will not increase the need for bandwidth it cannot get anyways by commodity RAM-hardware. I believe it will/can be a (much) cheaper way to increase the number of execution cores and processing power per system, compared to making a quad.
My head is kinda messy, hard to explain, but you do see my point?
Will that really be an issue, if RAM-bandwidth can't keep up with the Elastic-bus' advances? Now, the memory is capaple of supplying with 6.4GB/s, but the processors eats 14.2GB/s. Making these dual-core will not increase the need for bandwidth it cannot get anyways by commodity RAM-hardware. I believe it will/can be a (much) cheaper way to increase the number of execution cores and processing power per system, compared to making a quad.
My head is kinda messy, hard to explain, but you do see my point?
Yeah, I hear ya, and I agree. I'm not saying that IBM won't go that way (dual cores), I was just bringing up a potenial issue. But you may be right, the memory bandwidth may be more of a limiting factor than the two cores sharing on bus would be.
I don't that that we will ever see a PM with more than two packaged processors (meaning a dual dualcore I could see).
Yeah, I hear ya, and I agree. I'm not saying that IBM won't go that way (dual cores), I was just bringing up a potenial issue. But you may be right, the memory bandwidth may be more of a limiting factor than the two cores sharing on bus would be.
I don't that that we will ever see a PM with more than two packaged processors (meaning a dual dualcore I could see).
I could see the Xserver borrowing from the IBM blade server concept for "industrial strength" servers with the Apple name on them at some point in time if a market developed for some really serious hardware.
I could see the Xserver borrowing from the IBM blade server concept for "industrial strength" servers with the Apple name on them at some point in time if a market developed for some really serious hardware.
Comments
Originally posted by Smircle
I did not say different.
However, in the x86 camp, the advance in clockspeed has been faster than 2x in 18 month for some time now.
I'll just refer you to Eugene's posts on clockspeed changes for the past 18 months in the x86 world. Suffice to say AMD has advanced around 35% and Intel has advanced only around 40%. In fact Intel has maintained only around 55% improvement over the whole life of the PIV going from 1.4 - 3.0 GHz in around 25 months. That reduces to 40% if you add the 3.2 GHz update. Neither manufacturer is even close to achieving what you suggest though.
I'm not sure where people are getting the belief that clockspeed advances anywhere near 100% in anything close to 18 months but it doesn't and never has in recent history.
Originally posted by Telomar
I'm not sure where people are getting the belief that clockspeed advances anywhere near 100% in anything close to 18 months but it doesn't and never has in recent history.
Don't feed the trolls!
Originally posted by G-News
Of course, then again the prototype for the 970 probably started to appear 2 years ago already.
Actually, make that about one year ago (as far as Apple messing with 970 singles and duals). There were initial problems w/ Apple PI. IBM was none too happy about it either.
Originally posted by Programmer
Nope, they haven't sent me in a very long time.
There seems to be an awful lot of people assuming an awful lot about the 980, its existance, and the timeframe of its supposed introduction. I suggest we bask in the glow of the 970 for a while and wait for this year's Microprocessor conference in October where we might hear a little more from IBM about their 9xx plans.
Sorry to hear about the WWDC part
I concur about the MPF '04. It should be a very good time then, with exhilarating speed soon afterwards. I can't help but hope for IBM's success in getting the 90nm process underway, though. Definitely good times ahead. I find myself having to hold myself back from orderring a G5 now, but I have to pay off some bills first, darn it!
Originally posted by MacJedai
Actually, make that about one year ago (as far as Apple messing with 970 singles and duals). There were initial problems w/ Apple PI. IBM was none too happy about it either.
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
BA over in Ars has speculated that the move to .09 might bring an integrated memory controller, which would certainly solve the problem (if only by making it IBMs problem rather than Apples).
Any comments on how prepared Apple is for that?
Originally posted by johnsonwax
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
Well, they could eliminate the problem by integrating the 970 into the system controller.
Seriously, I wouldn't have guessed that they'd get a 500MHz clock under control, let alone manage that and fairly long paths to 8 slots of 128-bit DDR400. We've seen some really good work by Apple engineers here, and I wouldn't be shocked to discover that they'd had guidance from IBM engineers who are intimately familiar with the issues involved in building boards for the POWER4.
BA over in Ars has speculated that the move to .09 might bring an integrated memory controller, which would certainly solve the problem (if only by making it IBMs problem rather than Apples).
Any comments on how prepared Apple is for that?
Well, if the memory controller ends up on board, the question becomes: which protocol replaces the Elastic Bus as an interface to the system controller? If it's HyperTransport, Apple's all set, because they've got HT all over the place on their newest boards. If it's RapidIO, they have a little extra work to do; but I have an odd feeling that a memory controller-sporting 970 will talk to the rest of the board via HyperTransport. That's the more appropriate connection technology for a workstation-grade CPU.
Originally posted by johnsonwax
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
Remember that Steve Jobs himself said that the G5 would be at 3GHz in 12 months.
Originally posted by johnsonwax
This points out an obvious problem then. IBM making a 3GHz 970 != Apple shipping a 3GHz 970. I have trouble seeing Apple getting a 750MHz double-pumped FSB under control in the near term.
BA over in Ars has speculated that the move to .09 might bring an integrated memory controller, which would certainly solve the problem (if only by making it IBMs problem rather than Apples).
Any comments on how prepared Apple is for that?
Note that IBM are already making the system controller (although Apple design it), on the same process as the 970. To do anything much other than taking the circuitry of the interface from the 970 and using it directly in the system controller would probably be foolish, and that automatically gives you a matching system.
michael
And in defense of what Steve really said and what people are repeating. Steve said 3.0 "within" 12 months. Not in 12 months. Within implies 12 months or less.
Did a quick scan for the history of intel product release cycles, and this is what I came up with. It isn't precise, but should be generally accurate.
Pentium 4 1.4 & 1.5 around November 2000
Pentium 4 1.7 GHz Q1/2001
Pentium 4 2.0 Q2 or Q3/2001
Pentium 2.8 3rd quarter 2002
Pentium 3.2 2nd quarter 2003
Doesn't look like they ever quite doubled in 18 months, but they did come close. However since the release of the 2.8, things have slowed down a lot. Their move to 90nm will give them a little more legs, but with 3.2 just being released and 3.4 to 3.5 being a couple quarters down the road, even with the new process, they are going to be tasked hard to to keep pace with IBM using current designs.
I won't count Intel out by any means, but it should be a very interesting year. Especially once the G5's ship and get in the hands of real people.
I mean DDR 400 that the G5 has, what´s the maxium bandwidth of them ? A G5 at 3Ghz with a bus at 1,5 Ghz yeez...
I believe memory-speeds are a bigger problem now, than it will be in 12 months.
It does seem that a jump from 2.0 ghz to 3.0 ghz would be a pretty amazing job. I don't think that th 970 is an interim chip at all.
50% in one year is very good for PPC! That's a bigger percentage jump than from the G4 clock to the current highend G5 clock!
What's more. What is that from now? A whole 1 gig 970 more than a 2 gig 970.
Okay. That's 1 gig 970 more per chip. So in dual formations(!) a 3 gig 970 is giving us an extra 2 gig in 970 performance over what we have now..!
Put that into a G4 context. The percentage equivalent is insane. What is that? A 2 gig 970 is 4 gig G4! So over the next year, we're going to get the equivalent rise of 4 gig!!!! 3.4 integer G4, 5.4 fpu G4! In one year! Put like that... (Can somebody figure the percentage rise...?)
...that '50%' leap for PPC 970 to 3 gig is going to do alot more for PPC than Prescott will for Intel.
...den you got de bus...
Lemon Bon Bon
Originally posted by Lemon Bon Bon
50% in one year is very good for PPC! That's a bigger percentage jump than from the G4 clock to the current highend G5 clock!
What's more. What is that from now? A whole 1 gig 970 more than a 2 gig 970.
Okay. That's 1 gig 970 more per chip. So in dual formations(!) a 3 gig 970 is giving us an extra 2 gig in 970 performance over what we have now..!
Put that into a G4 context. The percentage equivalent is insane. What is that? A 2 gig 970 is 4 gig G4! So over the next year, we're going to get the equivalent rise of 4 gig!!!! 3.4 integer G4, 5.4 fpu G4! In one year! Put like that... (Can somebody figure the percentage rise...?)
...that '50%' leap for PPC 970 to 3 gig is going to do alot more for PPC than Prescott will for Intel.
...den you got de bus...
Lemon Bon Bon
haha lemon bon bon ur posts are always so positive toward apple and like a 'we apple users rock' vibe to em...haha
Need I say more? Heheh
Two dual core G5s sounds good, but each core will be sharing the current frontside bus with the other core. This will be similar to the situation with the current dual G4s. Granted, the G5 bus does have a butt-load more bandwidth than the G4 bus, but it will still be an issue.
Originally posted by Transcendental Octothorpe
Everyone talking about quad G5s and dual dualcore G5s, remember one thing:
Two dual core G5s sounds good, but each core will be sharing the current frontside bus with the other core. This will be similar to the situation with the current dual G4s. Granted, the G5 bus does have a butt-load more bandwidth than the G4 bus, but it will still be an issue.
Will that really be an issue, if RAM-bandwidth can't keep up with the Elastic-bus' advances? Now, the memory is capaple of supplying with 6.4GB/s, but the processors eats 14.2GB/s. Making these dual-core will not increase the need for bandwidth it cannot get anyways by commodity RAM-hardware. I believe it will/can be a (much) cheaper way to increase the number of execution cores and processing power per system, compared to making a quad.
My head is kinda messy, hard to explain, but you do see my point?
Originally posted by Zapchud
Will that really be an issue, if RAM-bandwidth can't keep up with the Elastic-bus' advances? Now, the memory is capaple of supplying with 6.4GB/s, but the processors eats 14.2GB/s. Making these dual-core will not increase the need for bandwidth it cannot get anyways by commodity RAM-hardware. I believe it will/can be a (much) cheaper way to increase the number of execution cores and processing power per system, compared to making a quad.
My head is kinda messy, hard to explain, but you do see my point?
Yeah, I hear ya, and I agree. I'm not saying that IBM won't go that way (dual cores), I was just bringing up a potenial issue. But you may be right, the memory bandwidth may be more of a limiting factor than the two cores sharing on bus would be.
I don't that that we will ever see a PM with more than two packaged processors (meaning a dual dualcore I could see).
Originally posted by Transcendental Octothorpe
Yeah, I hear ya, and I agree. I'm not saying that IBM won't go that way (dual cores), I was just bringing up a potenial issue. But you may be right, the memory bandwidth may be more of a limiting factor than the two cores sharing on bus would be.
I don't that that we will ever see a PM with more than two packaged processors (meaning a dual dualcore I could see).
I could see the Xserver borrowing from the IBM blade server concept for "industrial strength" servers with the Apple name on them at some point in time if a market developed for some really serious hardware.
Originally posted by RBR
I could see the Xserver borrowing from the IBM blade server concept for "industrial strength" servers with the Apple name on them at some point in time if a market developed for some really serious hardware.
Indeed, but that wouldn't be a PM, now would it?