[quote] Can anyone say Maya Unlimited 5.0 for OS X? <hr></blockquote>
Looking at the success of Maya Complete for the Mac, Maya Unlimited seems very probable. And with Dual 970's and a 8X AGP FireGL, that would be a pro's dream come true.
<strong>This has some good implications. First it shows how IBM under promises and over delivers; a rarity in the tech world. Also the 970 yields much be great. I'm assuming that the bus on the 2.5GHz is 1.25GHz (625MHz DDR). Impressive to say the least. Unless they are going for an elaborate bus ratio scheme.</strong><hr></blockquote>
\\That's a freaking serious assumtion. Bus @ 1.25GHz?
\\That's a freaking serious assumtion. Bus @ 1.25GHz?
ARe you speaking of the FSB? 1.25GHz?
The entire world would stop and gasp. OMG!</strong><hr></blockquote>
The 970's bus ratio is fixed at 1/4 the CPU clock speed, and its clock is doubled. So yes, a 2.5GHz 970 will have a bus that runs at an (effective) clock speed of 1.25GHz.
For those wondering, that's 10GB/s theoretical bandwidth, or about 8.8GB/s observed, assuming that the percentage lost to packet overhead is constant. Still not enough to sate the ravenous appetite of AltiVec, but a little tiny bit better than what we currently have, for definitions of "little tiny bit better" that approach a factor of 8.
\\That's a freaking serious assumtion. Bus @ 1.25GHz?
ARe you speaking of the FSB? 1.25GHz?
The entire world would stop and gasp. OMG!</strong><hr></blockquote>
I know how it sounds. I've tried demonstrating that the 970 bus CAN have a non-static bus ratio but have been told otherwise, that IBM has made it clear that it's a 2:1 bus period. I'm sitting on the fence for now on that issue. It can swing either way.
The 970's bus ratio is fixed at 1/4 the CPU clock speed, and its clock is doubled. So yes, a 2.5GHz 970 will have a bus that runs at an (effective) clock speed of 1.25GHz.
For those wondering, that's 10GB/s theoretical bandwidth, or about 8.8GB/s observed, assuming that the percentage lost to packet overhead is constant. Still not enough to sate the ravenous appetite of AltiVec, but a little tiny bit better than what we currently have, for definitions of "little tiny bit better" that approach a factor of 8.
<strong>Just curious... Without a release date, how do we know these aren't the specs for a second generation of 970s?</strong><hr></blockquote>
Because IBM's already said "...and we'll transition to .09 RSN". -> there won't _be_ a second generation of .13. These chips are actually being made at a .09 fab - warmup for the real work at .09.
"Still not enough to sate the ravenous appetite of AltiVec"</strong><hr></blockquote>
An Altivec calculation can rip through all of L1 & L2 in practically no time, particularly if it's streaming data of some kind.
All you have to do to guestimate the 'max' amount of bandwidth the VPU can suck up, is figure out 1) how many instructions/clock can be retired, 2) clock rate, 3) bits per instruction.
3) is 128 bits.
2) is 2.5 GHz.
1) is tougher, let's assume it's always just one.
I get _40_GB/s. (That's _bytes_)
Realize that a chunk of work can be 'saved' in the L1/L2 cache (or the registers, wherever)... but the tasks that AV is used on are data heavy -> they don't _FIT_ in the caches.
Nevermind that there's two integer units in the 970, and two FPUs -> 4x64 -> _another_ 256 bits/cycle.
I'm not saying that this is a really how much bandwidth you _need_, just that more is always better, and alot more is alot better
One of the key benefits of the ppc approach to FPUs & SIMD is that all the units can operate independently - it's just that actually doing this has been somewhat choked because lots of computing capacity can't get data fast enough. (If the AV unit is running full tilt, there's roughly zero bandwith to keep the integer units & FPUs fed. And the caches are filled with drek.)
Then there are duals, which need 2x the bandwidth.
"Still not enough to sate the ravenous appetite of AltiVec"</strong><hr></blockquote>
AltiVec is pretty much doomed to be memory bound. At peak efficiency, on the current G4, it's capable of processing something like 12GB of data per second. If the 970's bus were capable of handling that, it would have to run in the neighborhood of 3GHz, which would mean a 6GHz 970 - but the AltiVec unit on that monster would be capable of consuming something dangerously close to 100GB/sec.
AltiVec performance on memory-bound processes should skyrocket with the 970, especially if those processes are threaded well and the machine is SMP. But the bus still won't be able to come anywhere near saturating the AltiVec unit (the GigaBus will supply 1/5th the necessary bandwidth, as opposed to MaxBus, which supplies about 1/20th). It's capable of that much raw power.
If the first generation of the 970 does start with a top speed of 2.5GHz and you combine this with the software compianies that apple has aquired of the last 2 years. I do see a real increase in market share.
I also bet we see in 2004 or early 2005 Pixar will announce that will upgrade from intel to the IBM 970 running on OSX platform. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
There's not much publicly official info on anything to do with the 970 besides some non technical press releases and a presentation PDF. Hannibal from Ars has some private info he was supposed to disclose in part 2 of his epic 970 saga article but has yet to do so. Personally, knowing his bias, I think he is afraid of showing his findings in that it totally obliterates anything on the x86 side or processor design. </strong><hr></blockquote>
Just to clarify, Hannibal's "Part 2" hasn't arrived yet because he's still [still!!] waiting for a response from the IBM folk.
For those who don't know the whole story, I'll give an overview:
Hannibal decides he wants to write up the newly announced 970. He knows that he wants to do it in 2 parts, and starts work on part 1, while attempting to get additional information [accuracy is a good thing] for part 2. Hannibal finishes part 1, but he never receives a response from his people at IBM [who specifically stated they'd help him and answer his questions]. Without this information, H can't finish part 2, without wildly speculating... not something he does often when doing a HW write-up.
A few weeks after the posting of part 1, he makes an addendum at the end that stated that the second part would arrive on December 17th. That never happened. IT is now several months later, and still no word from the IBM folks.
There are several threads on the Ars site that talk about this.
Hope that clears up some stuff. ...and yes, I am peeved as well, but there is not much I can do about it. IMHO, he should post what he's got, with [NEED TO FILL IN DETAILS LATER] when he gets the answers he needs.... but I am an information junkie, so something is better than nothing in my opinion.
I'm gonna ask this again because I think my first post got buried in the excitement of Page 1...
If IBM is getting 1.8-2.5 Ghz on a .13 micron process, is there some down and dirty formula that might give an indication of speeds when these get shrunk to .09? Sorry for being a nag.
An Altivec calculation can rip through all of L1 & L2 in practically no time, particularly if it's streaming data of some kind.
All you have to do to guestimate the 'max' amount of bandwidth the VPU can suck up, is figure out 1) how many instructions/clock can be retired, 2) clock rate, 3) bits per instruction.
3) is 128 bits.
2) is 2.5 GHz.
1) is tougher, let's assume it's always just one.
I get _40_GB/s. (That's _bytes_)
Realize that a chunk of work can be 'saved' in the L1/L2 cache (or the registers, wherever)... but the tasks that AV is used on are data heavy -> they don't _FIT_ in the caches.
Nevermind that there's two integer units in the 970, and two FPUs -> 4x64 -> _another_ 256 bits/cycle.
I'm not saying that this is a really how much bandwidth you _need_, just that more is always better, and alot more is alot better
One of the key benefits of the ppc approach to FPUs & SIMD is that all the units can operate independently - it's just that actually doing this has been somewhat choked because lots of computing capacity can't get data fast enough. (If the AV unit is running full tilt, there's roughly zero bandwith to keep the integer units & FPUs fed. And the caches are filled with drek.)
Then there are duals, which need 2x the bandwidth.</strong><hr></blockquote>
Who initiated Altivec anyway, Apple, IBM, MOT? IBM didn't want it but who thought up the idea?
<strong>I'm gonna ask this again because I think my first post got buried in the excitement of Page 1...
If IBM is getting 1.8-2.5 Ghz on a .13 micron process, is there some down and dirty formula that might give an indication of speeds when these get shrunk to .09? Sorry for being a nag. </strong><hr></blockquote>
Figure 30%. So 2.3 - 3.25 GHz, extrapolating from the above frequencies. Of course, as the process matures, they should go higher.
[quote]Originally posted by Bigc:
<strong>Who initiated Altivec anyway, Apple, IBM, MOT? IBM didn't want it but who thought up the idea?</strong><hr></blockquote>
All three were involved in the design. The head of the development team was an Apple employee. I don't know how much more than that is known.
These specs look really good for Apple, but I feel that IBM's blade servers could actually result in damage to Apple.
Think about it - Apple sells loads of xServe's to these biotech company to do their protein cracking, or whatever.
A single rack of xServes is maybe 40 machines, 80 processors.
A rack of IBM PPC 970 blades will likely be 5 boxes, each with 14 blades, each with 2 processors = 140 processors.
These people aren't buying Apple hardware for its nice colours, but for its performance. If they can find similar performance for a similar price in a more compact unit, they'll buy it.
Plus, the Linux OS you'd run on the IBM kit is much better at clustering than Mac OS is, and so could be easier to manage for their systems folks.
Of course, if IBM and Apple can do a deal to put Mac OS X on IBM hardware, all bets are off, but I don't think this is likely. IBM have too great an investment in Linux.
Comments
[quote] Can anyone say Maya Unlimited 5.0 for OS X? <hr></blockquote>
Looking at the success of Maya Complete for the Mac, Maya Unlimited seems very probable. And with Dual 970's and a 8X AGP FireGL, that would be a pro's dream come true.
<strong>This has some good implications. First it shows how IBM under promises and over delivers; a rarity in the tech world. Also the 970 yields much be great. I'm assuming that the bus on the 2.5GHz is 1.25GHz (625MHz DDR). Impressive to say the least. Unless they are going for an elaborate bus ratio scheme.</strong><hr></blockquote>
\\That's a freaking serious assumtion. Bus @ 1.25GHz?
ARe you speaking of the FSB? 1.25GHz?
The entire world would stop and gasp. OMG!
<strong>
\\That's a freaking serious assumtion. Bus @ 1.25GHz?
ARe you speaking of the FSB? 1.25GHz?
The entire world would stop and gasp. OMG!</strong><hr></blockquote>
The 970's bus ratio is fixed at 1/4 the CPU clock speed, and its clock is doubled. So yes, a 2.5GHz 970 will have a bus that runs at an (effective) clock speed of 1.25GHz.
For those wondering, that's 10GB/s theoretical bandwidth, or about 8.8GB/s observed, assuming that the percentage lost to packet overhead is constant. Still not enough to sate the ravenous appetite of AltiVec, but a little tiny bit better than what we currently have, for definitions of "little tiny bit better" that approach a factor of 8.
[ 02-27-2003: Message edited by: Amorph ]</p>
<strong>
\\That's a freaking serious assumtion. Bus @ 1.25GHz?
ARe you speaking of the FSB? 1.25GHz?
The entire world would stop and gasp. OMG!</strong><hr></blockquote>
I know how it sounds. I've tried demonstrating that the 970 bus CAN have a non-static bus ratio but have been told otherwise, that IBM has made it clear that it's a 2:1 bus period. I'm sitting on the fence for now on that issue. It can swing either way.
<strong>
The 970's bus ratio is fixed at 1/4 the CPU clock speed, and its clock is doubled. So yes, a 2.5GHz 970 will have a bus that runs at an (effective) clock speed of 1.25GHz.
For those wondering, that's 10GB/s theoretical bandwidth, or about 8.8GB/s observed, assuming that the percentage lost to packet overhead is constant. Still not enough to sate the ravenous appetite of AltiVec, but a little tiny bit better than what we currently have, for definitions of "little tiny bit better" that approach a factor of 8.
[ 02-27-2003: Message edited by: Amorph ]</strong><hr></blockquote>
What do you mean by:
"Still not enough to sate the ravenous appetite of AltiVec"
<strong>Just curious... Without a release date, how do we know these aren't the specs for a second generation of 970s?</strong><hr></blockquote>
Because IBM's already said "...and we'll transition to .09 RSN". -> there won't _be_ a second generation of .13. These chips are actually being made at a .09 fab - warmup for the real work at .09.
<strong>What do you mean by:
"Still not enough to sate the ravenous appetite of AltiVec"</strong><hr></blockquote>
An Altivec calculation can rip through all of L1 & L2 in practically no time, particularly if it's streaming data of some kind.
All you have to do to guestimate the 'max' amount of bandwidth the VPU can suck up, is figure out 1) how many instructions/clock can be retired, 2) clock rate, 3) bits per instruction.
3) is 128 bits.
2) is 2.5 GHz.
1) is tougher, let's assume it's always just one.
I get _40_GB/s. (That's _bytes_)
Realize that a chunk of work can be 'saved' in the L1/L2 cache (or the registers, wherever)... but the tasks that AV is used on are data heavy -> they don't _FIT_ in the caches.
Nevermind that there's two integer units in the 970, and two FPUs -> 4x64 -> _another_ 256 bits/cycle.
I'm not saying that this is a really how much bandwidth you _need_, just that more is always better, and alot more is alot better
One of the key benefits of the ppc approach to FPUs & SIMD is that all the units can operate independently - it's just that actually doing this has been somewhat choked because lots of computing capacity can't get data fast enough. (If the AV unit is running full tilt, there's roughly zero bandwith to keep the integer units & FPUs fed. And the caches are filled with drek.)
Then there are duals, which need 2x the bandwidth.
<strong>What do you mean by:
"Still not enough to sate the ravenous appetite of AltiVec"</strong><hr></blockquote>
AltiVec is pretty much doomed to be memory bound. At peak efficiency, on the current G4, it's capable of processing something like 12GB of data per second. If the 970's bus were capable of handling that, it would have to run in the neighborhood of 3GHz, which would mean a 6GHz 970 - but the AltiVec unit on that monster would be capable of consuming something dangerously close to 100GB/sec.
AltiVec performance on memory-bound processes should skyrocket with the 970, especially if those processes are threaded well and the machine is SMP. But the bus still won't be able to come anywhere near saturating the AltiVec unit (the GigaBus will supply 1/5th the necessary bandwidth, as opposed to MaxBus, which supplies about 1/20th). It's capable of that much raw power.
[ 02-27-2003: Message edited by: Amorph ]
[ 02-27-2003: Message edited by: Amorph ]</p>
I also bet we see in 2004 or early 2005 Pixar will announce that will upgrade from intel to the IBM 970 running on OSX platform. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
<strong>
There's not much publicly official info on anything to do with the 970 besides some non technical press releases and a presentation PDF. Hannibal from Ars has some private info he was supposed to disclose in part 2 of his epic 970 saga article but has yet to do so. Personally, knowing his bias, I think he is afraid of showing his findings in that it totally obliterates anything on the x86 side or processor design.
Just to clarify, Hannibal's "Part 2" hasn't arrived yet because he's still [still!!] waiting for a response from the IBM folk.
For those who don't know the whole story, I'll give an overview:
Hannibal decides he wants to write up the newly announced 970. He knows that he wants to do it in 2 parts, and starts work on part 1, while attempting to get additional information [accuracy is a good thing] for part 2. Hannibal finishes part 1, but he never receives a response from his people at IBM [who specifically stated they'd help him and answer his questions]. Without this information, H can't finish part 2, without wildly speculating... not something he does often when doing a HW write-up.
A few weeks after the posting of part 1, he makes an addendum at the end that stated that the second part would arrive on December 17th. That never happened. IT is now several months later, and still no word from the IBM folks.
There are several threads on the Ars site that talk about this.
Hope that clears up some stuff. ...and yes, I am peeved as well, but there is not much I can do about it. IMHO, he should post what he's got, with [NEED TO FILL IN DETAILS LATER] when he gets the answers he needs.... but I am an information junkie, so something is better than nothing in my opinion.
If IBM is getting 1.8-2.5 Ghz on a .13 micron process, is there some down and dirty formula that might give an indication of speeds when these get shrunk to .09? Sorry for being a nag.
<strong>
An Altivec calculation can rip through all of L1 & L2 in practically no time, particularly if it's streaming data of some kind.
All you have to do to guestimate the 'max' amount of bandwidth the VPU can suck up, is figure out 1) how many instructions/clock can be retired, 2) clock rate, 3) bits per instruction.
3) is 128 bits.
2) is 2.5 GHz.
1) is tougher, let's assume it's always just one.
I get _40_GB/s. (That's _bytes_)
Realize that a chunk of work can be 'saved' in the L1/L2 cache (or the registers, wherever)... but the tasks that AV is used on are data heavy -> they don't _FIT_ in the caches.
Nevermind that there's two integer units in the 970, and two FPUs -> 4x64 -> _another_ 256 bits/cycle.
I'm not saying that this is a really how much bandwidth you _need_, just that more is always better, and alot more is alot better
One of the key benefits of the ppc approach to FPUs & SIMD is that all the units can operate independently - it's just that actually doing this has been somewhat choked because lots of computing capacity can't get data fast enough. (If the AV unit is running full tilt, there's roughly zero bandwith to keep the integer units & FPUs fed. And the caches are filled with drek.)
Then there are duals, which need 2x the bandwidth.</strong><hr></blockquote>
Who initiated Altivec anyway, Apple, IBM, MOT? IBM didn't want it but who thought up the idea?
<strong>Anyone old enough to remember when IBM was with the bad guys?</strong><hr></blockquote>
Also old enough to remember when IBM tanked due to bad management.
:eek:
That sends a shockwave through the computing community.
W-O-W!!!
1.8 970 = a 3.6 G4. That tops Intel to the year end.
But...BUT a 2.5 gig 970!?!?!?!?!?!?
:eek: :eek: :eek:
?!
Staggering. That will be the equivalent of a 5 gig G4!?!? Intel won't get to that level of performance until late 2004!!!
I'm in shock. :eek:
Put them in dual formation. That's the equivalent of a 10 gig G4 in terms of performance!
:eek:
Sandbagging. Indeed.
Macworld Newyork. Seismic announcement by Jobs. They, eventually, close the mhz gap and how.
A 2.5 970 will absolutely b*itch slap a Pentium 4 of any mhz from here until next year! And that's before you get to duals.
And as Amorph shrewdly noted, THAT altivec is going to fly on a 970 on that bandwidth at that mhz...g'yeesh.
Intel will get truly humiliated on Spec...and in real world performance...altivec enabled Photoshop filters!?!??!? Gurgle...
I want Lightwave benched on a 2.5 970. Then on duals!!!
I await the breath of the announcement from a certain fruit company...
Truly staggering.
Lemon Bon Bon
PS. Could Apple possibly not adopt this baby? They'd have to be stupifyingly nuts.
[ 02-27-2003: Message edited by: Lemon Bon Bon ]</p>
<hr></blockquote>
I remember that too.
Lemon Bon Bon :cool:
...oh and please put your goggles on.
<strong>I'm gonna ask this again because I think my first post got buried in the excitement of Page 1...
If IBM is getting 1.8-2.5 Ghz on a .13 micron process, is there some down and dirty formula that might give an indication of speeds when these get shrunk to .09? Sorry for being a nag.
Figure 30%. So 2.3 - 3.25 GHz, extrapolating from the above frequencies. Of course, as the process matures, they should go higher.
[quote]Originally posted by Bigc:
<strong>Who initiated Altivec anyway, Apple, IBM, MOT? IBM didn't want it but who thought up the idea?</strong><hr></blockquote>
All three were involved in the design. The head of the development team was an Apple employee. I don't know how much more than that is known.
[ 02-27-2003: Message edited by: Amorph ]</p>
Think about it - Apple sells loads of xServe's to these biotech company to do their protein cracking, or whatever.
A single rack of xServes is maybe 40 machines, 80 processors.
A rack of IBM PPC 970 blades will likely be 5 boxes, each with 14 blades, each with 2 processors = 140 processors.
These people aren't buying Apple hardware for its nice colours, but for its performance. If they can find similar performance for a similar price in a more compact unit, they'll buy it.
Plus, the Linux OS you'd run on the IBM kit is much better at clustering than Mac OS is, and so could be easier to manage for their systems folks.
Of course, if IBM and Apple can do a deal to put Mac OS X on IBM hardware, all bets are off, but I don't think this is likely. IBM have too great an investment in Linux.
Cheers!
[ 02-27-2003: Message edited by: ducasi ]</p>