Although I think that 2005 is a tease and it'll actually be sooner. Always exceed expectations by exaggerating development time/delays. Then when you ship on time it'll be perceived as early.
I think johnq is right on the money in his evaluation of Jozwiak's psychology. As I mentioned above, we had exactly the same scenario with the G3 to G4 transition in the iBook.
After Jozwiak's statement, we all expect a PowerBook G5 sometime in mid-2005. When the PowerBook G5 ships late this fall or at MWSF 2005, we'll all be positively surprised. QED.
If I remember well, Apple's statement about the G3 and the iBook G4 introduction are separated by more than one year.
My recollection is that the G3 statement came in early spring, i.e. just this time of the year. So the wait would have been more like 7 or 8 months. However, my memory is like a sieve and I have no desire to search for old news reports.
If it takes up to 2 years for a G5 to be used in a laptop, all I can say is I hope Motorola/STMicroelectronics/Phillips can meet their roadmap and introduce the 0.09µm process this year. I can't remember if they were projecting midyear or late in 2004. A G4 using a 0.09µm process, a 200MHz FSB and 1-2Mb L3 cache would be very competitive (expensive with L3 cache but competitive) and not too power hungry.
I don't expect DDR FSB capability for the G4 ever. If it happens for a computer CPU from Motorola it'll be a different generation of chip.
Customers will be able to use the chip in everything from PCs to notebooks to networking equipment, said Norman Rohrer, senior technical staff member at IBM
As it has already been discussed here, if integrated dual core G4s come in to light later this year or beginning 2005, then there is no point to move the Powerbooks to G5 for quite some time. And don't forget: this 1.5 GHz G4 came suddenly from the nowhere.
Aside from the need to update the FSB to something approaching modern??? Two G4's on the same old bus? Don't you think that would be a little bit slow? Didn't Apple try something like that before?
The G4 is very old technology. It needs to be replaced.
Aside from the need to update the FSB to something approaching modern??? Two G4's on the same old bus? Don't you think that would be a little bit slow? Didn't Apple try something like that before?
The G4 is very old technology. It needs to be replaced.
Apparently you missed the link I posted in the other thread ("Motorola is back"), from a SNDF presentation. We talk about a new G4 with system integration on it: DDRI and DDRII, advanced IO-RapidIO, general purpose IO. And dissipating 25 W at 1.5 GHz (dual core version). I really wish Motorola, or rather Freescale now, to be able to put into production this design, due this year according to the roadmap.
being behind isnt all that bad, they are holding off untill they get it absolutly right, and when they do, it will be released, and not a minute before. Apple, obviously, takes pride in what they make, if they were willing to stamp their name and seal on any peice of crap that that comes of the line, they would be no different than Dell, Gateway, HP or Microsoft.
I would rather have it late than horably flawed a month ahead of target.
Why the hell do people want G5s in laptops? You have massive power consumption and massive cooling requirements for the .09 micron part (due to massive leakage) and you want to put that into a low-power/low-circulation laptop.
Instead of wanting a modified G4 with low power consumption and lower heat output...
You have massive power consumption and massive cooling requirements for the .09 micron part (due to massive leakage) and you want to put that into a low-power/low-circulation laptop.
I haven't heard about the Massive leakage before, is there some more information you can provide?
I haven't heard about the Massive leakage before, is there some more information you can provide?
Well, are you aware of some of the problems associated with low K chips?
Quote:
Transistor leakage is becoming an increasing problem as semiconductor technology scales to smaller dimensions. Industry experts have called transistor leakage one of the fundamental challenges to Moore?s Law of technology scaling. Leakage problems are expected to get progressively worse as the industry scales to 90nm and 65nm transistors. Leakage power could easily dominate total chip power and prevent low power standby operation if not controlled.
I'm not an ECE or EE so I can't talk about the specifics, but what I do know is that when chips move to smaller manufacturing processes, there are power issues involving using much more power than previous chips in order to get the data through properly. It has to do a lot with Heisenberg's uncertainty principle: when you move the parts closer and closer together, there will be a point where the electrons will be unpredictable and will interact unpredictably. The result for chip design means that you need more power to get the electrons to move through the pipes successfully.
What this means for computers is that moving to smaller processes requires much more power and thus much more cooling, as the wattage increases dramatically.
Well, are you aware of some of the problems associated with low K chips?
NO
Quote:
Originally posted by g3pro
I'm not an ECE or EE so I can't talk about the specifics, but what I do know is that when chips move to smaller manufacturing processes, there are power issues involving using much more power than previous chips in order to get the data through properly. It has to do a lot with Heisenberg's uncertainty principle: when you move the parts closer and closer together, there will be a point where the electrons will be unpredictable and will interact unpredictably. The result for chip design means that you need more power to get the electrons to move through the pipes successfully.
What this means for computers is that moving to smaller processes requires much more power and thus much more cooling, as the wattage increases dramatically.
Quote:
Originally posted by g3pro case in point: intel's Prescott chip. 'nuff said.
No, not enough said, IBM's SSOI, the combination of all three processes is supposed to be a break through. Just because Intel is having a problem, does not mean other chip makers will.
Quote:
Originally posted by g3pro I hope I answered your question.
Not really, your answer was over generalized and didn't answer fully my question. Your statement goes against what IBM has stated. There were dozens of articles talking about IBM's 90nm transition being a huge breakthrough.
FYI: I am not trying to be rude, I am just looking for you to back up the statement you made.
Quote:
Originally posted by g3pro You have massive power consumption and massive cooling requirements for the .09 micron part (due to massive leakage) and you want to put that into a low-power/low-circulation laptop.
No, not enough said, IBM's SSOI, the combination of all three processes is supposed to be a break through. Just because Intel is having a problem, does not mean other chip makers will.
Not really, your answer was over generalized and didn't answer fully my question. Your statement goes against what IBM has stated. There were dozens of articles talking about IBM's 90nm transition being a huge breakthrough.
FYI: I am not trying to be rude, I am just looking for you to back up the statement you made.
The point is that the problems with moving to smaller processes is not with the actual companies doing it but the properties of physics. I'm sure that SSOI is going to be extremely important in getting 90nm chips to use less power, but it can only go so far.
The problem with Intel's Prescott on the 90nm process is that it required large amounts of cooling and power because of the massive amounts of leakage. Of course, Intel is moving to a larger pin setup for its next 90nm chip, but even that is not going to fix all the problems.
Basically, the G5 is still going to use lots of power and lots of cooling as a result leakage. And that's something you can't get past because of the fundamental properties of physics.
Would you want that in a laptop? I wouldn't. I would rather have a dual or quad core G4 with power saving features built in.
Freescale's going to 90nm this summer, though, so they'll be in the same pickle. They've got their ways around it (spacing transistors out carefully across the chip surface to minimize "hot spots", etc.) but they'll be battling the same problems IBM is, and Intel is, and AMD is.
I note that Motorola G4s tend to run at relatively high voltages, which might also be part of their approach to the problem? Anyone with more expertise than I have care to comment on that?
I fully expect the next PB to have the G5. IBM officially included notebooks in the PPC970fx target markets. Remember, that the PPC970fx is more energy efficient than any G4.
I think that the "new" PowerBook G4s are a prime example that Apple is milking their lines to long. Granted IBM has fabbing problems, so even if they wanted to ship a PowerBook G5 there would be no processors for them.
Apple probably needs a new system controller design and 0.09 nm fabbing for a PowerBook G5. But this problem can be solved with money!
I really hope that those fabbing problems will vanish and that the road is wide open for updated iMacs, PMs and a headless box.
Please let the iMac have a G5.
Aside from a position paper Motorola has not shown *any* signs that a dual core G4 with Rapid I/O connectivity is in the pipeline. I'm sure we would have heard about that processor if it would ship by Q1/2005.
Furthermore Apple would have to develop a completly new system controller around Rapid I/O instead of Hypertransport. The bus topology would be completly different from the PPC970fx. It is far simpler to scale down the G5 system controller in features (remove MP support) and size than to develop a completely new one.
The "new" G4s were a very modest update. It would take quite some money and brainshare to develop the new, new G4. I doubt Motorola has it and is interested in that market.
That's why I think Apple has simply no choice but to use the PPC970fx. There won't be any substantial updates to the G4 at least till Q1/2005.
Because the 970FX use less power than the 7447 at the same clock speed...
That isn't true at all. People keep making this statement with the only basis in IBM's microprocessor forum literature. This type of literature often conflates reality, with best case scenario testing, with projections, and a healthy dose of optimism -- a sort of advertorial/infomercial session really. According to this type of report IBM should have had 2Ghz G3's, or moto's G4 would already be at 1.8Ghz with a DDR FSB. It's rather obvious that they don't represent reality.
Production represents reality. Looking at Xserves and PMs, I think it's reather obvious that while the G5 is cool for a chip of its intended market, it isn't close to as cool as a 1.5Ghz 7447A.
Comments
Originally posted by johnq
Sky isn't falling, it's propped up with a stick.
Although I think that 2005 is a tease and it'll actually be sooner. Always exceed expectations by exaggerating development time/delays. Then when you ship on time it'll be perceived as early.
I think johnq is right on the money in his evaluation of Jozwiak's psychology. As I mentioned above, we had exactly the same scenario with the G3 to G4 transition in the iBook.
After Jozwiak's statement, we all expect a PowerBook G5 sometime in mid-2005. When the PowerBook G5 ships late this fall or at MWSF 2005, we'll all be positively surprised. QED.
Escher
Originally posted by PB
If I remember well, Apple's statement about the G3 and the iBook G4 introduction are separated by more than one year.
My recollection is that the G3 statement came in early spring, i.e. just this time of the year. So the wait would have been more like 7 or 8 months. However, my memory is like a sieve and I have no desire to search for old news reports.
PB: Feel free to investigate.
Escher
- Jasen.
I don't expect DDR FSB capability for the G4 ever. If it happens for a computer CPU from Motorola it'll be a different generation of chip.
Apple Confirms NO G5 PowerBooks anytime soon
blabla....
Customers will be able to use the chip in everything from PCs to notebooks to networking equipment, said Norman Rohrer, senior technical staff member at IBM
Source: TechWorld
Powerbook G5 between MWSF'05 and WWDC'05
Cheers
Originally posted by PB
As it has already been discussed here, if integrated dual core G4s come in to light later this year or beginning 2005, then there is no point to move the Powerbooks to G5 for quite some time. And don't forget: this 1.5 GHz G4 came suddenly from the nowhere.
Aside from the need to update the FSB to something approaching modern??? Two G4's on the same old bus? Don't you think that would be a little bit slow? Didn't Apple try something like that before?
The G4 is very old technology. It needs to be replaced.
Aside from the need to update the FSB to something approaching modern??? Two G4's on the same old bus? Don't you think that would be a little bit slow? Didn't Apple try something like that before?
The G4 is very old technology. It needs to be replaced.
Apparently you missed the link I posted in the other thread ("Motorola is back"), from a SNDF presentation. We talk about a new G4 with system integration on it: DDRI and DDRII, advanced IO-RapidIO, general purpose IO. And dissipating 25 W at 1.5 GHz (dual core version). I really wish Motorola, or rather Freescale now, to be able to put into production this design, due this year according to the roadmap.
I would rather have it late than horably flawed a month ahead of target.
Apple Confirms NO G5 PowerBooks anytime soon
Applele ?
Instead of wanting a modified G4 with low power consumption and lower heat output...
Originally posted by g3pro
You have massive power consumption and massive cooling requirements for the .09 micron part (due to massive leakage) and you want to put that into a low-power/low-circulation laptop.
I haven't heard about the Massive leakage before, is there some more information you can provide?
Originally posted by g3pro
Why the hell do people want G5s in laptops?
Because the 970FX use less power than the 7447 at the same clock speed _and_ have a modern bus interface.
Originally posted by oldmacfan
I haven't heard about the Massive leakage before, is there some more information you can provide?
Well, are you aware of some of the problems associated with low K chips?
Transistor leakage is becoming an increasing problem as semiconductor technology scales to smaller dimensions. Industry experts have called transistor leakage one of the fundamental challenges to Moore?s Law of technology scaling. Leakage problems are expected to get progressively worse as the industry scales to 90nm and 65nm transistors. Leakage power could easily dominate total chip power and prevent low power standby operation if not controlled.
I'm not an ECE or EE so I can't talk about the specifics, but what I do know is that when chips move to smaller manufacturing processes, there are power issues involving using much more power than previous chips in order to get the data through properly. It has to do a lot with Heisenberg's uncertainty principle: when you move the parts closer and closer together, there will be a point where the electrons will be unpredictable and will interact unpredictably. The result for chip design means that you need more power to get the electrons to move through the pipes successfully.
What this means for computers is that moving to smaller processes requires much more power and thus much more cooling, as the wattage increases dramatically.
case in point: intel's Prescott chip. 'nuff said.
I hope I answered your question.
Originally posted by g3pro
Well, are you aware of some of the problems associated with low K chips?
NO
Originally posted by g3pro
I'm not an ECE or EE so I can't talk about the specifics, but what I do know is that when chips move to smaller manufacturing processes, there are power issues involving using much more power than previous chips in order to get the data through properly. It has to do a lot with Heisenberg's uncertainty principle: when you move the parts closer and closer together, there will be a point where the electrons will be unpredictable and will interact unpredictably. The result for chip design means that you need more power to get the electrons to move through the pipes successfully.
What this means for computers is that moving to smaller processes requires much more power and thus much more cooling, as the wattage increases dramatically.
Originally posted by g3pro case in point: intel's Prescott chip. 'nuff said.
No, not enough said, IBM's SSOI, the combination of all three processes is supposed to be a break through. Just because Intel is having a problem, does not mean other chip makers will.
Originally posted by g3pro I hope I answered your question.
Not really, your answer was over generalized and didn't answer fully my question. Your statement goes against what IBM has stated. There were dozens of articles talking about IBM's 90nm transition being a huge breakthrough.
FYI: I am not trying to be rude, I am just looking for you to back up the statement you made.
Originally posted by g3pro You have massive power consumption and massive cooling requirements for the .09 micron part (due to massive leakage) and you want to put that into a low-power/low-circulation laptop.
Originally posted by oldmacfan
NO
No, not enough said, IBM's SSOI, the combination of all three processes is supposed to be a break through. Just because Intel is having a problem, does not mean other chip makers will.
Not really, your answer was over generalized and didn't answer fully my question. Your statement goes against what IBM has stated. There were dozens of articles talking about IBM's 90nm transition being a huge breakthrough.
FYI: I am not trying to be rude, I am just looking for you to back up the statement you made.
The point is that the problems with moving to smaller processes is not with the actual companies doing it but the properties of physics. I'm sure that SSOI is going to be extremely important in getting 90nm chips to use less power, but it can only go so far.
The problem with Intel's Prescott on the 90nm process is that it required large amounts of cooling and power because of the massive amounts of leakage. Of course, Intel is moving to a larger pin setup for its next 90nm chip, but even that is not going to fix all the problems.
Basically, the G5 is still going to use lots of power and lots of cooling as a result leakage. And that's something you can't get past because of the fundamental properties of physics.
Would you want that in a laptop? I wouldn't. I would rather have a dual or quad core G4 with power saving features built in.
I note that Motorola G4s tend to run at relatively high voltages, which might also be part of their approach to the problem? Anyone with more expertise than I have care to comment on that?
Originally posted by Amorph
Freescale's going to 90nm this summer, though, so they'll be in the same pickle.
Unbelievable!
My prediction: Q1/ 2005
Originally posted by Fat Freddy
My prediction: Q1/ 2005
Mine too, or at least it is my wish
I think that the "new" PowerBook G4s are a prime example that Apple is milking their lines to long. Granted IBM has fabbing problems, so even if they wanted to ship a PowerBook G5 there would be no processors for them.
Apple probably needs a new system controller design and 0.09 nm fabbing for a PowerBook G5. But this problem can be solved with money!
I really hope that those fabbing problems will vanish and that the road is wide open for updated iMacs, PMs and a headless box.
Please let the iMac have a G5.
Aside from a position paper Motorola has not shown *any* signs that a dual core G4 with Rapid I/O connectivity is in the pipeline. I'm sure we would have heard about that processor if it would ship by Q1/2005.
Furthermore Apple would have to develop a completly new system controller around Rapid I/O instead of Hypertransport. The bus topology would be completly different from the PPC970fx. It is far simpler to scale down the G5 system controller in features (remove MP support) and size than to develop a completely new one.
The "new" G4s were a very modest update. It would take quite some money and brainshare to develop the new, new G4. I doubt Motorola has it and is interested in that market.
That's why I think Apple has simply no choice but to use the PPC970fx. There won't be any substantial updates to the G4 at least till Q1/2005.
Originally posted by Smircle
Because the 970FX use less power than the 7447 at the same clock speed...
That isn't true at all. People keep making this statement with the only basis in IBM's microprocessor forum literature. This type of literature often conflates reality, with best case scenario testing, with projections, and a healthy dose of optimism -- a sort of advertorial/infomercial session really. According to this type of report IBM should have had 2Ghz G3's, or moto's G4 would already be at 1.8Ghz with a DDR FSB. It's rather obvious that they don't represent reality.
Production represents reality. Looking at Xserves and PMs, I think it's reather obvious that while the G5 is cool for a chip of its intended market, it isn't close to as cool as a 1.5Ghz 7447A.