Especially if it had a Cell co-processor (or co-processors) to handle real time rendering as well as HD encoding & decoding! (Not to mention my broadband connection).
I doubt we'll see an actual Cell processor in a Mac anytime soon (if ever), but I do think we'll be seeing Power, and Cell derived PowerPC processors fairly soon. I posed the question months ago if IBM had been working on cell based processors for a few years now, wouldn't we be seeing benefits of what they have learned from this technology in upcoming Power, and PowerPC processors? I think all the years of testing on multiple cells, and multiple cores alone puts IBM at an advantage when producing a multi-core PPC processors. With all that testing, and prototyping that must have been done I'm sure they have learned a few lessons, and found a few pitfalls that they now know to avoid. I'm sure they have discovered more than that alone, but my point is that they are at a great advantage in dealing with multi-core, technology. If only they would take one lesson from AMD and throw in that on-die memory controller everybody keeps talking about that is so highly regarded as being the key to the overwhelming performance of the Opteron processors.
I doubt we'll see an actual Cell processor in a Mac anytime soon (if ever), but I do think we'll be seeing Power, and Cell derived PowerPC processors fairly soon.
This really doesn't make sense to me. What does "Cell derived PowerPC" mean? The Cell contains a Power processor, so how would you derive a Power processor from it?
Any why wouldn't we see a Cell processor in a Mac? Assuming Apple can see how nicely their CoreXXXX technologies map onto a bunch of really fast vector processors (duh!), and once this thing gets into production (or a variation that has the balance of components that Apple wants... maybe 2 Power cores and only 4 SPUs, for example).
Cell is really about the System-on-chip and the small specialized cores so that you can afford a lot of them. Careful chip design and you get some pretty impressive clock rates and power consumption numbers.
This really doesn't make sense to me. What does "Cell derived PowerPC" mean? The Cell contains a Power processor, so how would you derive a Power processor from it?
cell is a powerpc. it need a brand new mainboard (that need a new kext) but ic can now run os x from 10.0. to 10.4. but it run like a g3 @ 4GHz. to use the vector unit apple must made the dirt work and make it accessible to developer like an altivec extension (if spu are altivec is esier)
noe look in prospective: insert a multicore power (for application that can' t be parallelized) and more spu (for all core image apps)....
The Sony playstation is going to having Altivec in it!
VMX = Altivec(TM)
Also, remember that Altivec was one of the things IBM incorporated into the PPC970 at Apple's request, circa 2001. This thing is going to Macs, no doubt about it.
I thought the PS2 already had two vector processing units in addition to the core processor within the Emotion Engine?
But anyway, all this tech will never be bad news for Apple. The question is at what point will we see some of this filter into the computers?
I thought the PS2 already had two vector processing units in addition to the core processor within the Emotion Engine?
But anyway, all this tech will never be bad news for Apple. The question is at what point will we see some of this filter into the computers?
Your correct. LSI's processor design, and vector processing unit is not Altivec, and is probably closer to the design that will be used in the PS3. Motorola has patented their design heavily. If however the Playstation is using the Altivec design this time I'm sure Motorola is getting paid for it. Or will be when they find out.
Your correct. LSI's processor design, and vector processing unit is not Altivec, and is probably closer to the design that will be used in the PS3. Motorola has patented their design heavily. If however the Playstation is using the Altivec design this time I'm sure Motorola is getting paid for it. Or will be when they find out.
I know that when the PS2 was launched, and for some time after the games programmers made little use of the vector units (the novelty?) in a similar way to the issuse which faced Apple and coding for the Altivec unit on the G4.
With that in mind, and if the VMX unit in Cell is similar enough to Altivec, what are the specific implications for a general code base which use these units (in games and in future software)? Does code require specificity for it's use or can it be 'ported' around for various different software applications?
I seem to remember reading an online article showing IBM's recent patents and one of those related to a compiler that could optimize code for, I think it mentioned, multiple processes or threads or something. I'll look again, but this could be interesting times ahead.
So Programmer, what do you think the odds are for Apple to drop Altivec support from the G6 and to simply forward such calls to a dedicated Cell CPU? This would reduce the G6 complexity and cost. You could treat Cell like an old math coprocessor.
This way the Power5 to G6 transition is simpler (no bolting on Altivec).
This way it is easier to cram multiple cores into a single G6 die because you have reduced the complexity of each core.
This way you don't have oddly redundant Altivec units on both the main CPU and the Cell CPU.
This way you could probably squeeze some extre MHz out of the G6 because you don't have to time your communication with the Altivec registers/etc.
Thoughts? I'm not up to date wrt the latest G6 rumors, all I know is that is is two cores on the die.
So Programmer, what do you think the odds are for Apple to drop Altivec support from the G6 and to simply forward such calls to a dedicated Cell CPU? This would reduce the G6 complexity and cost. You could treat Cell like an old math coprocessor.
Zero.
What is the one word that processor designers never mention when introducing their latest and greatest chips?
Latency
Quote:
This way the Power5 to G6 transition is simpler (no bolting on Altivec).
Given that they have at least 2 VMX implementations now, I don't see how that is a real problem. Especially with IBM's automated design tools.
Quote:
This way it is easier to cram multiple cores into a single G6 die because you have reduced the complexity of each core.
Why have multiple G6 cores when you can have even more SPUs? Most problems that can be made parallel also benefit from using vector units.
Quote:
This way you don't have oddly redundant Altivec units on both the main CPU and the Cell CPU.
People keeping saying "why have both" or "these are redundant"... but they are not. There is good reason to have both and they fulfill different purposes.
Quote:
This way you could probably squeeze some extre MHz out of the G6 because you don't have to time your communication with the Altivec registers/etc.
No more so than with the GPR/FPR files. The VMX unit doesn't slow down the chip -- you just have to look at all 9 cores on the Cell to see that!
Quote:
Thoughts? I'm not up to date wrt the latest G6 rumors, all I know is that is is two cores on the die. [/B]
There are no G6 rumors. There are dual core G5 rumors. If I had to start one I'd say G6 == Cell.
BTW: IBM was an equal partner in the initial VMX development so I'm quite sure that they do not pay Motorola/Freescale (or Apple for that matter) a cent.
Altivec uses ~10-12 million transistors, depending on implementation. It's not a millstone around the PowerPC's neck, and it becomes a less significant addition with every processor generation. By contrast, the execution logic of a Cell SPE takes up 7 million transistors.
It can also do tricks that no other SIMD unit (that I've heard of, and including the SPE's in Cell) can do.
And finally, it was designed to be integrated into the core of a PowerPC. It needs the low latency because the work it's used for frequently involves use of the scalar units as well (e.g., computing array indexes and pointer offsets). Isolating AltiVec as a separate core makes no sense. This is why the SPE's are a new design rather than being derived from AltiVec.
. . . BTW: IBM was an equal partner in the initial VMX development so I'm quite sure that they do not pay Motorola/Freescale (or Apple for that matter) a cent.
I believe it depends on the agreement, or contract, these three companies made. If all three had equal share in development of the vector unit, it could be wise to share equally in license fees. This way, if Sony and Toshiba produce these chip, IBM, Freescale and Apple will be paid equally for its use. For that matter, both IBM and Freescale may have been paying fees all along. Then again, the three inventors may have free use of the patent for products they manufacture. This would leave Apple out in the cold financially, however.
BTW, I think you are right about the cell being the G6 or whatever Apple wants to call it. The cell chip changes everything. For example, the G4 might have been Apple's low end CPU, and the G5 used in higher performance Macs. Now, I believe the Cell will be in everything. The low end Macs will have a lower performance version. It's just a question of when the transition takes place. I think Tiger may already have capability of using the SPEs, or SPUs, for the core services. If not, Apple is working on it now.
* 100 GBytes per second aggregate Memory & I/O speed:
* - Dual XDR controller gives 25.6 GBytes per second.
* - Dual configurable interfaces give 76.8 GBytes per second.
* 8 X "SPEs", 128 bit vector engines, 128 registers each.
* 2 instructions issued per cycle per SPE.
* Peak = 256 GigaFlops
* Double precision maths operations supported.
* 256KBytes "Local Store" per SPE.
* Internal communication is via 4 X 128 bit rings, up to 96 Bytes per cycle.
* PPE can handle 2 threads, this pretty much means it's taken from the POWER5.
* PPE includes VMX.
* PPE includes 512 KBytes Cache.
* "Dynamic Power Management" technology.
* Ten heat sensors
* 221 square mm in 90nm.
* 234 million transistors
* 90nm SOI, Low K, 8 layers of metal & Copper interconnect.
* IBM start manufacturing within 6 months, Sony to start later in the year.
Multiple simultaneous operating systems including Linux.
Apple may be involved as VMX (aka AltiVec) was an Apple initiative, with this the PPE core should boot OS X with little modification.
Looks like some architectural changes have been made since the patent application:
* Local Memory sizes have increased, they are now 256KBytes.
* Local memory is also referred to as "locking cache" so it may have the functionality of a cache as well a "local memory". The patent explicitly stated it was not a cache.
* The internal 1024 bit bus was not implemented, there is an internal bus system which runs at up to 96 bytes per clock.
* SPEs appear to contain an MMU and a DMA controller. Patent application did not mention a MMU in the SPEs.
I predict new PowerMacs within 8 months using Cell or a Cell variant.
Looks like IBM is finally going to use a low-k dielectric for the 90 nm fab. Combined with dual-liner strained silicon, a svelt Powerbook G5 will be very possible.
For Cell, it's not exactly a panacea. Depending on what the PPE architecture is like, it could be a worse performer at scalar ops than the G4 is. Also, 221 sq mm die running in excess of 2 GHz. It must be a concidence than no power numbers are bandied about for the entire chip.
100+ Watts for a 3 GHz chip? Can't wait to see the box that Sony will ship the thing in.
The one thing that I'm not completely sure on with cell is also the one thing that I think is getting totally blown out of proportion by news writers, and that is the use of: "Multiple simultaneous operating systems including Linux." I do not believe they are referring to full scale Operating systems, as in Windows, or the Mac OS type. I think this is in reference to a scaled function centric OS. At least for the time being. I don't think you'll be seeing a processor like this running Mac OS, and windows at the same time any time soon. Even though I believe these are more function focused OS's being (very lightly) described (and I think it's being done intentionally to help sell company stock) they are still being what I am perceiving as emulated. I may be wrong on this point too, but the SPE "cores can support multiple operating systems and programming models through the use of virtualization technologies." Isn't the term "virtualization technologies" just a glorified use of the term emulation?
Even if this were hardware emulation only running these operating systems and programming models, I think they are very scaled function focused routines.
Anyone else's thought's are, requested, and encouraged.
Comments
Originally posted by smalM
I would prefere a 970MP @ 3 GHz
Especially if it had a Cell co-processor (or co-processors) to handle real time rendering as well as HD encoding & decoding! (Not to mention my broadband connection).
Originally posted by onlooker
I doubt we'll see an actual Cell processor in a Mac anytime soon (if ever), but I do think we'll be seeing Power, and Cell derived PowerPC processors fairly soon.
This really doesn't make sense to me. What does "Cell derived PowerPC" mean? The Cell contains a Power processor, so how would you derive a Power processor from it?
Any why wouldn't we see a Cell processor in a Mac? Assuming Apple can see how nicely their CoreXXXX technologies map onto a bunch of really fast vector processors (duh!), and once this thing gets into production (or a variation that has the balance of components that Apple wants... maybe 2 Power cores and only 4 SPUs, for example).
Cell is really about the System-on-chip and the small specialized cores so that you can afford a lot of them. Careful chip design and you get some pretty impressive clock rates and power consumption numbers.
Originally posted by Programmer
This really doesn't make sense to me. What does "Cell derived PowerPC" mean? The Cell contains a Power processor, so how would you derive a Power processor from it?
The meaning is in the rest of the post.
noe look in prospective: insert a multicore power (for application that can' t be parallelized) and more spu (for all core image apps)....
Originally posted by Existence
The Sony playstation is going to having Altivec in it!
VMX = Altivec(TM)
Also, remember that Altivec was one of the things IBM incorporated into the PPC970 at Apple's request, circa 2001. This thing is going to Macs, no doubt about it.
I thought the PS2 already had two vector processing units in addition to the core processor within the Emotion Engine?
But anyway, all this tech will never be bad news for Apple. The question is at what point will we see some of this filter into the computers?
Originally posted by DaveLee
I thought the PS2 already had two vector processing units in addition to the core processor within the Emotion Engine?
But anyway, all this tech will never be bad news for Apple. The question is at what point will we see some of this filter into the computers?
Your correct. LSI's processor design, and vector processing unit is not Altivec, and is probably closer to the design that will be used in the PS3. Motorola has patented their design heavily. If however the Playstation is using the Altivec design this time I'm sure Motorola is getting paid for it. Or will be when they find out.
Originally posted by onlooker
Your correct. LSI's processor design, and vector processing unit is not Altivec, and is probably closer to the design that will be used in the PS3. Motorola has patented their design heavily. If however the Playstation is using the Altivec design this time I'm sure Motorola is getting paid for it. Or will be when they find out.
I know that when the PS2 was launched, and for some time after the games programmers made little use of the vector units (the novelty?) in a similar way to the issuse which faced Apple and coding for the Altivec unit on the G4.
With that in mind, and if the VMX unit in Cell is similar enough to Altivec, what are the specific implications for a general code base which use these units (in games and in future software)? Does code require specificity for it's use or can it be 'ported' around for various different software applications?
This way the Power5 to G6 transition is simpler (no bolting on Altivec).
This way it is easier to cram multiple cores into a single G6 die because you have reduced the complexity of each core.
This way you don't have oddly redundant Altivec units on both the main CPU and the Cell CPU.
This way you could probably squeeze some extre MHz out of the G6 because you don't have to time your communication with the Altivec registers/etc.
Thoughts? I'm not up to date wrt the latest G6 rumors, all I know is that is is two cores on the die.
Originally posted by Yevgeny
So Programmer, what do you think the odds are for Apple to drop Altivec support from the G6 and to simply forward such calls to a dedicated Cell CPU? This would reduce the G6 complexity and cost. You could treat Cell like an old math coprocessor.
Zero.
What is the one word that processor designers never mention when introducing their latest and greatest chips?
Latency
This way the Power5 to G6 transition is simpler (no bolting on Altivec).
Given that they have at least 2 VMX implementations now, I don't see how that is a real problem. Especially with IBM's automated design tools.
This way it is easier to cram multiple cores into a single G6 die because you have reduced the complexity of each core.
Why have multiple G6 cores when you can have even more SPUs? Most problems that can be made parallel also benefit from using vector units.
This way you don't have oddly redundant Altivec units on both the main CPU and the Cell CPU.
People keeping saying "why have both" or "these are redundant"... but they are not. There is good reason to have both and they fulfill different purposes.
This way you could probably squeeze some extre MHz out of the G6 because you don't have to time your communication with the Altivec registers/etc.
No more so than with the GPR/FPR files. The VMX unit doesn't slow down the chip -- you just have to look at all 9 cores on the Cell to see that!
Thoughts? I'm not up to date wrt the latest G6 rumors, all I know is that is is two cores on the die. [/B]
There are no G6 rumors. There are dual core G5 rumors. If I had to start one I'd say G6 == Cell.
BTW: IBM was an equal partner in the initial VMX development so I'm quite sure that they do not pay Motorola/Freescale (or Apple for that matter) a cent.
Originally posted by Programmer
Zero.
Thanks for the answers.
It can also do tricks that no other SIMD unit (that I've heard of, and including the SPE's in Cell) can do.
And finally, it was designed to be integrated into the core of a PowerPC. It needs the low latency because the work it's used for frequently involves use of the scalar units as well (e.g., computing array indexes and pointer offsets). Isolating AltiVec as a separate core makes no sense. This is why the SPE's are a new design rather than being derived from AltiVec.
Originally posted by Programmer
. . . BTW: IBM was an equal partner in the initial VMX development so I'm quite sure that they do not pay Motorola/Freescale (or Apple for that matter) a cent.
I believe it depends on the agreement, or contract, these three companies made. If all three had equal share in development of the vector unit, it could be wise to share equally in license fees. This way, if Sony and Toshiba produce these chip, IBM, Freescale and Apple will be paid equally for its use. For that matter, both IBM and Freescale may have been paying fees all along. Then again, the three inventors may have free use of the patent for products they manufacture. This would leave Apple out in the cold financially, however.
BTW, I think you are right about the cell being the G6 or whatever Apple wants to call it. The cell chip changes everything. For example, the G4 might have been Apple's low end CPU, and the G5 used in higher performance Macs. Now, I believe the Cell will be in everything. The low end Macs will have a lower performance version. It's just a question of when the transition takes place. I think Tiger may already have capability of using the SPEs, or SPUs, for the core services. If not, Apple is working on it now.
http://en.wikipedia.org/wiki/Cell_chip
This article was already referenced near the beginning of the thread.
http://www.blachford.info/computer/Cells/Cell6.html
APU = SPE or SPU.
PU = PPE.
* Clock speed over 4GHz.
* 100 GBytes per second aggregate Memory & I/O speed:
* - Dual XDR controller gives 25.6 GBytes per second.
* - Dual configurable interfaces give 76.8 GBytes per second.
* 8 X "SPEs", 128 bit vector engines, 128 registers each.
* 2 instructions issued per cycle per SPE.
* Peak = 256 GigaFlops
* Double precision maths operations supported.
* 256KBytes "Local Store" per SPE.
* Internal communication is via 4 X 128 bit rings, up to 96 Bytes per cycle.
* PPE can handle 2 threads, this pretty much means it's taken from the POWER5.
* PPE includes VMX.
* PPE includes 512 KBytes Cache.
* "Dynamic Power Management" technology.
* Ten heat sensors
* 221 square mm in 90nm.
* 234 million transistors
* 90nm SOI, Low K, 8 layers of metal & Copper interconnect.
* IBM start manufacturing within 6 months, Sony to start later in the year.
Multiple simultaneous operating systems including Linux.
Apple may be involved as VMX (aka AltiVec) was an Apple initiative, with this the PPE core should boot OS X with little modification.
Looks like some architectural changes have been made since the patent application:
* Local Memory sizes have increased, they are now 256KBytes.
* Local memory is also referred to as "locking cache" so it may have the functionality of a cache as well a "local memory". The patent explicitly stated it was not a cache.
* The internal 1024 bit bus was not implemented, there is an internal bus system which runs at up to 96 bytes per clock.
* SPEs appear to contain an MMU and a DMA controller. Patent application did not mention a MMU in the SPEs.
I predict new PowerMacs within 8 months using Cell or a Cell variant.
A Mac mini with a "smaller" Cell...?!?
Forget about it!
PC users will not be able to stop from switching, intel will crumble, M$ will flounder...
Sweet!
For Cell, it's not exactly a panacea. Depending on what the PPE architecture is like, it could be a worse performer at scalar ops than the G4 is. Also, 221 sq mm die running in excess of 2 GHz. It must be a concidence than no power numbers are bandied about for the entire chip.
100+ Watts for a 3 GHz chip? Can't wait to see the box that Sony will ship the thing in.
Even if this were hardware emulation only running these operating systems and programming models, I think they are very scaled function focused routines.
Anyone else's thought's are, requested, and encouraged.