Unless all of us have this wrong and the 970MP is in fact slated
for use in the PowerBooks @2.0 GHz as the new MOBILE PROCESSOR
Chances of them putting dual cores in a notebook before the PowerMac seem out of the question to me. I don't think they would do it that way, but If they have the G6, or Power5 versions of the 9xx processors already I would say that would be possible. But I doubt they do,
Check this out!
Quote:
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HTTP Web Server: Lotus Notes Exception - Document has been deleted
Talk About conformed! They removed the page. Looks like someone got wind of it. (Apple)
Original page in case you missed it.
Quote:
The dual 64-bit core PowerPC970MP? (970MP) is the next evolutionary step in the PowerPC 970 family of microprocessors. The higher frequency grade versions of the 970MP consume higher amounts of power than earlier IBM microprocessors do, and that can cause temperature issues. Each 970MP processor core contains a thermal diode used to monitor its operating temperature. The thermal diode must be monitored to ensure that the maximum operating temperature of the 970MP is not exceeded. These thermal diodes used by the microprocessors are unique to the PowerPC architecture and cannot be ?read? using standard thermal diode monitoring chips.
(there was a PDF document at the bottom of the page that was downloadable also, but I'm not going to host it.)
Ok now that the 970MP is pretty much confermed id like to bring up a point that has been bothering me. Im not too knowlegable about system architectures but this is what i have gathered. Currently the Dual G5 has two seperate proccessors each with their own seprate FSB. Now since the 970MP is a single chip it will probably be hooked up to a single FSB...i dont see how you can hook up two busses to one chip (please someone prove me wrong). Now if this is the case im scared, i doubt that this chip will have an on die bus controlling these two proccessors so what we might have is a huge bottleneck. This system could potentially be slower than a normal dual configuration with two FSB.
Unless all of us have this wrong and the 970MP is in fact slated
for use in the PowerBooks @2.0 GHz as the new MOBILE PROCESSOR
Its unlikely we would see a dual core G5 PB in 2005 or even 2006. I would suspect that Apple has been trying to shoehorn the 970GX into the PB without luck (probably due to the heat caused by the CPU and the 970 ASIC's).
The IBM info confirms a 970MP is close - so a Quad processor G5 PMac (by WWDC) will be jaw dropping!
It boils down to cost. However I see OMC as a possibility with the transition to 65nm and the resultant shrinking of the die.
I'd love to see SMT on each core and OMC on the G6
Cost vs. benefit. There is a lot of assumption that an on-chip memory controller is the right choice for these chips, but that isn't necessarily so -- especially if used in a multi-chip configuration.
Any chance these things are far enough along for an announcement along side Tiger in April? Otherwise, I would guess WWDC at the latest. My only reasoning is that PowerMacs need an update (they are due) and it is hard for me to imagine that IBM would state anything publicly (even without Steve's permission) if it wasn't a done deal and ready to fab (or in production). Any thoughts on this-people who know better than me?
Ok now that the 970MP is pretty much confermed id like to bring up a point that has been bothering me. Im not too knowlegable about system architectures but this is what i have gathered. Currently the Dual G5 has two seperate proccessors each with their own seprate FSB. Now since the 970MP is a single chip it will probably be hooked up to a single FSB...i dont see how you can hook up two busses to one chip (please someone prove me wrong). Now if this is the case im scared, i doubt that this chip will have an on die bus controlling these two proccessors so what we might have is a huge bottleneck. This system could potentially be slower than a normal dual configuration with two FSB.
I think we need THT's insights on that question. I'm still marveling at this this little diagram.
Quote:
Originally posted by THT
Text illustration:
Code:
--------------------------
| ---------- ---------- |
| | 1 MB L2 || 1 MB L2 | |
| |----------||----------| |
| | 970 || 970 | |
| | core || core | |
| ----..----------..---- |
| | PI bus arbiter | |
| ----------..---------- |
------------..------------
||
1+ GHz PI bus
||
to
U3 System ASIC
or
next gen northbridge
The PI is, surprisingly in an IBM document, the Apple Processor Interconnect, aka Apple PI, aka elastic bus, is it not?
So, it sounds like they took two complete 970 "GX" processors, except for a complete elastic bus arbiter, fabricated them on one die, and tied them together with an on-die elastic bus switch. L2 to L2 transfers, if done properly, can go through the switch, and not back to the northbridge. I'm taken the "double L2 caches" to mean that they are independent of each other and specific to their core.
That's the very definition of multi-core though. And likely not worse or better than a large unified, shared L2 for vast majority of cases. Still needs a large, high speed off-die backside L3 cache though.
It is possible to hook up two busses to one chip, but that requires all the i/o hardware to be designed that way and double the i/o pin-outs. That would make two completely independent cores per chip. Overall, that's probably not an economically advantageous way to package a dual core chip or design a supporting motherboard which would require double the FSB traces. Not to mention the existing Elastic bus is already very close to tapping out the supportable bandwidth of the RAM chips themselves. Faster RAM will help but doubling that bandwidth is big-$$. So you make due with a faster FSB and bigger caches for an overall significant speedup, near doubled if computations are CPU-bound, but not doubled if you are memory bandwidth-bound.
It is possible to hook up two busses to one chip, but that requires all the i/o hardware to be designed that way and double the i/o pin-outs. That would make two completely independent cores per chip. Overall, that's probably not an economically advantageous way to package a dual core chip or design a supporting motherboard which would require double the FSB traces. Not to mention the existing Elastic bus is already very close to tapping out the supportable bandwidth of the RAM chips themselves. Faster RAM will help but doubling that bandwidth is big-$$. So you make due with a faster FSB and bigger caches for an overall significant speedup, near doubled if computations are CPU-bound, but not doubled if you are memory bandwidth-bound.
ok so your saying that if the current dual g5's have their own bus at 1 ghz then a dual core g5 hooked up to one FSB would need to run at 2ghz for no bottleneck? Is a 2ghz FSB even feasable right now?
Which is why it was decided to keep the bus at the current speed and use an arbiter to allow both CPU cores to use that same bus.
If you have a memory intensive application where lots of data needs to be shoved around you will effectively half the bus speed for each CPU as they are both squeezing through the same bus.
The speed increase you will get from a dual core CPU for these types of applications is likely to be not that great.
But if you have a computationally intensive application chances are the two CPUs will never get in each other's way on the bus and speeds would almost be as good as two individual CPUs.
What does help a lot here is the increase of the L2 cache to 1MB. With this increase chances are that less instructions need to get (re-)fetched via the bus because they are already present in the L2 cache.
well for me, the qud pmac is coming within weeks. the ppc 970mp is ready and why apple has relased the new chud if they aren' t needed?
It could be that Apple just have gotten prototype samples of 970MP and they must redesign CHUD so they can start testing quad machines. CHUD Tools is used extensively inside Apple and they might not want to fork the development of these tools.
This scenario is quite plausible imho and it it were true we won't see quad Macs for several months, probably not even this year.
ok so your saying that if the current dual g5's have their own bus at 1 ghz then a dual core g5 hooked up to one FSB would need to run at 2ghz for no bottleneck? Is a 2ghz FSB even feasable right now?
I think Hiro's more salient point is that the current 1+ GHz G5 front side bus has more aggregate bandwidth than current memory technologies can deliver. So the bottleneck is the main memory, and having a higher performance FSB for a dual-core G5 won't buy it much. Ie, why would a 2 GHz FSB be needed if dual-channel PC3200 or PC2-5300 don't deliver more bandwidth than the current 1.25 GHz FSB of the 2.5 GHz Power Mac G5?
The cheapest way for Apple to get to 2 GHz FSB data rates is to evolve the 970 FSB from double data rate to quad data rate. Saves on pin-outs, saves on power. So, I think the 2 GHz data rates are feasible, right now. Other ways are to double the width of the bus to 64 bit, which is expensive, or to clock the FSB to 1 GHz for a 2 GHz data rate, which could have technical issues.
For the Power Mac G5, I do think Apple will stay with the 1/2 FSB ratio. So if they can ship a 3 GHz 970mp, it'll have 1.5 GHz FSB data rate, or a DDR 750 MHz FSB as it were.
For the Power Mac G5, I do think Apple will stay with the 1/2 FSB ratio. So if they can ship a 3 GHz 970mp, it'll have 1.5 GHz FSB data rate, or a DDR 750 MHz FSB as it were.
Why wouldn't a DDR 1.5GB solution work for a 3GHz 970MP?
Why wouldn't a DDR 1.5GB solution work for a 3GHz 970MP?
In my nomenclature, DDR 750 MHz = 1.5 GHz FSB data rate. Ie, for a 3 GHz 970-based CPU with an advertized 1.5 GHz FSB, it will have a 750 MHz real clock bus, but double the data rate.
While that is true, I'd also take it to the level of saying that 970 based PB's won't be coming anytime soon. What I expect to see soon is some sort of dual core machine with either an e600 or a PPE based processor.
Apple more than anything else needs to focus on more performance and much better battery life. After all why get a portable otherwise.
Dave
Quote:
Originally posted by hasapi
Its unlikely we would see a dual core G5 PB in 2005 or even 2006. I would suspect that Apple has been trying to shoehorn the 970GX into the PB without luck (probably due to the heat caused by the CPU and the 970 ASIC's).
The IBM info confirms a 970MP is close - so a Quad processor G5 PMac (by WWDC) will be jaw dropping!
Comments
Originally posted by FallenFromTheTree
Unless all of us have this wrong and the 970MP is in fact slated
for use in the PowerBooks @2.0 GHz as the new MOBILE PROCESSOR
Chances of them putting dual cores in a notebook before the PowerMac seem out of the question to me. I don't think they would do it that way, but If they have the G6, or Power5 versions of the 9xx processors already I would say that would be possible. But I doubt they do,
Check this out!
Our Apologies
You have attempted to enter a controlled access area that you are not currently entitled to view. IBM Microelectronics uses a entitlement process to protect potentially sensitive data.
Your entitlement is not an all or nothing proposition. Each user has a specific set of entitlements associated with their user profile. IBM employees, Business Partners and Customers may all have differing levels of entitlement. For example, all IBM employees would not have a blanket entitlement to all data. The IBM employee may only be entitled to information relating to their specific job responsibilities. This same principle applies to all users of this site.
Data accessible from this site may relate to IBM, IBM Business Partners, and Customers, and we take the responsibility for protecting that data very seriously. If you feel that you qualify for additional entitlements, please contact your IBM Representative or other IBM Contact person to secure additional entitlements. Thank you for your understanding of our privacy concerns, and again, we apologize for any inconvenience this may have caused you.
HTTP Web Server: Lotus Notes Exception - Document has been deleted
Talk About conformed! They removed the page. Looks like someone got wind of it. (Apple)
Original page in case you missed it.
The dual 64-bit core PowerPC970MP? (970MP) is the next evolutionary step in the PowerPC 970 family of microprocessors. The higher frequency grade versions of the 970MP consume higher amounts of power than earlier IBM microprocessors do, and that can cause temperature issues. Each 970MP processor core contains a thermal diode used to monitor its operating temperature. The thermal diode must be monitored to ensure that the maximum operating temperature of the 970MP is not exceeded. These thermal diodes used by the microprocessors are unique to the PowerPC architecture and cannot be ?read? using standard thermal diode monitoring chips.
(there was a PDF document at the bottom of the page that was downloadable also, but I'm not going to host it.)
Originally posted by FallenFromTheTree
Unless all of us have this wrong and the 970MP is in fact slated
for use in the PowerBooks @2.0 GHz as the new MOBILE PROCESSOR
Its unlikely we would see a dual core G5 PB in 2005 or even 2006. I would suspect that Apple has been trying to shoehorn the 970GX into the PB without luck (probably due to the heat caused by the CPU and the 970 ASIC's).
The IBM info confirms a 970MP is close - so a Quad processor G5 PMac (by WWDC) will be jaw dropping!
Originally posted by hmurchison
Well said THT.
It boils down to cost. However I see OMC as a possibility with the transition to 65nm and the resultant shrinking of the die.
I'd love to see SMT on each core and OMC on the G6
Cost vs. benefit. There is a lot of assumption that an on-chip memory controller is the right choice for these chips, but that isn't necessarily so -- especially if used in a multi-chip configuration.
It's also CRYSTAL CLEAR that Apple reads these forums.
I'm all for jaw dropping performance!
Originally posted by FallenFromTheTree
In the past 2 weeks Intel and AMD have openly raised the bar.
It's also CRYSTAL CLEAR that Apple reads these forums.
I'm all for jaw dropping performance!
I'm siding with him.
edit: sucky spelling
Originally posted by jsnuff1
Ok now that the 970MP is pretty much confermed id like to bring up a point that has been bothering me. Im not too knowlegable about system architectures but this is what i have gathered. Currently the Dual G5 has two seperate proccessors each with their own seprate FSB. Now since the 970MP is a single chip it will probably be hooked up to a single FSB...i dont see how you can hook up two busses to one chip (please someone prove me wrong). Now if this is the case im scared, i doubt that this chip will have an on die bus controlling these two proccessors so what we might have is a huge bottleneck. This system could potentially be slower than a normal dual configuration with two FSB.
I think we need THT's insights on that question. I'm still marveling at this this little diagram.
Originally posted by THT
Text illustration:
Code:
--------------------------
| ---------- ---------- |
| | 1 MB L2 || 1 MB L2 | |
| |----------||----------| |
| | 970 || 970 | |
| | core || core | |
| ----..----------..---- |
| | PI bus arbiter | |
| ----------..---------- |
------------..------------
||
1+ GHz PI bus
||
to
U3 System ASIC
or
next gen northbridge
The PI is, surprisingly in an IBM document, the Apple Processor Interconnect, aka Apple PI, aka elastic bus, is it not?
So, it sounds like they took two complete 970 "GX" processors, except for a complete elastic bus arbiter, fabricated them on one die, and tied them together with an on-die elastic bus switch. L2 to L2 transfers, if done properly, can go through the switch, and not back to the northbridge. I'm taken the "double L2 caches" to mean that they are independent of each other and specific to their core.
That's the very definition of multi-core though. And likely not worse or better than a large unified, shared L2 for vast majority of cases. Still needs a large, high speed off-die backside L3 cache though.
[Edit: illustration...]
Originally posted by Hiro
It is possible to hook up two busses to one chip, but that requires all the i/o hardware to be designed that way and double the i/o pin-outs. That would make two completely independent cores per chip. Overall, that's probably not an economically advantageous way to package a dual core chip or design a supporting motherboard which would require double the FSB traces. Not to mention the existing Elastic bus is already very close to tapping out the supportable bandwidth of the RAM chips themselves. Faster RAM will help but doubling that bandwidth is big-$$. So you make due with a faster FSB and bigger caches for an overall significant speedup, near doubled if computations are CPU-bound, but not doubled if you are memory bandwidth-bound.
ok so your saying that if the current dual g5's have their own bus at 1 ghz then a dual core g5 hooked up to one FSB would need to run at 2ghz for no bottleneck? Is a 2ghz FSB even feasable right now?
Originally posted by jsnuff1
Is a 2ghz FSB even feasable right now?
No it's not.
Which is why it was decided to keep the bus at the current speed and use an arbiter to allow both CPU cores to use that same bus.
If you have a memory intensive application where lots of data needs to be shoved around you will effectively half the bus speed for each CPU as they are both squeezing through the same bus.
The speed increase you will get from a dual core CPU for these types of applications is likely to be not that great.
But if you have a computationally intensive application chances are the two CPUs will never get in each other's way on the bus and speeds would almost be as good as two individual CPUs.
What does help a lot here is the increase of the L2 cache to 1MB. With this increase chances are that less instructions need to get (re-)fetched via the bus because they are already present in the L2 cache.
Originally posted by gelosilente
well for me, the qud pmac is coming within weeks. the ppc 970mp is ready and why apple has relased the new chud if they aren' t needed?
It could be that Apple just have gotten prototype samples of 970MP and they must redesign CHUD so they can start testing quad machines. CHUD Tools is used extensively inside Apple and they might not want to fork the development of these tools.
This scenario is quite plausible imho and it it were true we won't see quad Macs for several months, probably not even this year.
in any case the multi proc is a must, for me, in the next years
Originally posted by jsnuff1
ok so your saying that if the current dual g5's have their own bus at 1 ghz then a dual core g5 hooked up to one FSB would need to run at 2ghz for no bottleneck? Is a 2ghz FSB even feasable right now?
I think Hiro's more salient point is that the current 1+ GHz G5 front side bus has more aggregate bandwidth than current memory technologies can deliver. So the bottleneck is the main memory, and having a higher performance FSB for a dual-core G5 won't buy it much. Ie, why would a 2 GHz FSB be needed if dual-channel PC3200 or PC2-5300 don't deliver more bandwidth than the current 1.25 GHz FSB of the 2.5 GHz Power Mac G5?
The cheapest way for Apple to get to 2 GHz FSB data rates is to evolve the 970 FSB from double data rate to quad data rate. Saves on pin-outs, saves on power. So, I think the 2 GHz data rates are feasible, right now.
For the Power Mac G5, I do think Apple will stay with the 1/2 FSB ratio. So if they can ship a 3 GHz 970mp, it'll have 1.5 GHz FSB data rate, or a DDR 750 MHz FSB as it were.
Originally posted by THT
For the Power Mac G5, I do think Apple will stay with the 1/2 FSB ratio. So if they can ship a 3 GHz 970mp, it'll have 1.5 GHz FSB data rate, or a DDR 750 MHz FSB as it were.
Why wouldn't a DDR 1.5GB solution work for a 3GHz 970MP?
Originally posted by onlooker
Why wouldn't a DDR 1.5GB solution work for a 3GHz 970MP?
In my nomenclature, DDR 750 MHz = 1.5 GHz FSB data rate. Ie, for a 3 GHz 970-based CPU with an advertized 1.5 GHz FSB, it will have a 750 MHz real clock bus, but double the data rate.
Screenshot
and
PDF
Apple more than anything else needs to focus on more performance and much better battery life. After all why get a portable otherwise.
Dave
Originally posted by hasapi
Its unlikely we would see a dual core G5 PB in 2005 or even 2006. I would suspect that Apple has been trying to shoehorn the 970GX into the PB without luck (probably due to the heat caused by the CPU and the 970 ASIC's).
The IBM info confirms a 970MP is close - so a Quad processor G5 PMac (by WWDC) will be jaw dropping!