Hang on, wasn't this chip supposed to use PCI Express and 667Mhz DDR Ram? If so, what would be the point of using these on a 200Mhz bus, I don't remember this figure coming up before...
Hang on, wasn't this chip supposed to use PCI Express and 667Mhz DDR Ram? If so, what would be the point of using these on a 200Mhz bus, I don't remember this figure coming up before...
No, we're talking about a new processor. 7448D is a dual core version of the current G4 type (with a die shrink). 8461D is a dual core version of the next generation G4 with extra features like an on die memory controller, PCIe, faster bus, on board Ethernet and so forth.
7448D is so far just a rumor. 7448, 8461 and 8641D is not. They are confirmed by Freescale.
... 8461D is a dual core version of the next generation G4 with extra features like an on die memory controller, PCIe, faster bus, on board Ethernet and so forth. ...
I thought the 8000-series was the router processors, with no altivec or floating point, and that run at much lower speeds and temperatures.
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed? Shouldn't MPX as far as being a computer technology have been made to be more scalable than it has been?
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed? Shouldn't MPX as far as being a computer technology have been made to be more scalable than it has been?
Due to it's complexity and low latency IIRC. A 167Mhz MPX bus (on Macs) has got a lower latency to the mem controller then a 625Mhz (1.25Ghz effective) elastic bus.
So it has low latency, which is definitely a plus, but it's not enough because it simply can't shunt around data fast enough to other FSB technology. Or was latency when it was created seen as the main thing to target in regards to making a good FSB?
Another question, mpx is 64bit, if it were made 128bit, what would this change, would it be twice as 'fast', i.e. would the effective speed be doubled? I know that if this were easy it would have been done, plus intels and AMDs buses are low bit but pumped many times, is that correct?
Is MPX too complex so that it can't be double or quad pumped, neither have its width increased to 128bit and neither have it's clock speed increased past a theoretical 200Mhz?
Sorry for all the questions, would be great to have them answered though, I've always been curious as to why the G4's FSB has been behind that of the opposition.
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed?
Laziness, resource misallocation, perceived lack of demand, whatever.
Doubling the width would be as effective as doubling the speed, but then you get into backwards compatibility issues. In general interfaces are getting narrower over time, not wider.
So it has low latency, which is definitely a plus, but it's not enough because it simply can't shunt around data fast enough to other FSB technology. Or was latency when it was created seen as the main thing to target in regards to making a good FSB?
Don't know (though I'd suspect that the bandwidht was "good enough" when it was constructed), but latency is definetly important, that's what the whole on die mem controller buissnes is about. It's no fun for the CPU to have to wait for data from the mem, either because it can't respond fast enough or because it doesn't have the neccesary bandwidth.
Quote:
Originally posted by mattyj
Another question, mpx is 64bit, if it were made 128bit, what would this change, would it be twice as 'fast', i.e. would the effective speed be doubled? I know that if this were easy it would have been done, plus intels and AMDs buses are low bit but pumped many times, is that correct?
I don't know if you could still call it a MPX bus if you increased the pin count by x2, but yes it'd have the same effect as DDR. Designing support chips and mobos with it would become harder/more expensive though.
Quote:
Originally posted by mattyj Is MPX too complex so that it can't be double or quad pumped, neither have its width increased to 128bit and neither have it's clock speed increased past a theoretical 200Mhz?[/B]
The MPX bus protocol is designed to only support SDR, if you make it DDR or QDR it isn't a MPX bus anymore, by todays standards. Of course Freescale could extend the specification, but I don't see them doing that. Freescale is going on die mem controller on all their CPUs, spending money on the MPX bus is equal to waisting money in their perspective.
Thanks Eric, cleared up a few things for me. So an on die memory controller much like an AMD 64 chip, will be interesting to see how a G4 would perform without a FSB acting as a bottleneck. Whether or not it would be a worthy alternative (i.e. fast enough) to a G5 remains to be seen.
Sorry for all the questions, would be great to have them answered though, I've always been curious as to why the G4's FSB has been behind that of the opposition.
Mattyj, if you want more info, do a search including Amorph and Maxbus. He's had some interesting things to say on this front over the years...not that I can remember most of the things that he mentioned
I still can't work out why you'd bother with a dual 7448 on a 200Mhz bus? The drain on power and the heat profile, regardless of the shrink to 90nm, will still be prohibitive.
IMHO, this sounds like a prototype that Apple would use as a template for planning (cooling, battery consumption, form factor, manufacturing) of a 8641D-equipped piece of mobile hardware.
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed? Shouldn't MPX as far as being a computer technology have been made to be more scalable than it has been?
I really don't buy into the MPX bus' complexity being the reason its performance has lagged. Like wmf, I think the primary reason has been corporate idiocy.
There are corporate strategies for products, and Motorola simply stumbled over its own feet and left a 4+ year hole in the "host" processor lineup. At the time, 4 years ago, there were chip-to-chip bus wars, and Moto was leading a consortium of players with RapidIO. The corporate strategy was to use NUMA style architectures where processors had on-chip memory controllers and would be bridged to core logic ASICs and other processors with RapidIO.
The MPX processor bus was to be eliminated in this strategy. Motorola started divesting itself of core logic ASIC, ie northbridge chips, development for their own G4 processors, and left them to 3rd parties to take care of. They were expecting the G4 northbridges to go away essentially.
Well, Motorola had some corporate financial trouble at the time, worse yet, their fab went down the toilet and their processor design talent went to Intel. So they were left with essentially nothing. The fabs were late, so they really couldn't transition to architecture with RapidIO and their processor talent was gone, and really couldn't improve what they had. That was 4 years ago, and the stumbling continues on. Freescale really hasn't had time to change strategy, so they were left with incremental improvements as well.
The MPX bus itself shouldn't really present a problem for evolving to higher performance. I think it is fairly vanilla for a 64 bit wide parallel bus. The 128 bit wide data is actually in the specification but never implemented in hardware. Double data rate (double pumping) and quad data rate (quad pumping) are by far the easiest options to do: very small changes to footprint, multiple bus protocals (DDR MPX, MPX, 60X) could be supported, but obviously the effort was not put in.
With respect to making the bus wider, this approach is the opposite of the general trend. Making a bus wider increases the cost of the board (more traces in the same area, possibly more layers, more complex connectors). Putting trace space at a premium also exacerbates the problem of crosstalk, limiting scalability.
7448D is so far just a rumor. 7448, 8461 and 8641D is not. They are confirmed by Freescale.
The 7448 has also been confirmed by embedded manufactures advertising that the chip is available. So at least this guy is real and in atleast limited production.
Now if only Apple would implement and deliver products with it. Should give many users a nice performance boost. As to the 846** chips I still don't believe that Apple has an interest though Freescale could have very similar chips underwraps waiting for Apple to deliver.
These chips would be better optimized for PC usage and would take up a position in Freescales family of integrated processors.
the 7448 or the 7448d? I believe only the 7448 has been confirmed. And the 846x family will not interest PC vendors in the least. I'm sure its primary target is the embedded applications market.
Comments
Originally posted by mattyj
Hang on, wasn't this chip supposed to use PCI Express and 667Mhz DDR Ram? If so, what would be the point of using these on a 200Mhz bus, I don't remember this figure coming up before...
No, we're talking about a new processor. 7448D is a dual core version of the current G4 type (with a die shrink). 8461D is a dual core version of the next generation G4 with extra features like an on die memory controller, PCIe, faster bus, on board Ethernet and so forth.
7448D is so far just a rumor. 7448, 8461 and 8641D is not. They are confirmed by Freescale.
Originally posted by Henriok
... 8461D is a dual core version of the next generation G4 with extra features like an on die memory controller, PCIe, faster bus, on board Ethernet and so forth. ...
I thought the 8000-series was the router processors, with no altivec or floating point, and that run at much lower speeds and temperatures.
Originally posted by mattyj
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed? Shouldn't MPX as far as being a computer technology have been made to be more scalable than it has been?
Due to it's complexity and low latency IIRC. A 167Mhz MPX bus (on Macs) has got a lower latency to the mem controller then a 625Mhz (1.25Ghz effective) elastic bus.
Another question, mpx is 64bit, if it were made 128bit, what would this change, would it be twice as 'fast', i.e. would the effective speed be doubled? I know that if this were easy it would have been done, plus intels and AMDs buses are low bit but pumped many times, is that correct?
Is MPX too complex so that it can't be double or quad pumped, neither have its width increased to 128bit and neither have it's clock speed increased past a theoretical 200Mhz?
Sorry for all the questions, would be great to have them answered though, I've always been curious as to why the G4's FSB has been behind that of the opposition.
Originally posted by mattyj
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed?
Laziness, resource misallocation, perceived lack of demand, whatever.
Doubling the width would be as effective as doubling the speed, but then you get into backwards compatibility issues. In general interfaces are getting narrower over time, not wider.
Originally posted by mattyj
So it has low latency, which is definitely a plus, but it's not enough because it simply can't shunt around data fast enough to other FSB technology. Or was latency when it was created seen as the main thing to target in regards to making a good FSB?
Don't know (though I'd suspect that the bandwidht was "good enough" when it was constructed), but latency is definetly important, that's what the whole on die mem controller buissnes is about. It's no fun for the CPU to have to wait for data from the mem, either because it can't respond fast enough or because it doesn't have the neccesary bandwidth.
Originally posted by mattyj
Another question, mpx is 64bit, if it were made 128bit, what would this change, would it be twice as 'fast', i.e. would the effective speed be doubled? I know that if this were easy it would have been done, plus intels and AMDs buses are low bit but pumped many times, is that correct?
I don't know if you could still call it a MPX bus if you increased the pin count by x2, but yes it'd have the same effect as DDR. Designing support chips and mobos with it would become harder/more expensive though.
Originally posted by mattyj Is MPX too complex so that it can't be double or quad pumped, neither have its width increased to 128bit and neither have it's clock speed increased past a theoretical 200Mhz?[/B]
The MPX bus protocol is designed to only support SDR, if you make it DDR or QDR it isn't a MPX bus anymore, by todays standards. Of course Freescale could extend the specification, but I don't see them doing that. Freescale is going on die mem controller on all their CPUs, spending money on the MPX bus is equal to waisting money in their perspective.
Originally posted by Eric_Z
...
Thanks Eric, cleared up a few things for me. So an on die memory controller much like an AMD 64 chip, will be interesting to see how a G4 would perform without a FSB acting as a bottleneck. Whether or not it would be a worthy alternative (i.e. fast enough) to a G5 remains to be seen.
Originally posted by mattyj
Sorry for all the questions, would be great to have them answered though, I've always been curious as to why the G4's FSB has been behind that of the opposition.
Mattyj, if you want more info, do a search including Amorph and Maxbus. He's had some interesting things to say on this front over the years...not that I can remember most of the things that he mentioned
I still can't work out why you'd bother with a dual 7448 on a 200Mhz bus? The drain on power and the heat profile, regardless of the shrink to 90nm, will still be prohibitive.
IMHO, this sounds like a prototype that Apple would use as a template for planning (cooling, battery consumption, form factor, manufacturing) of a 8641D-equipped piece of mobile hardware.
Originally posted by mattyj
So could someone provide some insight for me to this: Why has MPX been stuck at the same bus speed for years, with so little improvements in speed? Shouldn't MPX as far as being a computer technology have been made to be more scalable than it has been?
I really don't buy into the MPX bus' complexity being the reason its performance has lagged. Like wmf, I think the primary reason has been corporate idiocy.
There are corporate strategies for products, and Motorola simply stumbled over its own feet and left a 4+ year hole in the "host" processor lineup. At the time, 4 years ago, there were chip-to-chip bus wars, and Moto was leading a consortium of players with RapidIO. The corporate strategy was to use NUMA style architectures where processors had on-chip memory controllers and would be bridged to core logic ASICs and other processors with RapidIO.
The MPX processor bus was to be eliminated in this strategy. Motorola started divesting itself of core logic ASIC, ie northbridge chips, development for their own G4 processors, and left them to 3rd parties to take care of. They were expecting the G4 northbridges to go away essentially.
Well, Motorola had some corporate financial trouble at the time, worse yet, their fab went down the toilet and their processor design talent went to Intel. So they were left with essentially nothing. The fabs were late, so they really couldn't transition to architecture with RapidIO and their processor talent was gone, and really couldn't improve what they had. That was 4 years ago, and the stumbling continues on. Freescale really hasn't had time to change strategy, so they were left with incremental improvements as well.
The MPX bus itself shouldn't really present a problem for evolving to higher performance. I think it is fairly vanilla for a 64 bit wide parallel bus. The 128 bit wide data is actually in the specification but never implemented in hardware. Double data rate (double pumping) and quad data rate (quad pumping) are by far the easiest options to do: very small changes to footprint, multiple bus protocals (DDR MPX, MPX, 60X) could be supported, but obviously the effort was not put in.
Originally posted by Henriok
7448D is so far just a rumor. 7448, 8461 and 8641D is not. They are confirmed by Freescale.
The 7448 has also been confirmed by embedded manufactures advertising that the chip is available. So at least this guy is real and in atleast limited production.
Now if only Apple would implement and deliver products with it. Should give many users a nice performance boost. As to the 846** chips I still don't believe that Apple has an interest though Freescale could have very similar chips underwraps waiting for Apple to deliver.
These chips would be better optimized for PC usage and would take up a position in Freescales family of integrated processors.
Dave