If they call the 7460 a "G5", then what do they call the 8500? A "G6"?
I'm still not sure about the Apollo ever going into Powermacs. If Apple does ship an Apollo Powermac in Feb., then what do they do when G5s are ready later in the year? Usually Apple doesn't fill the channels with a new CPU, then 6 months later empty them and refill them with an entirely new product. Speedbumped G4s and I could see this happen, but going through two different CPUs in one year? I dunno. That's why I think Apple will ship the G5 Powermacs, and then at MWNY, slip the Apollo into the iMac lineup. This way the entire desktop line would be between 1.0 and 1.6, 1.8 GHz by MWNY.
Well that's what I WANT, but I suppose it's not characteristic of Moto to deliver in that fashion.
The G5 will have a RapidIO port. Maybe even 2*8bit. This is for certain. It was stated on the old AI boards by Motoman, the best source we've (IMO) had. The specs posted on Geek.com sound about right, apart from the speeds. I really can't see Moto being able to get even a 14 stage pipeline on a .13 (Hip7) process at that sort of speed. I think that we'll be looking at between 1 and 1.6 Ghz G5's being released at somepoint this year. If Apollo's are released this month, then either MWNY or the Autumn Seybold. If not, then the Febuary Seybold.
Presented at Smart Networks Developer Forum, May 20-23, 2001. They focus a great deal on the e-500 core and the upcoming G5 chips. Yes, they're talking about the embedded chip, but it's silly to assume that they're putting all this effort into it if its going to be an embedded chip and nothing more. It is logical to assume that Apple is insisting they keep the desktop version under wraps. They may not be, but it is reasonable to suggest it.
"MOSR has misinformation... (1:50pm EST Tue Apr 10 2001)
...as usual. The G5 will not start out multicore and MacOS Rumors has the speeds wrong. On a 130nm process with SOI and copper, the 14 stage pipeline G5 will start at 1.6GHz and scale well beyond 2GHz. But before that we will see a 7460 G4 made on a 130nm SOI process, functionally equal to the 7450 but on an improved process. This G4 (codenamed Apollo), will achieve 1.2GHz and scall to most likely 1.7-1.8GHz.
Shortly (a quarter) after the debut of the 7460, you will see the 7500 on the same process in early 2002 with speeds between 1.6GHz and 2.5GHz. In late 2002 you will see the 100nm 75X0 start out at 2.4GHz and scale up to 3.5GHz. Also, MOSR neglected to mention that the 7500 will make extensive use of Rapid IO and have an on die DDR memory controller. The RIO ports will have a fast serial connection to several devices on the motherboard such as PCI-X bridges, peripheral controllers, ethernet and firewire controllers. The RIO bus is a serial 16-bit hub topology but runs at high speed (500-1000MHz). - by Mot insider"
[Note: This past summer Moto announced the renaming of the 7500 series to 8500.]
In light of what we know has transpired in the last 8 mo., he is very accurate on the Apollo information (particularly if they're what's coming next week at 1.2-1.4 GHz). That lends credance to his comments on the G5.
Those of you who claim there have been no reports of the G5 in the last two years ought to do a little nosing around on Motorola's web site and do a web search for "Motorola G5". You'll get thousands of hits. Yes, a lot of them are reports of a report of a report, but there are a few genuine nuggets in there, too. Its reliability is a matter of opinion, but saying it doesn't exist is ludicrous.
I'd be willing to give the first person that proves me (more like reminds me in a decade) wrong $100 that we will NEVER EVER see a 3.5 Ghz motorola processor powering a Macintosh computer.
I'd be willing to give the first person that proves me (more like reminds me in a decade) wrong $100 that we will NEVER EVER see a 3.5 Ghz motorola processor powering a Macintosh computer.
NEVER
EVER</strong><hr></blockquote>
Let me guess... 8 years ago you were declaring that the PPC601 didn't exist and we would NEVER EVER see a G4 chip, let alone one clocked as high as 800 MHz???? (the PowerMacs came out in March 1994, btw)
is it possible to strip altivec out of the g4/future g5 and have it on its own asic </strong><hr></blockquote>
There is nothing wrong with altivec. Why should they strip it out? Moto seems to have a problem with the cache design and definitely has a problem with the fpu design.
BTW does any compiler do optimisations for the G4e family (3+1 dispatch, more funtional units and different latency/thoughput timing compared to the G4 family)?
SoC program, the less complicated 8500 should be ready before that.
</strong><hr></blockquote>
Not sure about the "less complicated" thing - after all, the 8540 lacks both AltiVec and even a scalar FPU. And taking into account the rumored complete redesign of the FPU, it doesn't look much less complcated to me.
While you're pontificating you may want to change your post to reflect a little reality. If you are calling the 8500 the desktop version of the 8xxx series, then it is more complicated than the 8450, seeing as how the 8450 specs don't call out an altivec unit, L3 cache etc.</strong><hr></blockquote>
I think he might have been referring to the various integrated stuff inside the 8540 which is not strictly necessary for the desktop market (2 GBit Ethernet controllers, additional 100MBit one, PCI-X interface, DUART interface).
Then again, all those are just I/O "building blocks" connected to the OCeaN switch, so removing them wouldn't really reduce chip complexity that much (it wouldn't affect the core itself at all).
AltiVec and a scalar FPU on the other hand are an entirely different matter, as they extend (i.e. are directly connected to) the core itself.
is it possible to strip altivec out of the g4/future g5 and have it on its own asic (raycer guys job?), therefore allowing Apple to use strictly the embedded chips and saving Mot $$$ and time designing new chips??
just a thought...</strong><hr></blockquote>
Theoretically possible - maybe.
Practically feasible - no.
Having AltiVec on a separate ASIC would incur severe speed and design penalties. For every AltiVec instruction encountered in a program's instruction stream, the host processor would have to perform a (comparatively slow) I/O operation to talk to the AltiVec ASIC, and possibly to move data to be processed to / from the ASIC. This would likely be way slower than just doing the calculations inside the scalar FPU.
Remember that an embedded device is purpose specific, a desktop processor needs to fit in to a number of possible systems, with different requirements.
</strong><hr></blockquote>
I think the 8540 is still reasonably general purpose (neglecting the missing FPU). Admittedly, two of the Ethernet ports and the DUART would be unnecessary in a desktop environment, but the rest is basically a CPU + UniNorth on steroids (again, once an FPU is added).
Yes, they're talking about the embedded chip, but it's silly to assume that they're putting all this effort into it if its going to be an embedded chip and nothing more.
BTW does any compiler do optimisations for the G4e family (3+1 dispatch, more funtional units and different latency/thoughput timing compared to the G4 family)?
</strong><hr></blockquote>
In case you haven't been there already, the AltiVec mailing list (go to <a href="http://www.altivec.org)" target="_blank">www.altivec.org)</a> is probably a better place to pose such questions.
I'm aware of that. Once they have the basic G5 design, however, derivitives of it are relatively cheap. Apple is about 1/6th of their business, IIRC. I think Moto realizes that they will sell G5 desktop chips as fast as they can make them. Apple will do all their marketing, so the extra 10 or 20% investment (or whatever) to make a desktop processor out of it would have a huge ROI. That's sound business, nothing more.
Didn't CISCO buy the the G474XX for routers? I could have sworn they bought the same processor as Apple, could be wrong, heck, maybe routers don't use embedded processors, not my area of expertise.
Could we see a 1Ghz TiPB in the next couple of months?
I think the 14" iBook is also making room to stick a G4 chip in by Summer.
Let's see, by MWNY then:
iMac - Apollo G4 1Ghz and 1.2 Ghz
iBook - Apollo G4 800Mhz and 1Ghz ~ possible Superdrive?
Ti PB - Apollo G4 1.2. 1.4 and maybe 1.6Ghz + Superdrive.
PM - G5 running 1.6 1.8 2.0 Ghz. This is if we get G4.5 or "apollo G5" in next 30-45 days running at 1.2 1.4 and 1.6 Ghz (these would move into Ti PB by Summer then, all R&D payed off)
From the URL: "And no matter how fast the G4 processor is clocked at, the chip has its limits. This explains why we'll be seeing G5-equipped Macs this year.
<hr></blockquote>
Err...it occurs to me the author of that article might need to take a formal logic class. One chip having a specific shortcoming has no direct bearing on its successor's release date, only that there will *be* a successor.
[quote]The G5 may even come as early as this month's MacWorld in San Francisco. As any dedicated Mac aficionado knows, the semi-annual MacWorld Show and Conference is the traditional time at which Apple showcases its newest computers. At this year's Expo, held from January 8 to January 11, tens of thousands of MacHeads will line up to get a glimpse of the fastest Macs ever. And the Ranting One is guessing the G5 will be there!
<hr></blockquote>
The operative word being "guessing."
Not to pick on you Kid, but I think this is the kind of thing that stirs up the animosity between the two camps. Just because you can "provide a link", doesn't mean the link is worth anything - regardless of which stance the link benefits. People should be more careful in terms of posting something to be seen as "evidence". I know you were just showing yet another possibility, but...
...if everyone would only post links to information that is more or less concrete and verifiable...Motorola spokesperson comments, press releases, developer evidence, etc...things would be easier to discern.
Comments
I'm still not sure about the Apollo ever going into Powermacs. If Apple does ship an Apollo Powermac in Feb., then what do they do when G5s are ready later in the year? Usually Apple doesn't fill the channels with a new CPU, then 6 months later empty them and refill them with an entirely new product. Speedbumped G4s and I could see this happen, but going through two different CPUs in one year? I dunno. That's why I think Apple will ship the G5 Powermacs, and then at MWNY, slip the Apollo into the iMac lineup. This way the entire desktop line would be between 1.0 and 1.6, 1.8 GHz by MWNY.
Well that's what I WANT, but I suppose it's not characteristic of Moto to deliver in that fashion.
<a href="http://arstechnica.infopop.net/OpenTopic/page?q=Y&a=tpc&s=50009562&f=8300945231&m=336095374 3&p=1" target="_blank">Ars thread</a>
Lots of well-informed speculation about upcoming CPUs and memory tech.
<a href="http://www.eet.com/story/OEG19990507S0003"; target="_blank">EETimes</a>
Far more co-operation between IBM and Moto than many on these boards would have expected. (Taken from the above thread.)
<strong>You might take a look at this:
<a href="http://e-www.motorola.com/collateral/SNDFH1101.pdf"; target="_blank">Motorola PowerPC Microprocessor Family, Today and Tomorrow</a>
Presented at Smart Networks Developer Forum, May 20-23, 2001. They focus a great deal on the e-500 core and the upcoming G5 chips. Yes, they're talking about the embedded chip, but it's silly to assume that they're putting all this effort into it if its going to be an embedded chip and nothing more. It is logical to assume that Apple is insisting they keep the desktop version under wraps. They may not be, but it is reasonable to suggest it.
Another interesting link: <a href="http://www.geek.com/news/geeknews/2001apr/bch20010410005320.htm"; target="_blank">Geek.com News</a> from April 2001. The article itself isn't much, but the reply from "Mot Insider" is:
"MOSR has misinformation... (1:50pm EST Tue Apr 10 2001)
...as usual. The G5 will not start out multicore and MacOS Rumors has the speeds wrong. On a 130nm process with SOI and copper, the 14 stage pipeline G5 will start at 1.6GHz and scale well beyond 2GHz. But before that we will see a 7460 G4 made on a 130nm SOI process, functionally equal to the 7450 but on an improved process. This G4 (codenamed Apollo), will achieve 1.2GHz and scall to most likely 1.7-1.8GHz.
Shortly (a quarter) after the debut of the 7460, you will see the 7500 on the same process in early 2002 with speeds between 1.6GHz and 2.5GHz. In late 2002 you will see the 100nm 75X0 start out at 2.4GHz and scale up to 3.5GHz. Also, MOSR neglected to mention that the 7500 will make extensive use of Rapid IO and have an on die DDR memory controller. The RIO ports will have a fast serial connection to several devices on the motherboard such as PCI-X bridges, peripheral controllers, ethernet and firewire controllers. The RIO bus is a serial 16-bit hub topology but runs at high speed (500-1000MHz). - by Mot insider"
[Note: This past summer Moto announced the renaming of the 7500 series to 8500.]
In light of what we know has transpired in the last 8 mo., he is very accurate on the Apollo information (particularly if they're what's coming next week at 1.2-1.4 GHz). That lends credance to his comments on the G5.
Those of you who claim there have been no reports of the G5 in the last two years ought to do a little nosing around on Motorola's web site and do a web search for "Motorola G5". You'll get thousands of hits. Yes, a lot of them are reports of a report of a report, but there are a few genuine nuggets in there, too. Its reliability is a matter of opinion, but saying it doesn't exist is ludicrous.
[edit: typo]
[ 01-15-2002: Message edited by: TJM ]</strong><hr></blockquote>
LOL!
I'd be willing to give the first person that proves me (more like reminds me in a decade) wrong $100 that we will NEVER EVER see a 3.5 Ghz motorola processor powering a Macintosh computer.
NEVER
EVER
<strong>
LOL!
I'd be willing to give the first person that proves me (more like reminds me in a decade) wrong $100 that we will NEVER EVER see a 3.5 Ghz motorola processor powering a Macintosh computer.
NEVER
EVER</strong><hr></blockquote>
Let me guess... 8 years ago you were declaring that the PPC601 didn't exist and we would NEVER EVER see a G4 chip, let alone one clocked as high as 800 MHz???? (the PowerMacs came out in March 1994, btw)
<strong>for all your chip gurus out there..
is it possible to strip altivec out of the g4/future g5 and have it on its own asic </strong><hr></blockquote>
There is nothing wrong with altivec. Why should they strip it out? Moto seems to have a problem with the cache design and definitely has a problem with the fpu design.
BTW does any compiler do optimisations for the G4e family (3+1 dispatch, more funtional units and different latency/thoughput timing compared to the G4 family)?
[ 01-16-2002: Message edited by: smalM ]</p>
<strong>
Seeing as it is a further foray into Moto's
SoC program, the less complicated 8500 should be ready before that.
</strong><hr></blockquote>
Not sure about the "less complicated" thing - after all, the 8540 lacks both AltiVec and even a scalar FPU. And taking into account the rumored complete redesign of the FPU, it doesn't look much less complcated to me.
Bye,
RazzFazz
<strong>
While you're pontificating you may want to change your post to reflect a little reality. If you are calling the 8500 the desktop version of the 8xxx series, then it is more complicated than the 8450, seeing as how the 8450 specs don't call out an altivec unit, L3 cache etc.</strong><hr></blockquote>
I think he might have been referring to the various integrated stuff inside the 8540 which is not strictly necessary for the desktop market (2 GBit Ethernet controllers, additional 100MBit one, PCI-X interface, DUART interface).
Then again, all those are just I/O "building blocks" connected to the OCeaN switch, so removing them wouldn't really reduce chip complexity that much (it wouldn't affect the core itself at all).
AltiVec and a scalar FPU on the other hand are an entirely different matter, as they extend (i.e. are directly connected to) the core itself.
Bye,
RazzFazz
<strong>
Support for specific ports and Ethernet is built into the processor? What's the motherboard for?
For that matter, why would an embedded processor depend upon Ethernet but a desktop processor wouldn't?</strong><hr></blockquote>
Well, the 8540 has three of them (1x100MBit, 2xGBit), which are usful for embedded / networking applications, but not so much so for a PowerMac.
Bye,
RazzFazz
<strong>for all your chip gurus out there..
is it possible to strip altivec out of the g4/future g5 and have it on its own asic (raycer guys job?), therefore allowing Apple to use strictly the embedded chips and saving Mot $$$ and time designing new chips??
just a thought...</strong><hr></blockquote>
Theoretically possible - maybe.
Practically feasible - no.
Having AltiVec on a separate ASIC would incur severe speed and design penalties. For every AltiVec instruction encountered in a program's instruction stream, the host processor would have to perform a (comparatively slow) I/O operation to talk to the AltiVec ASIC, and possibly to move data to be processed to / from the ASIC. This would likely be way slower than just doing the calculations inside the scalar FPU.
Bye,
RazzFazz
<strong>
Remember that an embedded device is purpose specific, a desktop processor needs to fit in to a number of possible systems, with different requirements.
</strong><hr></blockquote>
I think the 8540 is still reasonably general purpose (neglecting the missing FPU). Admittedly, two of the Ethernet ports and the DUART would be unnecessary in a desktop environment, but the rest is basically a CPU + UniNorth on steroids (again, once an FPU is added).
Bye,
RazzFazz
<strong>
Yes, they're talking about the embedded chip, but it's silly to assume that they're putting all this effort into it if its going to be an embedded chip and nothing more.
</strong><hr></blockquote>
"just embedded, nothing more"?
Guess where Moto make most of their money.
Bye,
RazzFazz
<strong>Did Mot ever mention anything about the non-embedded G4 or G3 before it came out?</strong><hr></blockquote>
There is no such thing as an embedded version of the G3 or G4.
Bye,
RazzFazz
<strong>
BTW does any compiler do optimisations for the G4e family (3+1 dispatch, more funtional units and different latency/thoughput timing compared to the G4 family)?
</strong><hr></blockquote>
In case you haven't been there already, the AltiVec mailing list (go to <a href="http://www.altivec.org)" target="_blank">www.altivec.org)</a> is probably a better place to pose such questions.
Bye,
RazzFazz
<strong>
"just embedded, nothing more"?
Guess where Moto make most of their money.
Bye,
RazzFazz</strong><hr></blockquote>
I'm aware of that.
[ 01-16-2002: Message edited by: TJM ]</p>
"There is no such thing as an embedded version of the G3 or G4."
I'll bite. This confuses me, if you go to Motorola's website for products, all Power PC products are listed under the "embedded processor" section.
<a href="http://e-www.motorola.com/"; target="_blank">http://e-www.motorola.com/</a>;
Didn't CISCO buy the the G474XX for routers? I could have sworn they bought the same processor as Apple, could be wrong, heck, maybe routers don't use embedded processors, not my area of expertise.
<strong>RazzFazz
"There is no such thing as an embedded version of the G3 or G4."
I'll bite. This confuses me, if you go to Motorola's website for products, all Power PC products are listed under the "embedded processor" section.
</strong><hr></blockquote>
That was RazzFazz's point: There can't be an embedded version of an embedded processor, now can there?
Could we see a 1Ghz TiPB in the next couple of months?
I think the 14" iBook is also making room to stick a G4 chip in by Summer.
Let's see, by MWNY then:
iMac - Apollo G4 1Ghz and 1.2 Ghz
iBook - Apollo G4 800Mhz and 1Ghz ~ possible Superdrive?
Ti PB - Apollo G4 1.2. 1.4 and maybe 1.6Ghz + Superdrive.
PM - G5 running 1.6 1.8 2.0 Ghz. This is if we get G4.5 or "apollo G5" in next 30-45 days running at 1.2 1.4 and 1.6 Ghz (these would move into Ti PB by Summer then, all R&D payed off)
may want to change your post to reflect a little reality. If you are
calling the 8500 the desktop version of the 8xxx series, then it is
more complicated than the 8450, seeing as how the 8450 specs don't
call out an a ltivec unit, L3 cache etc.</strong><hr></blockquote>
More complicated? Oh please. You haven't seen the documentation for the
8540 (which you can't get right -- the 8450 is not the 8540). 2x ethernet
controllers and DSP-like functionality on board for starters. The 8500
will have a book E core with altivec (which is finished, obviously) and
maybe an onboard memory controller. Did you think of that, genius?
They think a G5 is soming-
From the URL: "And no matter how fast the G4 processor is clocked at, the chip has its limits. This explains why we'll be seeing G5-equipped Macs this year.
<hr></blockquote>
Err...it occurs to me the author of that article might need to take a formal logic class. One chip having a specific shortcoming has no direct bearing on its successor's release date, only that there will *be* a successor.
[quote]The G5 may even come as early as this month's MacWorld in San Francisco. As any dedicated Mac aficionado knows, the semi-annual MacWorld Show and Conference is the traditional time at which Apple showcases its newest computers. At this year's Expo, held from January 8 to January 11, tens of thousands of MacHeads will line up to get a glimpse of the fastest Macs ever. And the Ranting One is guessing the G5 will be there!
<hr></blockquote>
The operative word being "guessing."
Not to pick on you Kid, but I think this is the kind of thing that stirs up the animosity between the two camps. Just because you can "provide a link", doesn't mean the link is worth anything - regardless of which stance the link benefits. People should be more careful in terms of posting something to be seen as "evidence". I know you were just showing yet another possibility, but...
...if everyone would only post links to information that is more or less concrete and verifiable...Motorola spokesperson comments, press releases, developer evidence, etc...things would be easier to discern.