"We know internally that Apple has been replacing the acronym WWDC with the phrase "We Will Delight Crowds."
Crowds of developers or crowds of consumers?
Developers. Free books, answer their questions, insight into Panther frameworks etc. They need to get the "developers! developers! developers!" excited about the future of programming for the OS X platform. Of course it wouldn't hurt if they passed out a few new 15" AlBooks. .
Cnet confirms Hypertransport at WWDC, hints at 970.
"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.
It may also discuss plans to adopt IBM's PowerPC 970 processor, sources have suggested. The PowerPC 970 can handle 32-bit software--found on most desktops--and 64-bit software, which is found on high-end servers. Among the benefits of 64-bit computers is that they can take advantage of far more memory than 32-bit machines."
Cnet confirms Hypertransport at WWDC, hints at 970.
"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.
It may also discuss plans to adopt IBM's PowerPC 970 processor, sources have suggested. The PowerPC 970 can handle 32-bit software--found on most desktops--and 64-bit software, which is found on high-end servers. Among the benefits of 64-bit computers is that they can take advantage of far more memory than 32-bit machines."
Well, I think they got the details wrong. Do we know if the 970 has HT buses (even a variant?). HT on the motherboard makes sence in the context of connecting stuff to the memory controller, i.e. memory controller to an auxillary controller instead of using PCI. The processor to memory controller link could be HT, I am not saying it isn't, but it isn't being advertised as it either. And there is no information on specific links between processors directly, the Power 4(+) has three dedicated buses to connect to other processors in the package, there is nothing to suggest the 970 has one at all.
The only way I can make sense of it is if the 970's companion chip has a bus for direct connection to other 970 companion chips. That could be ApplePI (eWeek) or HyperTransport (CNET) or - heck - both, if ApplePI is a protocol.
I don't think that's out of the question at all. It's probably one of the more elegant and efficient ways to handle the sort of grunt work that can cripple multiprocessor efficiency (such as keeping the caches coherent, which in plain English means making sure that every CPU is operating on the most current data). It ensures that the memory controller doesn't become any more of a Grand Central Station than it will already be if it has a robust DMA engine on board.
Developers. Free books,.. They need to get the "developers! developers! developers!" excited ... Of course it wouldn't hurt if they passed out a few new 15" AlBooks. .
Developers edition 970 Powerbooks under every seat would have the whole house doing the 'monkey dance'.
My prediction is there will be 970 Powerbooks for any developer that wants one at developers pricing (not under every seat).
The only way I can make sense of it is if the 970's companion chip has a bus for direct connection to other 970 companion chips. That could be ApplePI (eWeek) or HyperTransport (CNET) or - heck - both, if ApplePI is a protocol.
I don't think that's out of the question at all. It's probably one of the more elegant and efficient ways to handle the sort of grunt work that can cripple multiprocessor efficiency (such as keeping the caches coherent, which in plain English means making sure that every CPU is operating on the most current data). It ensures that the memory controller doesn't become any more of a Grand Central Station than it will already be if it has a robust DMA engine on board.
No way. Having the memory controller chip with both processor busses connected to it is the most efficient method (in this instance). It can then also provide a large shared L3 cache (even out of embedded DRAM would be fine). The logic for detecting coherency issues, i.e is data dirty or not, benefits from being in one place and not having to compare notes with another chip.
If I were Apple (I know, I know, I'm not), I would design a very small dedicated memory controller chip that acted like a router, it ensures the requested data gets to the correct CPU OR peripherial chip. By making the chip as small as possible you could leave room on board the chip for some kind of cache, even if only as buffering. I would design the chip the same for uni- or dual- processor operation and have a high speed HT link between it and the rest of the system. And I would buy the chip that supplied PCI, AGP, ethernet, FireWire, USB (2), blah blah blah off of someone else (nVidia?) and concentrate my resources on uniqueness.
But they specifically talk about between processors, and we just don't know enough about the chip to do anything better than guess
Comments
Originally posted by Ensign Pulver
According to Loop Rumors:
"We know internally that Apple has been replacing the acronym WWDC with the phrase "We Will Delight Crowds."
Crowds of developers or crowds of consumers?
Developers. Free books, answer their questions, insight into Panther frameworks etc. They need to get the "developers! developers! developers!" excited about the future of programming for the OS X platform. Of course it wouldn't hurt if they passed out a few new 15" AlBooks.
Yeah they have to do something big to match MS...
...So Phil Schiller is a given.
***Drum roll***
Originally posted by MacUsers
I have all those steve ballmer videos from his microsoft presentations, that guy really freaked me out, i scared my dad with them too
Ouch.....don't make me remember that monkey dance
Originally posted by Leonis
Ouch.....don't make me remember that monkey dance
C'mon, it was fun, but anti-perspirant would help a bit....
Originally posted by piwozniak
C'mon, it was fun, but anti-perspirant would help a bit....
Originally posted by Marcus
Awesome!!!
"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.
It may also discuss plans to adopt IBM's PowerPC 970 processor, sources have suggested. The PowerPC 970 can handle 32-bit software--found on most desktops--and 64-bit software, which is found on high-end servers. Among the benefits of 64-bit computers is that they can take advantage of far more memory than 32-bit machines."
CNET: Fifty lemurs banging on keyboards.
Originally posted by Ensign Pulver
Cnet confirms Hypertransport at WWDC, hints at 970.
"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.
It may also discuss plans to adopt IBM's PowerPC 970 processor, sources have suggested. The PowerPC 970 can handle 32-bit software--found on most desktops--and 64-bit software, which is found on high-end servers. Among the benefits of 64-bit computers is that they can take advantage of far more memory than 32-bit machines."
Well, I think they got the details wrong. Do we know if the 970 has HT buses (even a variant?). HT on the motherboard makes sence in the context of connecting stuff to the memory controller, i.e. memory controller to an auxillary controller instead of using PCI. The processor to memory controller link could be HT, I am not saying it isn't, but it isn't being advertised as it either. And there is no information on specific links between processors directly, the Power 4(+) has three dedicated buses to connect to other processors in the package, there is nothing to suggest the 970 has one at all.
I don't think that's out of the question at all. It's probably one of the more elegant and efficient ways to handle the sort of grunt work that can cripple multiprocessor efficiency (such as keeping the caches coherent, which in plain English means making sure that every CPU is operating on the most current data). It ensures that the memory controller doesn't become any more of a Grand Central Station than it will already be if it has a robust DMA engine on board.
Originally posted by - J B 7 2 -
Developers. Free books,.. They need to get the "developers! developers! developers!" excited ... Of course it wouldn't hurt if they passed out a few new 15" AlBooks.
Developers edition 970 Powerbooks under every seat would have the whole house doing the 'monkey dance'.
My prediction is there will be 970 Powerbooks for any developer that wants one at developers pricing (not under every seat).
if i saw a dev. with one at a startbucks i would mug him.
Originally posted by Amorph
The only way I can make sense of it is if the 970's companion chip has a bus for direct connection to other 970 companion chips. That could be ApplePI (eWeek) or HyperTransport (CNET) or - heck - both, if ApplePI is a protocol.
I don't think that's out of the question at all. It's probably one of the more elegant and efficient ways to handle the sort of grunt work that can cripple multiprocessor efficiency (such as keeping the caches coherent, which in plain English means making sure that every CPU is operating on the most current data). It ensures that the memory controller doesn't become any more of a Grand Central Station than it will already be if it has a robust DMA engine on board.
No way. Having the memory controller chip with both processor busses connected to it is the most efficient method (in this instance). It can then also provide a large shared L3 cache (even out of embedded DRAM would be fine). The logic for detecting coherency issues, i.e is data dirty or not, benefits from being in one place and not having to compare notes with another chip.
If I were Apple (I know, I know, I'm not), I would design a very small dedicated memory controller chip that acted like a router, it ensures the requested data gets to the correct CPU OR peripherial chip. By making the chip as small as possible you could leave room on board the chip for some kind of cache, even if only as buffering. I would design the chip the same for uni- or dual- processor operation and have a high speed HT link between it and the rest of the system. And I would buy the chip that supplied PCI, AGP, ethernet, FireWire, USB (2), blah blah blah off of someone else (nVidia?) and concentrate my resources on uniqueness.
But they specifically talk about between processors, and we just don't know enough about the chip to do anything better than guess
Originally posted by Marcus
LOL! That's awesome. Maybe you should add a slider for "Sycophantic groveling to Bill Gates", too!