MacWorld in New York - 2002 is Apple's year

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  • Reply 121 of 619
    screedscreed Posts: 1,077member
    I took this:

    <strong>And rumor is that e500 core will soon be joined by another high performance core.

    </strong>

    to be a reference to the previous comment about collaboration with another company.



    Another core? A different core?! <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />



    Screed ...mayhaps I'm reading this incorrectly.
  • Reply 122 of 619
    "Another core? A different core?! "



    Different? And what would that 'other' and 'different' core do?



    In effect, Apple can lego build their ripost to Itanic 2 and Sledgehammer?



    Dorsal, are you saying that the e500 is similar in performance to the G4 bar the fact it is 64 bit? Extra integer? No extra fpu units? The altivec? No 256 bit version? Will its frequency start at the oft stated 2 gighz?



    So...the way forward is to increase frequency? And maybe stick two of them together...dual core?



    Sounds exciting but...with a note of caution on a same mhz performance. But if it starts at 2 gig then...that offsets that..? Can 7 stage pipeline stretch to 2 gighz frequency? The Hammer is doing better on same frequency...up to 40%!



    Modularity. So. It's looking like San Fran if the e500 is sampling now?



    Lemon Bon Bon <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />



    [ 06-17-2002: Message edited by: Lemon Bon Bon ]</p>
  • Reply 123 of 619
    jerombajeromba Posts: 357member
    This is what i fond about the e500 core on the motorola web site:

    Developper Forum July 21-24, 2002

    Motorola and IBM have announced the embedded version of the PowerPC architecture (Book E), and implementations are beginning to emerge. This session will address the impact on user applications and real-time operating systems, and the advantages of migrating to Book E. These issues and others about the coming transition will be answered by the designer of and principal contributor to the PowerPC Programming Environments Manual.



    Interesting...
  • Reply 124 of 619
    jerombajeromba Posts: 357member
    the e500 can be dual core (maybe quad, octo?)

    There is a diagram on motorola web site. Look for the MPC8540FACT.pdf

    That diagram shows that each core has in own bus memory ! If we keep in mind that the e500 core is 600-1000 Mhz, we can have this:

    1.2 / 2.0 / 2.4 / 4.0 Ghz WOW! (just for dual and quad).



    [ 06-17-2002: Message edited by: jeromba ]</p>
  • Reply 125 of 619
    jcgjcg Posts: 777member
    [quote]Originally posted by jeromba:

    <strong>the e500 can be dual core (maybe quad, octo?)

    There is a diagram on motorola web site. Look for the MPC8540FACT.pdf

    That diagram shows that each core has in own bus memory ! If we keep in mind that the e500 core is 600-1000 Mhz, we can have this:

    1.2 / 2.0 / 2.4 / 4.0 Ghz WOW! (just for dual and quad).



    [ 06-17-2002: Message edited by: jeromba ]</strong><hr></blockquote>



    If myy understanding of multi-core chips is correct, they are basically a MP design on one die. You would have a 600 mhz-1 Ghz for all of those chips, just like you have a Dual 1 Ghz MP tower, not a 2 Ghz tower now.
  • Reply 126 of 619
    jerombajeromba Posts: 357member
    yes sorry you're right but that's the name of it that do me wrong... e500 core...

    some pics to clear some minds:







    [ 06-17-2002: Message edited by: jeromba ]</p>
  • Reply 127 of 619
    daveleedavelee Posts: 245member
    So...



    Dorsal posts with what is a reasonably pragmatic, reasonably expected G4 system at NY.



    Then he goes and spoils it by posting some desirable G5 snippet. With no clue about timeframe.



    Drat.
  • Reply 128 of 619
    stevessteves Posts: 108member
    Just for fun, I'll add my 2 cents to the topics in this thread.



    Dorsal



    I remain neutral on my opinion of his actual knowledge of future Apple products. All I know is his past posts have included a range of Mobos for his company to review. When he's correct on one of his vague predictions, people begin the chant... Dorsal, Dorsal... Don't get me wrong, I enjoy reading his posts as much as the next person. It's just that I've seen a wide range of products he supposedly tested. These wide range of motherboards also seem to reflect what has been discussed as possibilities anyway. My point - though his posts are generally interesting, I've seen nothing substantial to make me believe he truly has inside information. If his prediction of Apple working with another company (such as nVidia -N Force ), then I might start to take his posts more seriously. Until then, it's sheer entertainment for me.



    Workstation graphics



    The difference between high end graphics cards (like Oxygen) and high end consumer cards (nVidia Geforce 4 Ti) are diminishing very quickly. That is, the consumer cards are advancing at a much faster rate. The main difference used to be the much larger amount of texture memory and the onboard TC&L engines, etc.



    Also, someone posted that games use something like 10,000 polygons per scene and pro scenes use something like 100,000 polygons. The thing is, the newer game engines are using polygon counts in the 100,000 range. The older Quake 3 and UT used closer to 10,000 polygons per scene. However, I read an article that was talking about the game engine in Unreal 2 (and UT 2003). One tree in the scene used more polygons than an entire scene in the previous generation game engine. The same is true with engine used in the upcoming Doom 3.



    Jobs/Apple Doomed



    Finally, those that think Jobs is going to have objects thrown at him for coming out with "only" dual 1.2 GHZ G4s, etc. have obviously never been to a Macworld event. RDF is in full force. It even works on PC types (trust me, I've seen it). Seriously though, this type of nonsense is said both before and after just about every Macworld event. Apple is not doomed for being behind in MHZ. Anyone that understands the fundamental difference between PCs and Macs knows this. Companies don't just flip flop on hardware platforms based on what someone else is doing. If Apple were to truly stagnate for any long period of time, then, they might be in trouble. However, even during the 18 month G4 stagnation, Apple was able to hold out by offering multiple processors, etc.



    Steve
  • Reply 129 of 619
    The other 'core': IBM's 'Cell' Project.



    TING5
  • Reply 130 of 619
    addisonaddison Posts: 1,185member
    With the kind of power described here, it is obvious that Apple will have a replacement for powermacs but that they might leap in price. That would leave room for an SE iMac with either a 17 or 19" screen to fill the low end of the pro-market. If the chip is really that modular then it will allow Apple to introduce a "SuperMac" with maybe 4 or 8 cores to take the market straight out from under SGI's feet.







    [ 06-17-2002: Message edited by: Addison ]</p>
  • Reply 131 of 619
    screedscreed Posts: 1,077member
    [quote]Originally posted by There is no g5:

    <strong>The other 'core': IBM's 'Cell' Project.



    TING5</strong><hr></blockquote>



    <a href="http://www.eetimes.com/story/OEG20010313S0113"; target="_blank">IBM, Sony, Toshiba team on processor architecture for broadband</a>



    [quote]<strong>Sony Computer Entertainment Inc. (SCEI), IBM Corp. and Toshiba Corp. announced a major partnership aimed at creating a processor architecture ? code-named Cell ? that will be optimized for multimedia packet processing over the broadband network.</strong><hr></blockquote>



    <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />



    [quote]<strong>The goal is to have the first Cell products ready by 2004 or 2005, based on a "10S" 100-nm (0.10-micron) process technology that moves to commercial production early in 2003 at IBM.</strong><hr></blockquote>



    <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />



    Screed
  • Reply 132 of 619
    bodhibodhi Posts: 1,424member
    Keep in mind that everything Dorsal said is publiclly available. Perfect example is that diagram from Motorola's site.



    Not discounting what Dorsal is saying...just trying to keep things in perspective.
  • Reply 133 of 619
    haderachhaderach Posts: 32member
    <strong>There will be an e500 core based desktop processor based on Apple's requirements. The e500 core is a 7 stage pipeline design very similar to the 7455 core (they both get about 2300MIPS). The execution units are very similar, in quantity and performance.</strong>



    Well, I would say that the e500 and the 7455 core are "similar", although not "very similar"... Did you really get MPC7500 prototypes as you reported a few months ago? I have only seen block diagrams and text so far, and I couldn't find anyone who could confirm the 7500 is really sampling. Maybe we should note that the e500 (as I know it) is a pure 32 bit design, 64 bits will be introduced with an e500 successor.



    <strong>There is an Altivec add on built for the e500.</strong>



    As far as I can say Altivec has been implemented as APU, connected to the e500 via OCEAN. It seems the same is true for the FPU, it looks like the FPU is not part of the e500 itself. I hope this doesn't affect the performance in a negative way.



    <strong>Apple's implimentation has dual RIO ports and a memory controller. The interconnect is the e500 native OCEAN and this is a wide/fast bus, only for on die interconnects.</strong>



    On the block diagrams I saw the memory controller was the same as the 8540 controller, this means 266/333 Mhz DDR on a 133/166 Mhz Bus.



    <strong>Multiprocessing in handled via RapidIO's 16 bit variant. It connects to a RapidIO hub (RIOH) that serves as the central hub for various RIO devices, such as peripheral controllers, PCI controllers, other PowerPC processors, network processors, etc. The hub controls the bit width and frequency, and this is determined by the distance from the hub (trace length). If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency. To connect to a PCI controller you can keep the 16 bit wide port or if pin out is an issue you may need to drop it to 8 bit and run it at a lower frequency such as 500MHz. RIO is capable of over 7GBps bandwidth running at 16bit.</strong>



    This will rock, hehe...



    <strong>The beauty of Book E is the modularity. The way Motorola designed it was so a customer can pick and choose the components.</strong>



    Right, customers can even design their own circuits an connect them as APUs via the OCEAN crossbar switch.



    <strong>this was as long as the customer had the money to spend as I imagine this is not an inexpensive proposistion. But it is an ideal solution for Apple. They can choose the size of the L2 cache, number of e500 cores, kind of memory controllers available, if they wanted a PCI controller also embedded...</strong>



    Ethernet is also available as component, although I do not believe this will be implemented directly into the CPU.



    <strong>And rumor is that e500 core will soon be joined by another high performance core.</strong>



    As far as I know they're working on a high performance 64 bit version of the core, but I have no information about when this could be ready (I even can't say when the e500 based 7500 will be ready, I guess Dorsal can tell us more about possible release dates).
  • Reply 134 of 619
    naepstnnaepstn Posts: 78member
    [quote]Originally posted by SteveS:

    <strong>Workstation graphics



    The difference between high end graphics cards (like Oxygen) and high end consumer cards (nVidia Geforce 4 Ti) are diminishing very quickly. That is, the consumer cards are advancing at a much faster rate. The main difference used to be the much larger amount of texture memory and the onboard TC&L engines, etc.

    </strong><hr></blockquote>



    From what I have heard, a large part of the difference between high-end workstation graphics cards and the consumer versions comes down to the drivers. Pro cards have their drivers certified by a third-party QC certification entity for things like CAD accuracy need to be very free of bugs. Some cards' drivers are specially tuned for certain applications. An example of this is the ATI Mobility Fire GL? 7800 (used in the IBM A-series mobile workstations), which is in fact the same card as the Radeon Mobility 7500, but with certified drivers, optimized for optimum OpenGL performance. Presumably, this is at the expense of performance in other areas, which is not suitable for consumer/prosumer use (including 2D graphics).



    As for the use/need for 64-bit processors, while I agree that it is unnecessary for most people, it is crucial for marketing and market-share. Apple can once again claim to be leading in hardware innovation, and if it results in leading-edge benchmarks in high-end database and scientific computing, then IT-folks will have a new respect for Apple products and will be less likely to spout crap about Apple products being underpowered. It's hard to make that argument when someone can retort with high-end computing benchmarks.
  • Reply 135 of 619
    programmerprogrammer Posts: 3,467member
    [quote]Originally posted by haderach:

    <strong>

    Well, I would say that the e500 and the 7455 core are "similar", although not "very similar"... Did you really get MPC7500 prototypes as you reported a few months ago? I have only seen block diagrams and text so far, and I couldn't find anyone who could confirm the 7500 is really sampling. Maybe we should note that the e500 (as I know it) is a pure 32 bit design, 64 bits will be introduced with an e500 successor.

    </strong><hr></blockquote>



    Hmmm... you're right. For some reason I thought that the e500 was 64-bit, but I can't find anything to indicate that it is. It makes sense then that the new core will be the 64-bit one. I wonder if IBM is designing the 64-bit core? That would be odd, wouldn't it...



    The OCEAN cross-bar is capable of 128 Gb/sec (=16 GB/sec), which doesn't seem all that fast... but its on-chip so its speed will be a function of clock rate and the highest they mention is 1 GHz. At 2 GHz it'll be twice as fast. Its also not clear if that is the point-to-point speed, or the overall net throughput through the entire cross-bar. It should be fast enough for now, however. It sounds like it could let Apple put multiple FPUs and VPUs onto the chip. This kind of an architecture should really suit Apple well since it can custom build its own designs.



    A multi-core design would have more than one e500 core connected via the OCEAN switch. They'd probably share the on-chip bus/cache/memory controller.



    I doubt we'll see it this year though (although I'd love to be surprised on this one!).
  • Reply 136 of 619
    [quote]Originally posted by Jonathan Brisby:

    <strong> In this way we will create a new bread of human,</strong><hr></blockquote>



    Soylent Green ?
  • Reply 137 of 619
    [quote]Originally posted by Dorsal M:

    <strong> If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency.</strong><hr></blockquote>



    Let's look at that again.



    [quote]Originally posted by Dorsal M:

    <strong> If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency.</strong><hr></blockquote>



    Does this mean a 2GHz chip? It can't! Can it?
  • Reply 138 of 619
    [quote]Originally posted by BobtheTomato:

    <strong>Soylent Green ?</strong><hr></blockquote>



    "You gotta eat all the old people! Eat all the old people. . ."
  • Reply 139 of 619
    bigcbigc Posts: 1,224member
    hmmm... Digital dna
  • Reply 139 of 619
    programmerprogrammer Posts: 3,467member
    [quote]Originally posted by DaveLee:

    <strong>So...



    Dorsal posts with what is a reasonably pragmatic, reasonably expected G4 system at NY.



    Then he goes and spoils it by posting some desirable G5 snippet. With no clue about timeframe.



    Drat.</strong><hr></blockquote>





    I don't understand why this "spoils" it?
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