Why you would want to elimenate multi threading is beyond me. Multithreading is what makes this sort of machine feasable. Sure a CPU bound process will perform poorly but how much software out there is really that bound up. Lets face it the OS would benefit, just about every application written in the last few years would benefit, people who run multiple programs at anyone time will beenfit. The only people who would loose would be those running CPU bound programs that don;t multi thread well and don't make much use of system resources. Sure there are some programs like this but not many.
Alright who really cares about bench marks anyways, this is an Apple forum right. Really Apple has suffered for years with poorly performing machines, when it comes to bench marks, whats to stop this. Plus any reasonable marketing idiot will come up with multi thread benchmarks that show the potential of this machine. Further if marketed towards resonably intelligent customers 4X SMP will be a big draw in and of itself. It would also be reasonable to assume that bandwidth and VMX issues would be addressed so the 700 MHz performance would exceed the current results that come from the 750 series.
Please read what I said one more time, I didn't say I want to eliminate multithreading just like that, but the need for it. That's the only way I can find a machine like this feasible. If all the cores could chew at the same thread, it would indeed be wonderful.
As for benchmarks, and poor-performing machines. Why do you think Apple's market share has been shrinking the last years? It's because they haven't afforded deals that have been compelling enough for the general customer. No, I don't want to turn this into yet another market share thread, but this is the very essence. If Apple offered machines that screamed bang for the buck, high performance, and all the sweet juice, market share would go up.
Benchmarks provides information about exactly this. And as you say, Apple's machines have not been very speedy, and customers knows this. How do they know? Just by looking at the clock-frequency? Yes, some do that, but a portion of the market more than large enough to be talked about do care a lot about benchmarks. They don't sell iMacs, Powerbooks, and mid/low-end hardware to people that's obsessed with benchmarks. And neither do they sell much to potential buyers that consults with these benchmark-caring, often enthusiasts.
You can't keep targeting reasonable intelligent customers like this, it's exactly what Apple's been doing for years, and it doesn't work satisfyingly. Apple wants to grow.
So for a 4x SMP-machine at 700MHz, you gotta have a pretty convincing and compelling offer to make. Heavy-ass multithreading is fine, fine for some. A ton of code has to be rewritten, and I have my doubts that programmers are willing to do that just because Apples one laptop-line is having 4x SMP.
It's good we're at least agreeing about the possible reality of this machine
This is a logical view, so L2 here could be on the same die as the cores or on the MCM (which is the next best thing). I'm also not entirely sure whether it makes sense to have a shared external cache. Some sort of control logic would be necessary, obviously. So the big L2 could be two caches, really, if that would make it easier to handle coherency issues. I'm getting in over my head here, so bear with me.
I too would be shocked if IBM didn't go with at least two fast caches per core. It seems to me that regressing to a G2 design is not part of the idea.
(The little grey bits in the image are the prefetch caches.)
Well if you can come up with a technology that eliminates the need for multithreading in systesm and software you would be a very wealthy man or woman!
Multithreading is what makes this machine feasable, it isn't the other way around. If the 4 processors cannnot be doing usefull work at the same time, then you will end up with very poor performance. Multihtreaded operating systems and applications software allow this to happen.
All cores chewing on the smae thread would not be wonderfull at all. That would mean that you did something 4 times that only needed to be done once. What you would want is an application that generated 4 or more threads to get its work done, then the system could come into its own. Granted some applications do not multithread easly and would suffer realative to those that do. But even with single threaded applications the overall results will be better than the same program on a single processor machine.
Apples market share has shrunk for a number of reasons performance has only been a small part of that. To go into this would mess up this thread so I won't.
It would be a total shame if Apple ever thought that its market was the "benchmark-caring" crowd. Apple has several markets and one of those is high performance. There are several ways to judge the performance of a machine, I'm sure Apple can find the proper way to present this performance.
Frankly I don't know if Apple wants to grow, I think Apple is Steves baby and he wants to see it healthy. One way to keep a company like Apple healthy is to innovate, history has shown us that Apple is healthest when she innovates. The other thing that Steve and the stockholders want is $$$$$$$$$$$. Money is what its all about in the end, unhappy shareholders can ruin a company in a blink of an eye. An innovative laptop that can demonstrate leading edge performance, in a number of different metrics, can bring in $$$$$$$$$$$$.
You have a fundamental misunderstanding of the software technologies that have been implemented recently. First a large portion of of the Software base that can benefit from being SMP aware already is. The more hardware that Apple sells that is SMP just provides even more programmers the incentive to go the SMP route. Almost all of the professonal PPC hardware that Apple has sold in the last few years has been SMP. Frankly they have been having a hard time even moving the single processor G5's, thus the recent marketing changes. The software base is there to take advantage of this mystery machine and has been for some time. Second; the state of the software base is only part of the equation. OS/X is a modern operating system many parts of which are multithreaded. Even if anyone specific applications program can not take advantage of the SMP facilites the operating system can. So you still come out ahead. Third; many of the application libaries are multithreaded also. So our poor single thread application MAY still make use of multithreading even if it wasn't written to do so itself.
Its not that I'm disagreeing with you, it is more a question of some of your reasoning being wrong. Yeah I understand that some applications wouldn't give the best results on this type of machine, but overall performance could be a fanatastic in the context of a laptop. Frankly we don't even know what that 700 MHz processor will be equal to, there is nothing to keep IBM from actually improving its performance.
What is compelling will differ between users, but the one advantage Apple had for a long time was run time on battery. If Apple can get back to excellent run times and extrodinary user experience then they have a good chance of success.
Thanks
dave
Quote:
Originally posted by Zapchud
Please read what I said one more time, I didn't say I want to eliminate multithreading just like that, but the need for it. That's the only way I can find a machine like this feasible. If all the cores could chew at the same thread, it would indeed be wonderful.
As for benchmarks, and poor-performing machines. Why do you think Apple's market share has been shrinking the last years? It's because they haven't afforded deals that have been compelling enough for the general customer. No, I don't want to turn this into yet another market share thread, but this is the very essence. If Apple offered machines that screamed bang for the buck, high performance, and all the sweet juice, market share would go up.
Benchmarks provides information about exactly this. And as you say, Apple's machines have not been very speedy, and customers knows this. How do they know? Just by looking at the clock-frequency? Yes, some do that, but a portion of the market more than large enough to be talked about do care a lot about benchmarks. They don't sell iMacs, Powerbooks, and mid/low-end hardware to people that's obsessed with benchmarks. And neither do they sell much to potential buyers that consults with these benchmark-caring, often enthusiasts.
You can't keep targeting reasonable intelligent customers like this, it's exactly what Apple's been doing for years, and it doesn't work satisfyingly. Apple wants to grow.
So for a 4x SMP-machine at 700MHz, you gotta have a pretty convincing and compelling offer to make. Heavy-ass multithreading is fine, fine for some. A ton of code has to be rewritten, and I have my doubts that programmers are willing to do that just because Apples one laptop-line is having 4x SMP.
It's good we're at least agreeing about the possible reality of this machine
IBM's vlc compiler has auto-threading capabilities. I have no idea how well they do. It's a given that a trained programmer could do better, but the fact that a trained programmer could write better assembly code hasn't stopped the compiler from taking off. If threading by compiler option works well enough it'll be widely adopted (it'll really need to make it into gcc before this happens, though). Cocoa, being a set of frameworks, is very well set up to spawn threads itself as needed, giving all Cocoa apps some of the benefit automagically. And, of course, NSThread makes manual threading as intuitive as it's ever going to be in languages designed before threads existed.
This seems to me to be work in the general direction of Cell. IBM certainly has an interest in making parallelism as easy as possible, because they're going this way no matter what Apple does. It's not running the same thread across multiple CPUs, but it's about as close as you can get.
programmer will not rewrite software for just a laptop, but this is the general direction in which mac architecture will move, and apple will make that clear to developer
If that's so, no L2 cache will be a major performance-hit.
The G4 (7400 & 7410) had no L2 cache as such, just 1MB of what we now call L3 cache.
Maybe this thing will use a combined memory/L3 controller similar to the POWER line (much scaled down, of course).
Look at it this way, the PowerPC 970 has L2 cache like the POWER4, but without the memory/L3 controller (for cost/performance reasons). Now what if this has the L3 without the L2? It may make sense for an SoC design, where you'd try and limit the size of the silicon, to have L3 cache instead of, rather than in addition to, L2.
programmer will not rewrite software for just a laptop, but this is the general direction in which mac architecture will move, and apple will make that clear to developer
"general direction in which mac architecture will move," eh? which branch of mac architecture? will we similar multi-core (i.e., beyond 2 CPUs) configurations with the 980 (or any other future progression of the 970-range CPU)?
I like the comment about syntax
at the same time, though, I'm taking it all with a little crystal of sodium chloride...
sorry I meant the L2 cache is prefetch for the L3 cache.
The L3 cache is sufficient fast at 22.4GB/sec
the L1 cache is still 32/32
OK, this is the same design IBM's using in the POWER5. Good.
Another attempt, just because OmniGraffle is so much fun:
Even if the public unveiling is summer 2004, I'd expect WWDC to be heavily slanted toward SMP programming and threading, with perhaps some sooper seekrit sessions for big and important developers. The whole thing is NDA'd, and if the last WWDC was any indication, Mac devs have gotten a little better at keeping quiet.
Winter '04 is fair as an introduction, though. That's right at the deadline Steve said he wanted for a "G5 PowerBook," which is good enough.
Why you would want to elimenate multi threading is beyond me. Multithreading is what makes this sort of machine feasable.
Which is a rather significant strike against the 440 as it is not SMP compliant.
From the BlueGene/L Overview PDF:
Quote:
Since the 440 CPU core does not implement the necessary hardware to provide SMP support, the two cores are not L1 cache coherent. A lockbox is provided to allow coherent processor-to-processor communication.
I think Nr9 has conflated some things he didn't understand and maybe is making some guesses.
The 440 does not have FPUs. This functionality is added by the 440 FPU2 which integrates via the aux port. It is capable of a special version of SIMD that IBM describes as SIMOMD (Multiple Ops and Multiple Data) and this may be what leads Nr9 to speculate about VMX. Otherwise, IBM would have to fabricate a custom co-processor that incorporates VMX and a scalar FPU.
Add the fact that the 440's performance in the BlueGene/L prototype is only as spectacular as it is thanks to the 440 FPU2's ability to do 2 FMADs per cycle (or 4 FLOPSs -- a total of 8 FLOPs with both CPUs engaged) but is otherwise not very spectacular (7 stage pipeline with 3 exec units) and it's unlikely this is a direction that IBM and Apple would go for mobile computing. Especially not when process reductions and a bit of creative airflow engineering would provide more performance at less cost in engineering cycles.
the multiprocessing is distributd via a message passing interface.
this is main reason for delay in OS X.
Which makes very, very good sense. New DragonflyBSD-esque kernel in Mac OS X 10.4. If that happens btw, I told you so in advance (I first posted a thread about it months and months ago). I hope Jordan Hubbard is working his butt off!
If it's going to have 4 processors it had better be.
Quote:
[/b]the multiprocessing is distributd via a message passing interface.
this is main reason for delay in OS X.[/b]
Oh, I see. That's why we haven't seen Mac OS X ship yet. And here I thought I was just being delusional.
Please. You don't rewrite your OS and tell all your developers they have to rewrite their software to support a highly parallel achitecture just because you want a low power laptop.
Quote:
you are wrong if you think cooling engineering will let a 970 go in a powerbook. this is precisely the reason apple is going to this direction.
the 970 is very hot and suck lot power
Yes, this is true. At high speeds, at the current process size.
Quote:
if you add exotic form of cooling, you are likely to have very little battery life.
Which is why you implement things like speed step and look into solutions like cooligy's.
Quote:
as for VMX and FPU, you can guess what the solution is. half of work already have been done.
I don't think you get it.
The PPC970 has 1 SIMD (VMX), 1 scalar Integer and two scalar FPUs (and other assorted goodies, but lets not go there just yet) which is a nice blend of SIMD and scalar functionality. This makes it a good general purpose CPU.
What you are proposing would have 1 scalar integer, 1 scalar FPU and 1 SIMD. Not very well balanced. Four of them would just mean you're compounding the imbalance by a factor of four.
it's unlikely this is a direction that IBM and Apple would go for mobile computing. Especially not when process reductions and a bit of creative airflow engineering would provide more performance at less cost in engineering cycles.
You are dead wrong, my friend. You can keep coming up with "clever hacks" to keep big CPUs like the 970 cool in PowerBooks, keep refining the enclosure, but eventually you have to bite the bullet.
What is biting the bullet? Biting the bullet is recognising that CPUs can't keep getting hotter and using more power indefinitely, and finding a new way. That new way is increasing-parallel computing using small, extensible and fast chips like the 440 and the Crusoe.
Please. You don't rewrite your OS and tell all your developers they have to rewrite their software to support a highly parallel achitecture just because you want a low power laptop.
What you are proposing would have 1 scalar integer, 1 scalar FPU and 1 SIMD. Not very well balanced. Four of them would just mean you're compounding the imbalance by a factor of four.
Wrong again. Not only will ALL Macs look like this in 5 to 10 years, but Apple has told developers to re-optimize (NOT rewrite - existing software would still work but slower - have a look at DrangonFlyBSD sometime) their software over and over again, with each leap forward in computing architecture. Apple is the only desktop computer maker that can and does succeed in this too.
Comments
Originally posted by wizard69
Why you would want to elimenate multi threading is beyond me. Multithreading is what makes this sort of machine feasable. Sure a CPU bound process will perform poorly but how much software out there is really that bound up. Lets face it the OS would benefit, just about every application written in the last few years would benefit, people who run multiple programs at anyone time will beenfit. The only people who would loose would be those running CPU bound programs that don;t multi thread well and don't make much use of system resources. Sure there are some programs like this but not many.
Alright who really cares about bench marks anyways, this is an Apple forum right. Really Apple has suffered for years with poorly performing machines, when it comes to bench marks, whats to stop this. Plus any reasonable marketing idiot will come up with multi thread benchmarks that show the potential of this machine. Further if marketed towards resonably intelligent customers 4X SMP will be a big draw in and of itself. It would also be reasonable to assume that bandwidth and VMX issues would be addressed so the 700 MHz performance would exceed the current results that come from the 750 series.
Please read what I said one more time, I didn't say I want to eliminate multithreading just like that, but the need for it. That's the only way I can find a machine like this feasible. If all the cores could chew at the same thread, it would indeed be wonderful.
As for benchmarks, and poor-performing machines. Why do you think Apple's market share has been shrinking the last years? It's because they haven't afforded deals that have been compelling enough for the general customer. No, I don't want to turn this into yet another market share thread, but this is the very essence. If Apple offered machines that screamed bang for the buck, high performance, and all the sweet juice, market share would go up.
Benchmarks provides information about exactly this. And as you say, Apple's machines have not been very speedy, and customers knows this. How do they know? Just by looking at the clock-frequency? Yes, some do that, but a portion of the market more than large enough to be talked about do care a lot about benchmarks. They don't sell iMacs, Powerbooks, and mid/low-end hardware to people that's obsessed with benchmarks. And neither do they sell much to potential buyers that consults with these benchmark-caring, often enthusiasts.
You can't keep targeting reasonable intelligent customers like this, it's exactly what Apple's been doing for years, and it doesn't work satisfyingly. Apple wants to grow.
So for a 4x SMP-machine at 700MHz, you gotta have a pretty convincing and compelling offer to make. Heavy-ass multithreading is fine, fine for some. A ton of code has to be rewritten, and I have my doubts that programmers are willing to do that just because Apples one laptop-line is having 4x SMP.
It's good we're at least agreeing about the possible reality of this machine
Originally posted by Nr9
heh everyone is trolling on battlefront to some degree, whether they kno it or not.
i dont think we need to discuss that
anyway, the processor has no real L2 cache but a 2KB prefetch for the L1.
And may I ask how large this L1 cache is? 64kB, as the current 440 core?
If that's so, no L2 cache will be a major performance-hit.
This is a logical view, so L2 here could be on the same die as the cores or on the MCM (which is the next best thing). I'm also not entirely sure whether it makes sense to have a shared external cache. Some sort of control logic would be necessary, obviously. So the big L2 could be two caches, really, if that would make it easier to handle coherency issues. I'm getting in over my head here, so bear with me.
I too would be shocked if IBM didn't go with at least two fast caches per core. It seems to me that regressing to a G2 design is not part of the idea.
(The little grey bits in the image are the prefetch caches.)
Multithreading is what makes this machine feasable, it isn't the other way around. If the 4 processors cannnot be doing usefull work at the same time, then you will end up with very poor performance. Multihtreaded operating systems and applications software allow this to happen.
All cores chewing on the smae thread would not be wonderfull at all. That would mean that you did something 4 times that only needed to be done once. What you would want is an application that generated 4 or more threads to get its work done, then the system could come into its own. Granted some applications do not multithread easly and would suffer realative to those that do. But even with single threaded applications the overall results will be better than the same program on a single processor machine.
Apples market share has shrunk for a number of reasons performance has only been a small part of that. To go into this would mess up this thread so I won't.
It would be a total shame if Apple ever thought that its market was the "benchmark-caring" crowd. Apple has several markets and one of those is high performance. There are several ways to judge the performance of a machine, I'm sure Apple can find the proper way to present this performance.
Frankly I don't know if Apple wants to grow, I think Apple is Steves baby and he wants to see it healthy. One way to keep a company like Apple healthy is to innovate, history has shown us that Apple is healthest when she innovates. The other thing that Steve and the stockholders want is $$$$$$$$$$$. Money is what its all about in the end, unhappy shareholders can ruin a company in a blink of an eye. An innovative laptop that can demonstrate leading edge performance, in a number of different metrics, can bring in $$$$$$$$$$$$.
You have a fundamental misunderstanding of the software technologies that have been implemented recently. First a large portion of of the Software base that can benefit from being SMP aware already is. The more hardware that Apple sells that is SMP just provides even more programmers the incentive to go the SMP route. Almost all of the professonal PPC hardware that Apple has sold in the last few years has been SMP. Frankly they have been having a hard time even moving the single processor G5's, thus the recent marketing changes. The software base is there to take advantage of this mystery machine and has been for some time. Second; the state of the software base is only part of the equation. OS/X is a modern operating system many parts of which are multithreaded. Even if anyone specific applications program can not take advantage of the SMP facilites the operating system can. So you still come out ahead. Third; many of the application libaries are multithreaded also. So our poor single thread application MAY still make use of multithreading even if it wasn't written to do so itself.
Its not that I'm disagreeing with you, it is more a question of some of your reasoning being wrong. Yeah I understand that some applications wouldn't give the best results on this type of machine, but overall performance could be a fanatastic in the context of a laptop. Frankly we don't even know what that 700 MHz processor will be equal to, there is nothing to keep IBM from actually improving its performance.
What is compelling will differ between users, but the one advantage Apple had for a long time was run time on battery. If Apple can get back to excellent run times and extrodinary user experience then they have a good chance of success.
Thanks
dave
Originally posted by Zapchud
Please read what I said one more time, I didn't say I want to eliminate multithreading just like that, but the need for it. That's the only way I can find a machine like this feasible. If all the cores could chew at the same thread, it would indeed be wonderful.
As for benchmarks, and poor-performing machines. Why do you think Apple's market share has been shrinking the last years? It's because they haven't afforded deals that have been compelling enough for the general customer. No, I don't want to turn this into yet another market share thread, but this is the very essence. If Apple offered machines that screamed bang for the buck, high performance, and all the sweet juice, market share would go up.
Benchmarks provides information about exactly this. And as you say, Apple's machines have not been very speedy, and customers knows this. How do they know? Just by looking at the clock-frequency? Yes, some do that, but a portion of the market more than large enough to be talked about do care a lot about benchmarks. They don't sell iMacs, Powerbooks, and mid/low-end hardware to people that's obsessed with benchmarks. And neither do they sell much to potential buyers that consults with these benchmark-caring, often enthusiasts.
You can't keep targeting reasonable intelligent customers like this, it's exactly what Apple's been doing for years, and it doesn't work satisfyingly. Apple wants to grow.
So for a 4x SMP-machine at 700MHz, you gotta have a pretty convincing and compelling offer to make. Heavy-ass multithreading is fine, fine for some. A ton of code has to be rewritten, and I have my doubts that programmers are willing to do that just because Apples one laptop-line is having 4x SMP.
It's good we're at least agreeing about the possible reality of this machine
This seems to me to be work in the general direction of Cell. IBM certainly has an interest in making parallelism as easy as possible, because they're going this way no matter what Apple does. It's not running the same thread across multiple CPUs, but it's about as close as you can get.
the L1 cache is still 32/32
Originally posted by Henriok
And.. Amorph's and Barto's diagrams were very beautiful! I'm not worthy
I wouldn't call my diagram "beautiful". It had no fire, no energy, no nothing!
If you want diagrams that look good, all you need is OmniGraffle. Fantastic program, it can even replace PowerPoint.
Barto
Originally posted by Zapchud
If that's so, no L2 cache will be a major performance-hit.
The G4 (7400 & 7410) had no L2 cache as such, just 1MB of what we now call L3 cache.
Maybe this thing will use a combined memory/L3 controller similar to the POWER line (much scaled down, of course).
Look at it this way, the PowerPC 970 has L2 cache like the POWER4, but without the memory/L3 controller (for cost/performance reasons). Now what if this has the L3 without the L2? It may make sense for an SoC design, where you'd try and limit the size of the silicon, to have L3 cache instead of, rather than in addition to, L2.
Barto
it is the beauty of human language to remain coherent in the absence of strict syntax
we should take advantage of that. this is future of english.
Originally posted by Nr9
programmer will not rewrite software for just a laptop, but this is the general direction in which mac architecture will move, and apple will make that clear to developer
Anyone else thinking a WWDC introduction?
I like the comment about syntax
at the same time, though, I'm taking it all with a little crystal of sodium chloride...
Originally posted by Nr9
sorry I meant the L2 cache is prefetch for the L3 cache.
The L3 cache is sufficient fast at 22.4GB/sec
the L1 cache is still 32/32
OK, this is the same design IBM's using in the POWER5. Good.
Another attempt, just because OmniGraffle is so much fun:
Even if the public unveiling is summer 2004, I'd expect WWDC to be heavily slanted toward SMP programming and threading, with perhaps some sooper seekrit sessions for big and important developers. The whole thing is NDA'd, and if the last WWDC was any indication, Mac devs have gotten a little better at keeping quiet.
Winter '04 is fair as an introduction, though. That's right at the deadline Steve said he wanted for a "G5 PowerBook," which is good enough.
Originally posted by wizard69
Why you would want to elimenate multi threading is beyond me. Multithreading is what makes this sort of machine feasable.
Which is a rather significant strike against the 440 as it is not SMP compliant.
From the BlueGene/L Overview PDF:
Since the 440 CPU core does not implement the necessary hardware to provide SMP support, the two cores are not L1 cache coherent. A lockbox is provided to allow coherent processor-to-processor communication.
I think Nr9 has conflated some things he didn't understand and maybe is making some guesses.
The 440 does not have FPUs. This functionality is added by the 440 FPU2 which integrates via the aux port. It is capable of a special version of SIMD that IBM describes as SIMOMD (Multiple Ops and Multiple Data) and this may be what leads Nr9 to speculate about VMX. Otherwise, IBM would have to fabricate a custom co-processor that incorporates VMX and a scalar FPU.
Add the fact that the 440's performance in the BlueGene/L prototype is only as spectacular as it is thanks to the 440 FPU2's ability to do 2 FMADs per cycle (or 4 FLOPSs -- a total of 8 FLOPs with both CPUs engaged) but is otherwise not very spectacular (7 stage pipeline with 3 exec units) and it's unlikely this is a direction that IBM and Apple would go for mobile computing. Especially not when process reductions and a bit of creative airflow engineering would provide more performance at less cost in engineering cycles.
this powerbook g5 is obviously not SMP.
the multiprocessing is distributd via a message passing interface.
this is main reason for delay in OS X.
you are wrong if you think cooling engineering will let a 970 go in a powerbook. this is precisely the reason apple is going to this direction.
the 970 is very hot and suck lot power
if you add exotic form of cooling, you are likely to have very little battery life.
as for VMX and FPU, you can guess what the solution is. half of work already have been done.
Originally posted by Nr9
the multiprocessing is distributd via a message passing interface.
this is main reason for delay in OS X.
Which makes very, very good sense. New DragonflyBSD-esque kernel in Mac OS X 10.4. If that happens btw, I told you so in advance (I first posted a thread about it months and months ago). I hope Jordan Hubbard is working his butt off!
Barto
Originally posted by Nr9
tomb
this powerbook g5 is obviously not SMP.
If it's going to have 4 processors it had better be.
[/b]the multiprocessing is distributd via a message passing interface.
this is main reason for delay in OS X.[/b]
Oh, I see. That's why we haven't seen Mac OS X ship yet. And here I thought I was just being delusional.
Please. You don't rewrite your OS and tell all your developers they have to rewrite their software to support a highly parallel achitecture just because you want a low power laptop.
you are wrong if you think cooling engineering will let a 970 go in a powerbook. this is precisely the reason apple is going to this direction.
the 970 is very hot and suck lot power
Yes, this is true. At high speeds, at the current process size.
if you add exotic form of cooling, you are likely to have very little battery life.
Which is why you implement things like speed step and look into solutions like cooligy's.
as for VMX and FPU, you can guess what the solution is. half of work already have been done.
I don't think you get it.
The PPC970 has 1 SIMD (VMX), 1 scalar Integer and two scalar FPUs (and other assorted goodies, but lets not go there just yet) which is a nice blend of SIMD and scalar functionality. This makes it a good general purpose CPU.
What you are proposing would have 1 scalar integer, 1 scalar FPU and 1 SIMD. Not very well balanced. Four of them would just mean you're compounding the imbalance by a factor of four.
Originally posted by Tomb of the Unknown
it's unlikely this is a direction that IBM and Apple would go for mobile computing. Especially not when process reductions and a bit of creative airflow engineering would provide more performance at less cost in engineering cycles.
You are dead wrong, my friend. You can keep coming up with "clever hacks" to keep big CPUs like the 970 cool in PowerBooks, keep refining the enclosure, but eventually you have to bite the bullet.
What is biting the bullet? Biting the bullet is recognising that CPUs can't keep getting hotter and using more power indefinitely, and finding a new way. That new way is increasing-parallel computing using small, extensible and fast chips like the 440 and the Crusoe.
Barto
Originally posted by Tomb of the Unknown
Please. You don't rewrite your OS and tell all your developers they have to rewrite their software to support a highly parallel achitecture just because you want a low power laptop.
What you are proposing would have 1 scalar integer, 1 scalar FPU and 1 SIMD. Not very well balanced. Four of them would just mean you're compounding the imbalance by a factor of four.
Wrong again. Not only will ALL Macs look like this in 5 to 10 years, but Apple has told developers to re-optimize (NOT rewrite - existing software would still work but slower - have a look at DrangonFlyBSD sometime) their software over and over again, with each leap forward in computing architecture. Apple is the only desktop computer maker that can and does succeed in this too.
Barto