Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed. <hr></blockquote>
Gosh-- would Steve actually say that? He seems like such a nice, sweet boy.
In my office, managers want to say that all the time to Motorola, but we can't...
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
</strong><hr></blockquote>
Given that is correct, there is going to be a huge lacuna in not just the sale of PowerMacs but also in Apple's profits. Not to mention Motorola's lack of motivation re. research, as noted above. At most, they will have one more G4 upgrade in the pipeline - probably not with the front bus update expected by many here.
I foresee lowered profit expectations from Apple later today - and a corresponding fall in the price of their shares. Only comfort: they can't fall much lower, given their cash accumulation :-/
[quote] Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office" <hr></blockquote>
Good for him--and frankly, good for US. After years of broken promises, I can't trust these fvckers at all...that's why I'm assuming we see nothing from them except incremental speed bumps until the PPC970, and Apple moves g4 straight to 970, starting with the PowerMac, then the PowerBook (due to the great low-power version!) while the consumer offerings stay g4 and the iBook gets its promotion finally to g4.
I really doubt that there will be a new g4, or a g5, that is terribly radical in design--why would Mot suddenly be trying? Or succeeding? they cancelled the 86xx--it seems illogical to me that they are going to pull some kind of "g5" out of their asses.
Oh, and here's a nice summary of yesterdays' talk, if'n you haven't seen it:
I just read the Real World Technologies article. The part about the system interconnect is very interesting.
One of the more interesting aspects of the PowerPC 970 processor is the system interconnect. Unlike the bi-directional processor busses seen on Intel IA-32 and IA-64 processor, or even the bi-directional point to point interconnects used on Alpha EV6 and AMD Athlon processors, the system interconnect of the PowerPC 970 processor are uni-directional, point to point, source synchronous interconnects that do not have to worry about bus loading factors or bus turn around times, and the interconnect can wave-pipeline multiple number of bits of data on the wires concurrently. The most difficult part of such high frequency system interconnect may be the deskewing circuitry that would be required. In this case, the PowerPC 970 appears to have benefitted well from the POWER4 lineage, where the deskewing circuitry for a wavepipelined interconnect was previously disclosed by IBM.
The system interconnect on the PowerPC 970 has been designed to operate at an integer fraction of the CPU core frequency. At a CPU core frequency of 1.8 GHz, the system interconnect will operate at a frequency of 900 MHz. With two unidirectional 32 bit wide interconnects, one from the CPU to the companion system controller chip, the other from the companion system controller chip back to the CPU, the system interconnects can provide 3.6 GB/s of raw system bandwidth on each direction for an aggregate bandwidth of 7.2 GB/s. However, the unidirectional links must multiplex address and control information onto the same interconnects, and when these overheads are taken into considerations, IBM claims an effective peak data bandwidth of 6.4 GB per second.
----------------
I'm not so sure Motorola will continue to develop the G4. The G4+ is their high-performance core, and the SNDF paper had roadmaps of the G4+ being the high-end core indefinitly.
It comes down to this: will Motorola continue to be the performance leader in embedded chips, or will they cease development and eventually production of all non-communications CPUs?
If the former, then a G4 with Rapid-I/O is on the horizon.
A 90nm PowerPC 970 would appear to be cool and cheap enough to work where Apple currently uses G4s.
A few years from now, when circitry is thinner again and the 970 is the equivelant of the 7410 in 2001, would imagine it could be used in iBooks.
----------------
I noticed another thing in the Real World Technologies article.
"Moreover, the nature of the point to point interconnect means that to support a dual CPU system, the companion chip must be designed with the dual CPU SMP in mind, with dedicated channels devoted to each CPU. Furthermore, to support the high bandwidth available on the system interconnect, a dual channel PC2700 DDR SDRAM memory system would appear to be a minimum requirement to support a single CPU."
Does this mean that the interconnect is not shared? How exactly does a "uni-directional" bus work?
And I see no reason why Apple has to use RAM which fills the interconnect if it costs too much. There used to be plenty of PC133 Athlon motherboards.
The front-side bus electrically runs at 450-MHz, double-clocked to an effective rate of 900-MHz, generating a peak bandwidth of 7.2 Gbytes or 6.4 Gbytes/s of useable bandwidth after transaction overhead is taken into account, Sandon said.
Add to that 2 32bit busses running in tandem. Is it me of does this sound neither like RIO or HyperTransport? In fact this looks like it is really 2 GX busses like the ones found on the POWER4. Also did anyone note the pin count? Over 550. If it is true that there is no external cache controller then all those pins do indeed look like they will need all these pins. The Power 4 runs the GX bus at 366-433MHz now so 450MHz X 2 does not sound unreasonable. looks like the big difference is that this one runs double pumped. Impressive.
For myself, who deosn't know anything about how this stuff works, I find SpecInt/FP a little suspicious.
Look at the G4 getting smoked by the fastest x86 on these tests, but then we switch to real life and (execpting browsers) the G4 isn't anywhere near 5-10X slower than x86. Timed tests, show the top X86 about 60% faster, give or take. Can that spec mark be accurate? If it was Apple should have been destroyed in any test, but it isn't, even with the lowly G4, it even manages to win a test here and there. So what's going on?
Now there's a chip that (at the very least) doesn't give anything away to X86, but (being on the mac) it's going to get the same OS integration and efficiency, plus altivec, plus multi-CPU prowess.
It looks like good things ahead.
How much is this thing going to cost? Hammer and Itanium will cost alot, do you think IBM will undercut them significantly. That seems implied in the whole GPuL (ultra-Light) designation. Current PPC's are quite affordable, will 970 follow in that mould?
You're right, we should not worry too much about what SPEC shows. If IBM had time to modify the code like Intel and AMD do, their processors would do much better on the test. but they feel that their processors will win over manufacturers with the IBM good name and true real life performance.
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed. </strong><hr></blockquote>
Don't put too much into this, moki. I hear this is one of Steve's standard farewells. In fact Apple employees cherish this particular adieu. It's how they know he's in a good mood.
Anybody wonder what's going to happen when next summer comes? I, for one, can't picture Apple selling many G4 powermacs at this time when the 970 is just months away from being available.
I find it hard to believe that somebody at Apple hasn't thought about this either.
<strong>For myself, who deosn't know anything about how this stuff works, I find SpecInt/FP a little suspicious.
Look at the G4 getting smoked by the fastest x86 on these tests, but then we switch to real life and (execpting browsers) the G4 isn't anywhere near 5-10X slower than x86. Timed tests, show the top X86 about 60% faster, give or take. Can that spec mark be accurate? If it was Apple should have been destroyed in any test, but it isn't, even with the lowly G4, it even manages to win a test here and there. So what's going on?
</strong><hr></blockquote>
You beat me to it. Your observation is exactly correct -- I heavily use both a dual 1 GHz DDR PowerMac and a 1.5 GHz Athlon, and for pretty much everything the PowerMac stomps all over the Athlon, especially in terms of how fast it feels. The SPECmark tests are written in C, and it is easy to write C programs which are biased against PPC to the benefit of x86 by exploiting the load/store nature of the PPC vs. the memory intensive nature of the x86. I have personally written a couple of cases where writing a piece of code one way double the speed of one processor family and halved the other, and then re-writing it halved the first and doubled the second. You might say that this is a problem in the compiler but really its a problem in the language because behaving differently would have been a compiler bug. Add to this that Intel typically uses their own compiler (which is quite good now) and adds their own special markups to the code so that it can make what are normally invalid assumptions. Further, their vector unit supports doing double precision floating point and their compiler supports this now... it was something they had to add because their original FPU design sucks so badly. And lastly, as mentioned above, the SPECmarks use a lot of memory and aren't written very intelligently to try and to a lot of work per memory fetch.
The comparable performance of the POWER4 and GPUL on SPECmarks isn't a result of IBM pulling some tricks, its a result of the improvements in memory bandwidth and superscalar dispatch. My expectation is that the GPUL will scale better than linearly with clockrate over the G4, and as a result in any real test (i.e. not SPEC) it will be a real barn burner.
So forget SPEC -- sure the GPUL is in the right ballpark now, but this isn't showing its real power.
<strong> [quote]
How much is this thing going to cost? Hammer and Itanium will cost alot, do you think IBM will undercut them significantly. That seems implied in the whole GPuL (ultra-Light) designation. Current PPC's are quite affordable, will 970 follow in that mould?</strong><hr></blockquote>
Given that its complexity is less than the PentiumIV and on the same process I would be comparing its cost to Athlon and PentiumIV, not Hammer and Itanium. As I said above, IBM is giving us a 64-bit powerhouse in a stunningly small package. The question shouldn't be will it be cheaper than the competition, but instead, how much cheaper?
To answer a question about the 2 vector units: no, it is one "logical" vector unit split into two execution units. This is similar to the original G4 7400 where there was a vector compute unit and a vector permute unit. The first does all the math, the second does all the moving & shuffling of vector components.
The Real World Technologies article is quite good. In particular:
- Instruction cracking is only used for the few complex PowerPC instructions that are in the ISA. Everything else just goes straight through.
- The pipeline has 9 fetch/decode stages and 5-13 execute stages (depending on the execution unit). That's a total length of 14-22 stages but the majority go through only 14.
- The bus interface is capable of 3.2 GB/sec in each direction. Maximum utilization is thus when an equal amount of data is incoming and outgoing, assuming that the code is already cached. This isn't always the case, so some algorithms will no doubt be unbalanced. It also means that code no longer needs to choose between reads and writes, it can intermingle these more-or-less freely.
- As I've been saying for some time now, getting MacOS X up and running on the 64-bit PPC should be really simple (far less effort than adopting any other processor type, for example) and running 32-bit applications will be absolutely seamless. Extensions to the system APIs to handle 64-bit may take a bit longer, but this means that Apple can adopt the 970 immediately.
- The bus interface means designing the chipset will be more challenging that the current MPX chipset(s)... especially for a dual processor configuration. Furthermore, since the FSB is point-to-point, each processor in an SMP system needs an additional port on the chipset. Given that this is the case, duals should be feasible but I have a hard time imagining Apple building a 3 or more way SMP system. The pin counts would rapidly get excessive and the only way I could see it working would be to have multiple chipsets with their own memories hooked together via something like RapidIO (thus using a NUMA system). My guess is that we'll need to wait for multi-core GPULs before we see Apple go beyond 2-way SMP.
I also noted the need for a new custom system controller that would have to be designed from the beginning for X number of processors. Here's the quote:
"System Chip Support
One of the more troublesome hurdle for Apple to overcome in the adoption of the PowerPC 970 processor may be the system engineering aspect of the processor. As described previously, the 4 byte wide unidirectional serial links may provide upwards of 6 to 7 GB of raw bandwidth per second. However, the specification of the ~900 MHz operation on the system board would require considerable investment into the system support chip. Moreover, the nature of the point to point interconnect means that to support a dual CPU system, the companion chip must be designed with the dual CPU SMP in mind, with dedicated channels devoted to each CPU. Furthermore, to support the high bandwidth available on the system interconnect, a dual channel PC2700 DDR SDRAM memory system would appear to be a minimum requirement to support a single CPU. Unless Apple can also obtain a low cost support chip from IBM, the PowerPC 970 processor would likely force the Apple Macintosh product lines to become even more upscale, and Apple would likely retain the use of the PowerPC G4 processors for the lower end iMac and eMac product lines."
My question, not being a chip tech person, is how long would we expect it to take Apple to design/build/manufacture this chip? Considering that IBM says it won't have samples ready for Apple until April - June 2003, and Apple will need this controller chip to test with the new 970, it would seem EXTREMELY OPTIMISTIC to expect anything but just a pre-announcement at MWNY in July, with availability in the Sep 2003 timeframe, if all goes well. MacOS X also has to be modified to be 64-bit compliant, but I expect that's already been done. That just leaves getting the hardware working reliably.
Comments from anyone who actually understands how all this works?
Like Programmer said, designing multi-processor systems will get unwieldy after 2 CPUs. the CPU and controller communicate with 2 32bit buses; thats at least 120 pins for one CPU. 2 CPUs will need over 200 pins dedicated just for CPU communication, never mind all the other connections needed off the main controller chip. One option is to mount the memory controller right on the same card as the CPU and have a the 2 uni-directional buses talking to only one processor and have a HyperTransport bus connect to other controllers. This way you don't spend time designing an expensive 2-way controller that will be limited to only 2 processors...
<strong>My question, not being a chip tech person, is how long would we expect it to take Apple to design/build/manufacture this chip? Considering that IBM says it won't have samples ready for Apple until April - June 2003, and Apple will need this controller chip to test with the new 970, it would seem EXTREMELY OPTIMISTIC to expect anything but just a pre-announcement at MWNY in July, with availability in the Sep 2003 timeframe, if all goes well. MacOS X also has to be modified to be 64-bit compliant, but I expect that's already been done. That just leaves getting the hardware working reliably.
Comments from anyone who actually understands how all this works?
</strong><hr></blockquote>
IBM would have disclosed details of the processor to Apple many months if not over a year ago. If Apple was on board at that time, they would have had access to early silicon and prototypes, not to mention detailed documentation to at least have a controller pretty much designed. At this time I would expect Apple to have working prototypes using early samples.
<strong>I also noted the need for a new custom system controller that would have to be designed from the beginning for X number of processors. Here's the quote:
"System Chip Support
One of the more troublesome hurdle for Apple to overcome in the adoption of the PowerPC 970 processor may be the system engineering aspect of the processor. As described previously, the 4 byte wide unidirectional serial links may provide upwards of 6 to 7 GB of raw bandwidth per second. However, the specification of the ~900 MHz operation on the system board would require considerable investment into the system support chip. Moreover, the nature of the point to point interconnect means that to support a dual CPU system, the companion chip must be designed with the dual CPU SMP in mind, with dedicated channels devoted to each CPU. Furthermore, to support the high bandwidth available on the system interconnect, a dual channel PC2700 DDR SDRAM memory system would appear to be a minimum requirement to support a single CPU. Unless Apple can also obtain a low cost support chip from IBM, the PowerPC 970 processor would likely force the Apple Macintosh product lines to become even more upscale, and Apple would likely retain the use of the PowerPC G4 processors for the lower end iMac and eMac product lines."
My question, not being a chip tech person, is how long would we expect it to take Apple to design/build/manufacture this chip? Considering that IBM says it won't have samples ready for Apple until April - June 2003, and Apple will need this controller chip to test with the new 970, it would seem EXTREMELY OPTIMISTIC to expect anything but just a pre-announcement at MWNY in July, with availability in the Sep 2003 timeframe, if all goes well. MacOS X also has to be modified to be 64-bit compliant, but I expect that's already been done. That just leaves getting the hardware working reliably.
Comments from anyone who actually understands how all this works?
[ 10-16-2002: Message edited by: Dave Marsh ]</strong><hr></blockquote>
Apple probably already has this chip in house, and most likely has been working on the motherboard since May/June of this year. If I understand it, Apple does a lot of the custom chip design for the Mac systems, so they should have the talent and experience to design the daughter cards for these processors without relying on IBM for everything, and it is possible that IBM and Apple are pooling their R&D budgets together to come up with a common daughter cards and chip sets for the variouse configurations will likely use such as Singal, Dual and Quads.
Here's an interesting thought, what if IBM is designing the hardware for themselves AND Apple to use. Not the actual motherboard, but perhaps the core of the system controller. IBM uses CoreConnect for all their new designs, so if they licensed the actual core to Apple, Apple would have most of the work on a memory/PCI interface already done. Add to the core a firewire, ethernet, and PCI-X controller (all cores that IBM also produces) they can have a solution ready as soon as the processors come out of the factory.
Comments
Will a PowerMac with this chip beat the socks off any SGI machines? Are we likely to see a wholesale switch to the Mac for video production?
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed.
Gosh-- would Steve actually say that? He seems like such a nice, sweet boy.
In my office, managers want to say that all the time to Motorola, but we can't...
- Faster than the G4
- Doesn't get clobbered at projected SPEC (yes, I do use some of the SPEC components regularly)
- May well show up as duals
- This is on a 0.13um process: what would a 0.09u process do for the PowerPC 970?
- VMX supported by bandwidth
But what happens in the meantime? I'd expect the G4 to go to ~1.6GHz, maybe 200MHz MPX FSB or RapidIO.What about the PowerPC 975? 980?
<strong>
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
</strong><hr></blockquote>
Given that is correct, there is going to be a huge lacuna in not just the sale of PowerMacs but also in Apple's profits. Not to mention Motorola's lack of motivation re. research, as noted above. At most, they will have one more G4 upgrade in the pipeline - probably not with the front bus update expected by many here.
I foresee lowered profit expectations from Apple later today - and a corresponding fall in the price of their shares. Only comfort: they can't fall much lower, given their cash accumulation :-/
Good for him--and frankly, good for US. After years of broken promises, I can't trust these fvckers at all...that's why I'm assuming we see nothing from them except incremental speed bumps until the PPC970, and Apple moves g4 straight to 970, starting with the PowerMac, then the PowerBook (due to the great low-power version!) while the consumer offerings stay g4 and the iBook gets its promotion finally to g4.
I really doubt that there will be a new g4, or a g5, that is terribly radical in design--why would Mot suddenly be trying? Or succeeding? they cancelled the 86xx--it seems illogical to me that they are going to pull some kind of "g5" out of their asses.
Oh, and here's a nice summary of yesterdays' talk, if'n you haven't seen it:
<a href="http://www.realworldtech.com/page.cfm?AID=RWT101502203725"; target="_blank">PPC970 presentation at the Microprocessor Forum...a summary.</a>
One of the more interesting aspects of the PowerPC 970 processor is the system interconnect. Unlike the bi-directional processor busses seen on Intel IA-32 and IA-64 processor, or even the bi-directional point to point interconnects used on Alpha EV6 and AMD Athlon processors, the system interconnect of the PowerPC 970 processor are uni-directional, point to point, source synchronous interconnects that do not have to worry about bus loading factors or bus turn around times, and the interconnect can wave-pipeline multiple number of bits of data on the wires concurrently. The most difficult part of such high frequency system interconnect may be the deskewing circuitry that would be required. In this case, the PowerPC 970 appears to have benefitted well from the POWER4 lineage, where the deskewing circuitry for a wavepipelined interconnect was previously disclosed by IBM.
The system interconnect on the PowerPC 970 has been designed to operate at an integer fraction of the CPU core frequency. At a CPU core frequency of 1.8 GHz, the system interconnect will operate at a frequency of 900 MHz. With two unidirectional 32 bit wide interconnects, one from the CPU to the companion system controller chip, the other from the companion system controller chip back to the CPU, the system interconnects can provide 3.6 GB/s of raw system bandwidth on each direction for an aggregate bandwidth of 7.2 GB/s. However, the unidirectional links must multiplex address and control information onto the same interconnects, and when these overheads are taken into considerations, IBM claims an effective peak data bandwidth of 6.4 GB per second.
----------------
I'm not so sure Motorola will continue to develop the G4. The G4+ is their high-performance core, and the SNDF paper had roadmaps of the G4+ being the high-end core indefinitly.
It comes down to this: will Motorola continue to be the performance leader in embedded chips, or will they cease development and eventually production of all non-communications CPUs?
If the former, then a G4 with Rapid-I/O is on the horizon.
A 90nm PowerPC 970 would appear to be cool and cheap enough to work where Apple currently uses G4s.
A few years from now, when circitry is thinner again and the 970 is the equivelant of the 7410 in 2001, would imagine it could be used in iBooks.
----------------
I noticed another thing in the Real World Technologies article.
"Moreover, the nature of the point to point interconnect means that to support a dual CPU system, the companion chip must be designed with the dual CPU SMP in mind, with dedicated channels devoted to each CPU. Furthermore, to support the high bandwidth available on the system interconnect, a dual channel PC2700 DDR SDRAM memory system would appear to be a minimum requirement to support a single CPU."
Does this mean that the interconnect is not shared? How exactly does a "uni-directional" bus work?
And I see no reason why Apple has to use RAM which fills the interconnect if it costs too much. There used to be plenty of PC133 Athlon motherboards.
Barto
The front-side bus electrically runs at 450-MHz, double-clocked to an effective rate of 900-MHz, generating a peak bandwidth of 7.2 Gbytes or 6.4 Gbytes/s of useable bandwidth after transaction overhead is taken into account, Sandon said.
Add to that 2 32bit busses running in tandem. Is it me of does this sound neither like RIO or HyperTransport? In fact this looks like it is really 2 GX busses like the ones found on the POWER4. Also did anyone note the pin count? Over 550. If it is true that there is no external cache controller then all those pins do indeed look like they will need all these pins. The Power 4 runs the GX bus at 366-433MHz now so 450MHz X 2 does not sound unreasonable. looks like the big difference is that this one runs double pumped. Impressive.
Look at the G4 getting smoked by the fastest x86 on these tests, but then we switch to real life and (execpting browsers) the G4 isn't anywhere near 5-10X slower than x86. Timed tests, show the top X86 about 60% faster, give or take. Can that spec mark be accurate? If it was Apple should have been destroyed in any test, but it isn't, even with the lowly G4, it even manages to win a test here and there. So what's going on?
Now there's a chip that (at the very least) doesn't give anything away to X86, but (being on the mac) it's going to get the same OS integration and efficiency, plus altivec, plus multi-CPU prowess.
It looks like good things ahead.
How much is this thing going to cost? Hammer and Itanium will cost alot, do you think IBM will undercut them significantly. That seems implied in the whole GPuL (ultra-Light) designation. Current PPC's are quite affordable, will 970 follow in that mould?
<strong>
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed.
Don't put too much into this, moki. I hear this is one of Steve's standard farewells. In fact Apple employees cherish this particular adieu. It's how they know he's in a good mood.
I find it hard to believe that somebody at Apple hasn't thought about this either.
This may be an option that Apple could use someday if they need a performance boost to keep up with x86.
<strong>For myself, who deosn't know anything about how this stuff works, I find SpecInt/FP a little suspicious.
Look at the G4 getting smoked by the fastest x86 on these tests, but then we switch to real life and (execpting browsers) the G4 isn't anywhere near 5-10X slower than x86. Timed tests, show the top X86 about 60% faster, give or take. Can that spec mark be accurate? If it was Apple should have been destroyed in any test, but it isn't, even with the lowly G4, it even manages to win a test here and there. So what's going on?
</strong><hr></blockquote>
You beat me to it. Your observation is exactly correct -- I heavily use both a dual 1 GHz DDR PowerMac and a 1.5 GHz Athlon, and for pretty much everything the PowerMac stomps all over the Athlon, especially in terms of how fast it feels. The SPECmark tests are written in C, and it is easy to write C programs which are biased against PPC to the benefit of x86 by exploiting the load/store nature of the PPC vs. the memory intensive nature of the x86. I have personally written a couple of cases where writing a piece of code one way double the speed of one processor family and halved the other, and then re-writing it halved the first and doubled the second. You might say that this is a problem in the compiler but really its a problem in the language because behaving differently would have been a compiler bug. Add to this that Intel typically uses their own compiler (which is quite good now) and adds their own special markups to the code so that it can make what are normally invalid assumptions. Further, their vector unit supports doing double precision floating point and their compiler supports this now... it was something they had to add because their original FPU design sucks so badly. And lastly, as mentioned above, the SPECmarks use a lot of memory and aren't written very intelligently to try and to a lot of work per memory fetch.
The comparable performance of the POWER4 and GPUL on SPECmarks isn't a result of IBM pulling some tricks, its a result of the improvements in memory bandwidth and superscalar dispatch. My expectation is that the GPUL will scale better than linearly with clockrate over the G4, and as a result in any real test (i.e. not SPEC) it will be a real barn burner.
So forget SPEC -- sure the GPUL is in the right ballpark now, but this isn't showing its real power.
<strong> [quote]
How much is this thing going to cost? Hammer and Itanium will cost alot, do you think IBM will undercut them significantly. That seems implied in the whole GPuL (ultra-Light) designation. Current PPC's are quite affordable, will 970 follow in that mould?</strong><hr></blockquote>
Given that its complexity is less than the PentiumIV and on the same process I would be comparing its cost to Athlon and PentiumIV, not Hammer and Itanium. As I said above, IBM is giving us a 64-bit powerhouse in a stunningly small package. The question shouldn't be will it be cheaper than the competition, but instead, how much cheaper?
The Real World Technologies article is quite good. In particular:
- Instruction cracking is only used for the few complex PowerPC instructions that are in the ISA. Everything else just goes straight through.
- The pipeline has 9 fetch/decode stages and 5-13 execute stages (depending on the execution unit). That's a total length of 14-22 stages but the majority go through only 14.
- The bus interface is capable of 3.2 GB/sec in each direction. Maximum utilization is thus when an equal amount of data is incoming and outgoing, assuming that the code is already cached. This isn't always the case, so some algorithms will no doubt be unbalanced. It also means that code no longer needs to choose between reads and writes, it can intermingle these more-or-less freely.
- As I've been saying for some time now, getting MacOS X up and running on the 64-bit PPC should be really simple (far less effort than adopting any other processor type, for example) and running 32-bit applications will be absolutely seamless. Extensions to the system APIs to handle 64-bit may take a bit longer, but this means that Apple can adopt the 970 immediately.
- The bus interface means designing the chipset will be more challenging that the current MPX chipset(s)... especially for a dual processor configuration. Furthermore, since the FSB is point-to-point, each processor in an SMP system needs an additional port on the chipset. Given that this is the case, duals should be feasible but I have a hard time imagining Apple building a 3 or more way SMP system. The pin counts would rapidly get excessive and the only way I could see it working would be to have multiple chipsets with their own memories hooked together via something like RapidIO (thus using a NUMA system). My guess is that we'll need to wait for multi-core GPULs before we see Apple go beyond 2-way SMP.
"System Chip Support
One of the more troublesome hurdle for Apple to overcome in the adoption of the PowerPC 970 processor may be the system engineering aspect of the processor. As described previously, the 4 byte wide unidirectional serial links may provide upwards of 6 to 7 GB of raw bandwidth per second. However, the specification of the ~900 MHz operation on the system board would require considerable investment into the system support chip. Moreover, the nature of the point to point interconnect means that to support a dual CPU system, the companion chip must be designed with the dual CPU SMP in mind, with dedicated channels devoted to each CPU. Furthermore, to support the high bandwidth available on the system interconnect, a dual channel PC2700 DDR SDRAM memory system would appear to be a minimum requirement to support a single CPU. Unless Apple can also obtain a low cost support chip from IBM, the PowerPC 970 processor would likely force the Apple Macintosh product lines to become even more upscale, and Apple would likely retain the use of the PowerPC G4 processors for the lower end iMac and eMac product lines."
My question, not being a chip tech person, is how long would we expect it to take Apple to design/build/manufacture this chip? Considering that IBM says it won't have samples ready for Apple until April - June 2003, and Apple will need this controller chip to test with the new 970, it would seem EXTREMELY OPTIMISTIC to expect anything but just a pre-announcement at MWNY in July, with availability in the Sep 2003 timeframe, if all goes well. MacOS X also has to be modified to be 64-bit compliant, but I expect that's already been done. That just leaves getting the hardware working reliably.
Comments from anyone who actually understands how all this works?
<img src="confused.gif" border="0">
[ 10-16-2002: Message edited by: Dave Marsh ]</p>
<strong>My question, not being a chip tech person, is how long would we expect it to take Apple to design/build/manufacture this chip? Considering that IBM says it won't have samples ready for Apple until April - June 2003, and Apple will need this controller chip to test with the new 970, it would seem EXTREMELY OPTIMISTIC to expect anything but just a pre-announcement at MWNY in July, with availability in the Sep 2003 timeframe, if all goes well. MacOS X also has to be modified to be 64-bit compliant, but I expect that's already been done. That just leaves getting the hardware working reliably.
Comments from anyone who actually understands how all this works?
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IBM would have disclosed details of the processor to Apple many months if not over a year ago. If Apple was on board at that time, they would have had access to early silicon and prototypes, not to mention detailed documentation to at least have a controller pretty much designed. At this time I would expect Apple to have working prototypes using early samples.
<strong>I also noted the need for a new custom system controller that would have to be designed from the beginning for X number of processors. Here's the quote:
"System Chip Support
One of the more troublesome hurdle for Apple to overcome in the adoption of the PowerPC 970 processor may be the system engineering aspect of the processor. As described previously, the 4 byte wide unidirectional serial links may provide upwards of 6 to 7 GB of raw bandwidth per second. However, the specification of the ~900 MHz operation on the system board would require considerable investment into the system support chip. Moreover, the nature of the point to point interconnect means that to support a dual CPU system, the companion chip must be designed with the dual CPU SMP in mind, with dedicated channels devoted to each CPU. Furthermore, to support the high bandwidth available on the system interconnect, a dual channel PC2700 DDR SDRAM memory system would appear to be a minimum requirement to support a single CPU. Unless Apple can also obtain a low cost support chip from IBM, the PowerPC 970 processor would likely force the Apple Macintosh product lines to become even more upscale, and Apple would likely retain the use of the PowerPC G4 processors for the lower end iMac and eMac product lines."
My question, not being a chip tech person, is how long would we expect it to take Apple to design/build/manufacture this chip? Considering that IBM says it won't have samples ready for Apple until April - June 2003, and Apple will need this controller chip to test with the new 970, it would seem EXTREMELY OPTIMISTIC to expect anything but just a pre-announcement at MWNY in July, with availability in the Sep 2003 timeframe, if all goes well. MacOS X also has to be modified to be 64-bit compliant, but I expect that's already been done. That just leaves getting the hardware working reliably.
Comments from anyone who actually understands how all this works?
[ 10-16-2002: Message edited by: Dave Marsh ]</strong><hr></blockquote>
Apple probably already has this chip in house, and most likely has been working on the motherboard since May/June of this year. If I understand it, Apple does a lot of the custom chip design for the Mac systems, so they should have the talent and experience to design the daughter cards for these processors without relying on IBM for everything, and it is possible that IBM and Apple are pooling their R&D budgets together to come up with a common daughter cards and chip sets for the variouse configurations will likely use such as Singal, Dual and Quads.