jony0
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What's new with macOS Sequoia's System Settings
TravisV said:the macOS Sequoia Passwords app is one of the best features coming to Sequoia. Hopefully it won't be to buggy by the fall. Ay least I can then get rid of my iPassword app and subscription. -
Apple reveals iPadOS 17 with customizable Lock Screen, Health app, more
appleinsideruser said:Looking forward to seeing my Health data on iPad. -
Russia claims Apple is helping US spy on thousands of iPhone users
iqatedo said:...and Ukraine invaded Russia on 24th February 2022...
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Jony Ive's lifetime of design work honored with Edison Achievement Award
Marvin said:Rogue01 said:Not everything he designed was a winner. -
Apple could be the first to use TSMC's 3nm chip process for M2 Pro
AppleInsider said:Apple's 2022 MacBook Pros may pack new M2 Pro and M2 Max chipsets made with TSMC's latest 3nm manufacturing process, according to a new report.
TSMC, the world's largest semiconductor contract manufacturer, has been steadily building out its 3nm production processes. According to the Commercial Times, Apple could be the first customer to get its hands on those chips.
The report notes that Apple will use 3nm wafers for the first time in the second half of 2022, likely for its M2 Pro chipsets. Future releases built on the 3nm process could include the iPhone-specific A17 chipset, as well as a future third-generation of the M series.
Commercial Times also separately reported that TSMC will begin mass production of its 3nm wafers in September. The report adds that initial yield will be higher than when TSMC switched to 5nm processes.
Compared to previous chipmaking processes, semiconductors made using the 3nm process could bring increased power efficiency and performance to Apple's devices.waveparticle said:3nm is not a wafer. It is a process. TSMC is able to ramp up its process technology to firmly keep Apple in its camp as well as numerous other chip design companies.
I can only assume that AI being well aware that it is a [manufacturing, production] process applied to [chipsets, releases, semiconductors].
I can only assume that AI assumed they could safely use the single word wafer shorthand rather than more multi-worded expressions, assuming that most readers here would not confuse the issue. So … no biggie.
There is no industry-wide agreement about defining a 3 nm node either (emphasis mine) :
https://en.wikipedia.org/wiki/3_nm_processThe term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers. However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.
It's just a number they use relative to their previous process to indicate some reduction in node geometry of different transistor technologies.
Full disclosure I didn't know that either before looking it up now and am a bit disappointed, I thought it actually meant an actual size.