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HiramAbif said:

"This can be especially useful for Apple Watch Ultra users, who may use the rugged smartwatch while deep off-grid or at sea, and out of 5G range."

Considering that the Apple Watch series doesn't have 5G radios, that wouldn't really matter would it? 

Along with the sat-com rumor, the 2025 Watches are rumored to come with 5G modems. Like the LTE ones in existing Watch, they would be lower performance 5G modems, typically used for smaller devices or low bandwidth devices.

While most smartphones have their RAM on the same package as the processor, Apple is looking to go against the norm. In order to allow for more RAM and also speed up memory access for Apple Intelligence tasks, it now wants to put the RAM and processor on separate chips.

The article reads like a jumbled mess.

The LPDDR RAM and the logic chip in an iPhone SoC package are separate chips. It's a package-on-package architecture where the LPDDR chip package is stacked on top of the logic chip (eg, the A18 silicon chip). The whole thing is then encased in a ceramic or resin compound and appears as "one" package with many media folks calling it a "chip".

Apple already has multiple ways to increase RAM quantities and RAM bandwidth. In the M4 (or M3, M2, M1, A12X, etc), they don't stack the RAM on top of the logic chip. They placed them adjacent to the logic chip. There are 2 RAM packages in the M4 constituting 2 LPDDR interfaces, which doubles the bandwidth from the A18 package. The M4 Pro quadruples, and the M4 Max octuples. Obviously, there are space constraints with the bigger chips and higher memory bandwidths, and they are not going into a phone.

Dollars to donuts, Apple wants to use commodity LPDDR memory. Hard to believe that would go with a custom memory for something like the iPhone, so the rumor score really should be something like unlikely, poor, or low possibility. For the A19, A20, they are just going to use PoP with 8, 12, or 16 GByte memory packages and call it a day. Memory bandwidth probably goes up to something like 75 GByte/s, or perhaps whatever is for LPDDR6.

Apple did work with Sk Hynix to create a low-latency wide I/O RAM interface for the Vision Pro R1 co-processor. It's a 128 MByte chip with a 512 bit memory interface, with about double the bandwidth of LPDDR5, and supposedly better latency. There's 8x as many pinouts in the R1 memory interface, with less bandwidth per pin, compared to LPDDR. Would they do something like this with 8, 12, 16 GByte of memory? Only if it costs about as much as using LPDDR after x millions of units made, or perhaps if it is more power efficient and offers a marketable feature or improvement.

sldpll said:

Wouldn’t this be one of the worst ways to mount a bunch of M4 Mac minis? The new mini air intake is on the front part of the bottom circle and exhausts hot air through the back of the bottom circle, blowing hot air directly into the next Mac mini. Making the Mac minis on the left side intake up to 3x heated air…

If you have ever been in a server room, you want to be in the back, where it would actually be a comfortable temperature. The front? Like 60 °F.

The are many server designs where CPUs and GPUs are placed serially to the cooling flow as a rack is typically deeper than it is wide. They would account for that in the cooling design of the building. 

The speculation is that the foveation is done differently now. What you guys know about that?

That is, more of your Mac display field of view is clearer than fuzzed than before. So, it can look clearer. Is the foveation now done on the Mac? Was it always done on the Mac in the first place?

visionOS also needs an iPhone virtual display feature just like it is on the Mac now. 

elijahg said:

It's almost certainly PCIE on a non-standard connector, like every Mac that has actually had a slotted SSD since about 2012. However, there may be a controller on the "blade" that has special Apple firmware.

The SSD controller is on-chip connected to the on-chip switched fabric. It is NVMe, but is not on a PCIe bus. It's an on-chip SSD controller connected to the same on-chip bus that the CPU, GPU, NPU, SLC, memory controller, etc, share.

It's been about 7 years since the iMac Pro. The media has to stop calling these Apple NAND daughterboards SSDs. It's dumb NAND on the daughterboards. They used it for the iMac Pro, Mac Pro, Mac Studio and now Mac mini. Circuit-wise, it's no different than the soldered on NAND on the laptop boards, save for instead of being on the logic board, the NAND is on a daughterboard.

I think they think the increase security is worth not using commodity PCIe/NVMe based SSD boards. I'm assuming they think that it is much harder to extract data out of the daughterboards than a NVMe storage board. Being able to control storage pricing is another big plus for them.

The M4 Pro Mac mini supports 8 TB storage. I think that means 4 NAND packages if another doubling in density has become affordable, otherwise it could be 8 NAND packages. So, that tiny daughterboard can have 8 NAND packages on it? Or do the M4 Pro models have 2 daughterboards? Will be interesting to see how 8 TB of NAND or put into the Mac mini.