Uh, people. The system bus on all PCs that use DDR266 is 133. DDR doubles the rate of the system bus for memory access by transferring data twice per cycle.
<strong>How about clustering? I thought it was mentioned during Jobs's announcement. Is this possible with OS X Server? How will the nodes be connected?</strong><hr></blockquote>
clustering is supported. they did a cluster demo.
probably using gigabit ethernet and proprietary software like many do now with normal PowerMacs
Mike from AccelerateYourMac has emailed two different sources at Apple to see if the G4 does actually support the DDR Ram.
[quote]New G4 Server - Conflicting Specs on CPU vs RAM Bandwidth - I hope this is just a typo/leftover from the previous server specs, but a reader noted that the PDF specs file for the new sever lists under the Hardware/CPU specs (Page 25 of PDF - under "hardware" it says)
"133mhz bus supporting over 1GB/sec of data throughput"
The Memory section shows the usual PC2100 2.1GB/sec memory bandwidth. (It's standard for PC2100 DDR systems to have a 133mhz bus - DDR triggering on rising/falling edge of the clock for effective 2x rates.)
I've written two contacts at Apple to ask if the specs in the CPU section are a typo or if the G4 chip used does not really support DDR memory rates. (The 7450 and later G4s have always supported DDR L3 cache, the question was if they fully supported DDR memory.)<hr></blockquote>
<strong>The Memory section shows the usual PC2100 2.1GB/sec memory bandwidth. (It's standard for PC2100 DDR systems to have a 133mhz bus - DDR triggering on rising/falling edge of the clock for effective 2x rates.)
</strong><hr></blockquote>
Given the fact that they explicitely label PC2100 RAM as "266MHz" on their specs page, I doubt that they'd in contrast call the same thing "133MHz" for the FSB.
Also, don't you think that, now that Apple made their press conference, Motorola would mention such a DDR-capable G4 on their web page?
<strong>Mike from AccelerateYourMac has emailed two different sources at Apple to see if the G4 does actually support the DDR Ram.
</strong><hr></blockquote>
Different CPU and Memory bandwidths aren't unheard of.
There have been two Rambus chipsets (i820 single channel, i840 dual channel) for the Pentium III, which had a 133 Mhz SDR bus just like the G4. There was a DDR chipset too if I'm not mistaken, probably by VIA. Of course these did not bring any tangible performance improvements, in fact the Rambus chipsets were part of the reason for the initial bad rap that RDRAM got. It was much more expensive than SDRAM at the time, and it didn't perform much better. When the P4 came out, everybody realised it was the P3 that was the problem and not RDRAM.
There are also 133 Mhz SDRAM chipsets for the 4x100 Mhz Pentium 4, and 333 Mhz DDR for the 266 Mhz Athlon, you get the picture...
Do you guys have confirmation from spec papers, white papers, or other tech docs that confirms that all the I/O is going through independently?
On all current chipsets that I can think of with a snoppy bus, IDE/ATA is on the PCI bus and PCI is sitting on the front side bus. That means these things normally share the bandwidth of the bus. This is the resoning around the original idea for a bus to allow for connection to memory to be reasonable width on the motherboard and also allows easy snoopy for MP support. Maxbus is a snoppy bus, so unless Apple put the PCI and ATA on a separate DDR bus and has some sort of bridge chip to facilitate communication with the 133MHz FSB, then there won't be any advantage.
I really hope that this is what they did. They needed to add a buffer anyways from the FSB to the DDR memory since data is bursting out every half-cycle once initiated, so they have to be cached somewhere to get timing to line up with when the CPU will be grabbing the data off of the FSB. This part would have been easy for Apple to do, but really does not give much performance improvement.
Putting the PCI and ATA IO on a separate DDR bus would have been good for performance if they could figure out how to efficiently make it work with snooping. Easy way is to not do cached IO, but that would be bad.
I'm pretty sure what Apple did is extended their old NorthBridge/SouthBridge model to a hub and spoke model. This is similar to what new Intel chipsets since the 810 and the Athlon hypertransport based chipsets do. You can easily snoop as long as you forward the correct pieces of data between the hub components.
Comments
The server market mostly uses mostly P3s with a 133 bus. Check out these Proliant servers and see how well the new Xserves blows them away on price and performance: <a href="http://www.smb.compaq.com/ctoBases.asp?ProductLineId=431&FamilyId=1171&oi=E9 CED&BEID=19701&SBLID=" target="_blank">http://www.smb.compaq.com/ctoBases.asp?ProductLineId=431&FamilyId=1171&oi=E9 CED&BEID=19701&SBLID=</a>
Apple did a great job with the Xserve, the only thing that's missing is a SCSI version.
Thanks, I was confusing communication between L3 cache and the main memory. One day I may get it right.</strong>
Maybe this will help:
[code]
---------------------------
| 2 MB backside L3 DDR SRAM |
---------------------------
|
[4 GByte/s, 4:1 CPU:cache clock ratio]
|
------------------
| 1 GHz MPC 7455 |
------------------
|
[1.067 GByte/s 133 MHz MPX bus]
| ------ Gigabit Ethernet
| |
--------------------------------------------
| Core logic chipset (ASIC, aka Northbridge) | -- Firewire
--------------------------------------------
| | |
[2.1 GByte/s] [AGP 4x 1.067 GB/s] [PCI 0.533 GB/s]
| [PCI 0.266 GB/s ] |
| | |------ 2 64x66 PCI slots
PC2100 DDR Graphics |
SDRAM card |------ 4 indepedent ATA/100 buses
|
------ serial, CD-ROM, USB
</pre><hr></blockquote>
Not sure if Apple has a new "southbridge" to support ATA/100, USB, and EIDE (for optical drive) or not.
<strong>How about clustering? I thought it was mentioned during Jobs's announcement. Is this possible with OS X Server? How will the nodes be connected?</strong><hr></blockquote>
clustering is supported. they did a cluster demo.
probably using gigabit ethernet and proprietary software like many do now with normal PowerMacs
Thank you, that helps me visualize better.
One small step for Apple, one giant leap in understanding for me.
[quote]New G4 Server - Conflicting Specs on CPU vs RAM Bandwidth - I hope this is just a typo/leftover from the previous server specs, but a reader noted that the PDF specs file for the new sever lists under the Hardware/CPU specs (Page 25 of PDF - under "hardware" it says)
"133mhz bus supporting over 1GB/sec of data throughput"
The Memory section shows the usual PC2100 2.1GB/sec memory bandwidth. (It's standard for PC2100 DDR systems to have a 133mhz bus - DDR triggering on rising/falling edge of the clock for effective 2x rates.)
I've written two contacts at Apple to ask if the specs in the CPU section are a typo or if the G4 chip used does not really support DDR memory rates. (The 7450 and later G4s have always supported DDR L3 cache, the question was if they fully supported DDR memory.)<hr></blockquote>
<strong>The Memory section shows the usual PC2100 2.1GB/sec memory bandwidth. (It's standard for PC2100 DDR systems to have a 133mhz bus - DDR triggering on rising/falling edge of the clock for effective 2x rates.)
</strong><hr></blockquote>
Given the fact that they explicitely label PC2100 RAM as "266MHz" on their specs page, I doubt that they'd in contrast call the same thing "133MHz" for the FSB.
Also, don't you think that, now that Apple made their press conference, Motorola would mention such a DDR-capable G4 on their web page?
Bye,
RazzFazz
<strong>Mike from AccelerateYourMac has emailed two different sources at Apple to see if the G4 does actually support the DDR Ram.
</strong><hr></blockquote>
Different CPU and Memory bandwidths aren't unheard of.
There have been two Rambus chipsets (i820 single channel, i840 dual channel) for the Pentium III, which had a 133 Mhz SDR bus just like the G4. There was a DDR chipset too if I'm not mistaken, probably by VIA. Of course these did not bring any tangible performance improvements, in fact the Rambus chipsets were part of the reason for the initial bad rap that RDRAM got. It was much more expensive than SDRAM at the time, and it didn't perform much better. When the P4 came out, everybody realised it was the P3 that was the problem and not RDRAM.
There are also 133 Mhz SDRAM chipsets for the 4x100 Mhz Pentium 4, and 333 Mhz DDR for the 266 Mhz Athlon, you get the picture...
Do you guys have confirmation from spec papers, white papers, or other tech docs that confirms that all the I/O is going through independently?
On all current chipsets that I can think of with a snoppy bus, IDE/ATA is on the PCI bus and PCI is sitting on the front side bus. That means these things normally share the bandwidth of the bus. This is the resoning around the original idea for a bus to allow for connection to memory to be reasonable width on the motherboard and also allows easy snoopy for MP support. Maxbus is a snoppy bus, so unless Apple put the PCI and ATA on a separate DDR bus and has some sort of bridge chip to facilitate communication with the 133MHz FSB, then there won't be any advantage.
I really hope that this is what they did. They needed to add a buffer anyways from the FSB to the DDR memory since data is bursting out every half-cycle once initiated, so they have to be cached somewhere to get timing to line up with when the CPU will be grabbing the data off of the FSB. This part would have been easy for Apple to do, but really does not give much performance improvement.
Putting the PCI and ATA IO on a separate DDR bus would have been good for performance if they could figure out how to efficiently make it work with snooping. Easy way is to not do cached IO, but that would be bad.
I'm pretty sure what Apple did is extended their old NorthBridge/SouthBridge model to a hub and spoke model. This is similar to what new Intel chipsets since the 810 and the Athlon hypertransport based chipsets do. You can easily snoop as long as you forward the correct pieces of data between the hub components.
[ 05-22-2002: Message edited by: mmaster ]</p>