<strong>Maybe a 7470 or 7500 chip in Jan'. eg 7470 on proper DDR.</strong><hr></blockquote>
It has been stated the MPX bus won't go DDR before and I really see no reason to suspect that will change. The only way Powermacs will get a DDR bus is if th MPX bus is replaced. The most likely way Motorola will do that is an on-chip memory controller and RapidIO. I doubt we'll see that in Motorola's next revision though, which means late next year probably before you see that.
[quote]<strong>Thing is. Are Apple going Hyper or Rio? Are IBM going Rio or Hyper. I would have thought Rio. That would indicate a 7500 on Rio being Moto's last chip to take us through to next Summer...and IBM early 2004. Annoying.</strong><hr></blockquote>
IBM is a known supporter of RapidIO. Hypertransport really has other places on the board in my mind but I may be wrong.
[quote]<strong>Do Moto' think they can get the G4 2 gig and higher? Maybe they can. But I say they can sodding keep it...because it'll take them a couple of years to get there from now...</strong><hr></blockquote>
I'd suspect something along the lines of 1.5GHz then ~1.8GHz if Apple keeps the G4.
[quote]<strong>Jan' 2004 = IBM chip on Hypertransport?</strong><hr></blockquote>
I would suspect they use RIO if anything. Just wait until October and I suppose we'll know for certain.
[quote]<strong>[The current set up looks like a 'penultimate' topping out of the G4 to me. The G4 was supposed to top out at its current speed. No?</strong><hr></blockquote>
I'm really not sure where this comes from. It has been stated time and again the G4 has life left. Motorola didn't lie about a 167MHz FSB and they aren't lying about that. My suspicion is the next revision will probably be 1.5 GHz with a larger level 2 cache and finally on the 0.13 micron process.
Just today I saw a paper on IBM's site that had a graph for RIO bandwidth. The 16 bit implementation running at 1GHz achieves 64Gbps, or about 8GBps, 25% more bandwidth than the 6.4GBps the BabyPOWER4 is supposed to deliver. A 500-700MHz implementation would deliver enough bandwidth for this chip and other components.
But the POWER4 has a memory controller piggy backed on the L3 controller (or vice versa most likely) and IBM's bandwidth estimate might be
memory_controller_bandwidth + RIO bandwidth = 6.4GBps
I think this is the likely scenario. Being a forward thinking company, I would assume that IBM would have the BabyPOWER4 have an advanced memory interface like DDR-II 400 with 3.2GBps aggregate bandwidth (single channel) and that leaves 3.2GBps for peripheral devices like PCI-X bus(ses), firewire, Gb ethernet, multiple IDE interfaces, AGP 8X, etc. These peripherals would communicate with the processor(s) via RIO (a switched fabric).
A powermac based on this would look something like this:
[code]
PCI slots
____ ||||
=====\\____|CPU |_ |||| | AGP 8X
=====/ |____| | ____|___|_
RAM+L3 |________|PCI |--== ATA/1XX
____ | RIO |peripheral|
=====\\____|CPU |_|500MHz |__________|--= USB
=====/3.2 |____| 16bit | |
Gbps 3.2 Gb fire
Gbps eth. wire
</pre><hr></blockquote>
And better yet, it IBM implements 2 RIO busses on the processor, one can be dedicated to inter-processor communication. 16bit RIO only requires 70 odd pins or so.
<strong>Just for reference, the Sahara was introduced at the Microprocessor Forum last October, and then got into iBooks 7 months later this past May. At the conference, they said the Sahara would begin sampling in January. So we'll have to see when they say this new Power4 begins sampling - that may give us an idea as to when Apple could use it.</strong><hr></blockquote>
That is a good comparison allright, a previous IBM chip for Apple. One thing makes me doubt they will follow the same pattern however. A new G3 is not that big of a deal to most Mac users. A G5 for the PowerMac line is a huge deal. Everyone will be following this closely. If IBM says samples in January, folks can pretty much peg when Apple will come out with it. Now what would that do to Apple sales, say three to six months before the G5 ships? It is not like this is a speed bump. It is a big leap in performance. When everyone thinks a G5 is coming soon, few will buy a G4 PowerMac. IBM and Apple surely considered such customer reactions in making plans. Maybe I give them too much credit, but I don't think so. That is another reason I see an earlier introduction into the PowerMac.
Here is pure speculation, thinking of how the G5 might be introduced. It might ship very soon and appear in the top end of the PowerMac at a higher price. The G4 would keep selling at the lower end, as people see the distinction and many decide they do not need the G5's performance, and price. Fairly quickly, I would expect to see lower priced G5s with a lower clock rate moving down, and eventually into the lowest PowerMac. This would give a gentle ramp up to G5 production. The G5 would sell very well at the top end, and for a while keep the G4 selling in the lower end PowerMacs.
Okay, I admit I'm a wild optimist too, but this makes more sense to me than letting PowerMac customers see the G5 coming well in advance.
<regarding use of the term "penultimate" w.r.t. the new G4s>
I'm really not sure where this comes from. It has been stated time and again the G4 has life left. Motorola didn't lie about a 167MHz FSB and they aren't lying about that. My suspicion is the next revision will probably be 1.5 GHz with a larger level 2 cache and finally on the 0.13 micron process.</strong><hr></blockquote>
[quote]
pe·nul·ti·mate Pronunciation Key (p-nlt-mt)
adj.
Next to last.
<hr></blockquote>
That is exactly what I meant -- we will probably see one more refinement of the G4 prior to Apple's adoption of the new IBM processor. A process shrink and larger L2 are the most likely candidates, although an on-chip memory controller & alternate bus (probably RIO) are an outside possibility. Topping out at 1.8 GHz according to what Motorola said a while back. MPX will not go DDR.
<strong>Just today I saw a paper on IBM's site that had a graph for RIO bandwidth. The 16 bit implementation running at 1GHz achieves 64Gbps, or about 8GBps, 25% more bandwidth than the 6.4GBps the BabyPOWER4 is supposed to deliver. A 500-700MHz implementation would deliver enough bandwidth for this chip and other components. </strong><hr></blockquote>
Its also worth noting that RIO has rougly 20-25% overhead due to packet headers and the like.
If it is G5 ready, that will qualify its looks...when it arrives...
The case seems to be dropping some hints to me...from what I've heard about the heat sink's size and all...
I'd love to see those Pentium 4 snail ad's...
Thought, now that Apple are openly using 'code names' for their OS...eg Jaguar. What chance we'll have a G5 'Hoover'....called something 'ard n' nasty?
That is exactly what I meant -- we will probably see one more refinement of the G4 prior to Apple's adoption of the new IBM processor. A process shrink and larger L2 are the most likely candidates, although an on-chip memory controller & alternate bus (probably RIO) are an outside possibility. Topping out at 1.8 GHz according to what Motorola said a while back. MPX will not go DDR.</strong><hr></blockquote>
With a process shrink, this gives some leeway on whet Motorola thinks would be useful for embedded applications; hopefully this is also in line with what would be useful for a desktop processor. For example, if they double the L2, and replace the L3 controller with a DDR memory controller, but keep MPX as the external bus, they can satisfy the embedded controller markets as well as the desktop (Apple) markets. Then even when Apple transitions the PowerMac to the BabyPOWER4, they will still have a processor to use with the PowerBook, iMac, and possibly iBook for some time to come.
Well, if it's any help on feeding the rumors, I have it on good authority that the POWER4 design group from RTP, NC, moved to the NY fab center within the past month...
Uncertain if this was the POWER4 group, or the POWER4-derived PPC group... but hints point at the latter.
That is exactly what I meant -- we will probably see one more refinement of the G4 prior to Apple's adoption of the new IBM processor. A process shrink and larger L2 are the most likely candidates, although an on-chip memory controller & alternate bus (probably RIO) are an outside possibility. Topping out at 1.8 GHz according to what Motorola said a while back. MPX will not go DDR.</strong><hr></blockquote>
The current release will very likely be the penultimate one by choice rather than technical reasons. That's all I meant. I'm glad we agree on what's coming next though
The POWER4 was designed to tackle some issues that IBM needed to take care of for a high performance modern CPU.
First issue was SMP optimization. They needed a CPU designed for high-throughput multitasking and the ability to handle multiple active processes. Secondly, the designed for a full-system design. They needed to redesign every bus in and out, every subsystem, for complete optimization and performance. Then they needed a highly scalable, high frequency design to deliver the best possible performance. Because, as we'll see later, total system performance depends on this point more so than before in traditional designs. They also needed RAS (Reliability, Availability, and Serviceability). They have included heavy duty ECC and redundant parts for this aspect, but much of it also has to do with total system design, but they made the processor much less prone to normal failures. And finally, compatibility with PowerPC be it either 32bit instructions or 64bit ones.
The POWER4 features 2 identical processor cores on one die. They each have an exclusive L1 (64KB instruction, 32KB data, ) cache and a unified 1.5MB of full speed L2 cache (256bit wide; 3 banks of 512KB each). L3 is on a separate chip and is controlled by a dedicated L3 controller and communicates with the external L3 at 128bits wide and at one third the processor speed (32MB maximum per module, but can be combines with the cache of other modules on the MCM to have a total of 128MB!). The POWER4 can also do out of order execution.
To communicate with other controllers and I/O, the POWER4 uses the GX bus. The GX bus is actually 2 32bit wide buses that operate at one third the processor speed also. Notice that all the buses so far will scale with processor frequency. As the processor gets faster, total system performance will scale proportionately, giving the system a better performance balance.
The POWER4 can issue up to 8 instructions per cycle (there are 8 execution units) with a sustained completion rate of 5 instructions. Each core has 2 double precision FPUs, 2 load/store units, 2 integer units, a beefy BPU for branch prediction, and another execution unit to perform logical operations on the condition register. The minimum penalty for a missed branch prediction is a loss of 12 cycles (12 pipeline stages) but the POWER4 has 16 pipeline stages. (This was difficult to determine but I found this obscure piece of information deep in an IBM research paper).
Memory management become tricky with the POWER4. Each processor can have an optional memory controller attached behind the L3 cache. On an IBM system the memory controller is actually attached to the memory card, and the controller is attached to the L3 eDRAM chip. Therefore maximum possible bandwidth to memory is only limited by the L3 cache limit. On a 1.3GHz POWER4 that is 6.933GBps. The memory controller attached to the L3 by means of 2 64bit buses, one in each direction, at one third the processor speed. The memory cards themselves use 400MHz (fixed frequency) DRAM memory chips with 2 bit ECC connected to memory controllers via 4 16bit bidirectional buses. This 400MHz DRAM gives you about... 6.4GBps.
IBM can connect 4 processors on one MCM to allow for 8 cores per MCM within the MCM they act like a switch. They can all share and snoop all the L3 cache (up to 128MB total). You can connect up to 4 of these MCMs to have a total of 32 cores in the system. All the MCMs in the system transfer data back and forth in a ring topology.
What a desktop version of the POWER4 may hold in store
First of all it would most likely have only one core in initial versions, but otherwise the core would be virtually identical to the one in the POWER4. Instead of 1.5MB of L2 cache, 3 banks of 256KB, or 768KB would be more likely.
The GX bus is overkill especially for something as simple at peripheral control. IBM is working on RapidIO implementations so it is likely they would have one RIO bus (16bit) to connect to the PCI bus/ ethernet/ firewire /etc. and one GX bus (at one quarter processor speed but this is best left to be a variable; 4:1, 5:1, 6:1 etc.) for inter-processor communication.
Since the L3 controller on the processor already support the memory access, you will need about 2-4MB of L3 cache (eDRAM) and to the cache a memory controller of Apple's choosing would interface with it. It can be anything since this approach is so flexible. Apple merely needs to create the interface. It can be DDR, DDR-II, RDRAM, QDR, whatever comes out in the future. The memory controller it self can house the eDRAM L3 cache to minimize design complexity on the motherboard.
It seems to me that once a year there are rumours about the next generation Powermac. About a year ago, I think it was october or november. I heard about a 64bit G5 prototype 1.6 Ghz MP with a 400Mhz FSB running a special version of Os X doing very fast tricks in the lowland.
2 months later I heard about Moto's 85xx embedded processor and feared this original G5 died with it's introduction. After the introduction of the G4 1Ghz MP powermac I thought the rumour about this particular G5 was a cruel tease of a friend of mine.
Now, 7 Months later this new IBM G5 processor appears as intended successor of the G4 and I am very currious about it's history: is this the same prototype my dear geek friend mentioned or is this something completly different. I know hardware testing is a long and painfull process espacially in this particular case with this "new" 64bit processor so I wonder; could this IBM power4light thing ended up a year ago in a prototype macintosh
<strong>It seems to me that once a year there are rumours about the next generation Powermac. About a year ago, I think it was october or november. I heard about a 64bit G5 prototype 1.6 Ghz MP with a 400Mhz FSB running a special version of Os X doing very fast tricks in the lowland.
2 months later I heard about Moto's 85xx embedded processor and feared this original G5 died with it's introduction. After the introduction of the G4 1Ghz MP powermac I thought the rumour about this particular G5 was a cruel tease of a friend of mine.
Now, 7 Months later this new IBM G5 processor appears as intended successor of the G4 and I am very currious about it's history: is this the same prototype my dear geek friend mentioned or is this something completly different. I know hardware testing is a long and painfull process espacially in this particular case with this "new" 64bit processor so I wonder; could this IBM power4light thing ended up a year ago in a prototype macintosh
or was it the cancelled 7500 from motorola?
</strong><hr></blockquote>
The really big difference here is that this is all based on information straight from IBM. In October we're going to get a lot more information, hopefully including a timeline.
That this PowerPC will be 8-way superscalar is simply amazing... I was just reading some of AMD's specs on their Hammer and it is only 3-way superscalar (backed by 9 execution units). This means that at the same clock rate the IBM chip can dispatch 2.67 times as many instructions! Now if it can't get them from memory fast enough, or if there aren't enough execution units to feed them to, this won't amount to anything... but it certainly has a lot of potential. It could be (if there are enough execution units) that at 2GHz this thing could seriously outperform a 4 GHz Hammer. I'd argue that between an "equivalent" (i.e. they can process an equal number of instructions per second, have the same memory bandwidth, etc) PowerPC and x86-64, the PowerPC will get significantly more work done -- the instruction set is substantially better and it has far more registers. And with a much lower clock rate the PowerPC will likely run cooler. I can't wait to hear more about this beast IBM is building. :eek:
The really big difference here is that this is all based on information straight from IBM. In October we're going to get a lot more information, hopefully including a timeline.
That this PowerPC will be 8-way superscalar is simply amazing... I was just reading some of AMD's specs on their Hammer and it is only 3-way superscalar (backed by 9 execution units). This means that at the same clock rate the IBM chip can dispatch 2.67 times as many instructions! Now if it can't get them from memory fast enough, or if there aren't enough execution units to feed them to, this won't amount to anything... but it certainly has a lot of potential. It could be (if there are enough execution units) that at 2GHz this thing could seriously outperform a 4 GHz Hammer. I'd argue that between an "equivalent" (i.e. they can process an equal number of instructions per second, have the same memory bandwidth, etc) PowerPC and x86-64, the PowerPC will get significantly more work done -- the instruction set is substantially better and it has far more registers. And with a much lower clock rate the PowerPC will likely run cooler. I can't wait to hear more about this beast IBM is building. :eek: </strong><hr></blockquote>
Also consider that this will not be a MHz slouch. The POWER4 core has anywhere between 14 and 16 pipeline stages. Although less than the P4 this is more than the Hammer/Athlon. MHz is not the best way to measure performance, but add in the 8 way superscalar design and advanced branch predictor and you have a winning combination that will clock in slightly slower than the P4 but blow it completely away. Any real competition from Intel will come only from the Itanium2.
Also, if you read the article, you'll notice they refer to a 64bit PowerPC chip in testing called "lstar". Not POWER but PowerPC. Could this be the code name for the mini POWER4?
The really big difference here is that this is all based on information straight from IBM. In October we're going to get a lot more information, hopefully including a timeline.
That this PowerPC will be 8-way superscalar is simply amazing... I was just reading some of AMD's specs on their Hammer and it is only 3-way superscalar (backed by 9 execution units). This means that at the same clock rate the IBM chip can dispatch 2.67 times as many instructions! Now if it can't get them from memory fast enough, or if there aren't enough execution units to feed them to, this won't amount to anything... but it certainly has a lot of potential. It could be (if there are enough execution units) that at 2GHz this thing could seriously outperform a 4 GHz Hammer. I'd argue that between an "equivalent" (i.e. they can process an equal number of instructions per second, have the same memory bandwidth, etc) PowerPC and x86-64, the PowerPC will get significantly more work done -- the instruction set is substantially better and it has far more registers. And with a much lower clock rate the PowerPC will likely run cooler. I can't wait to hear more about this beast IBM is building. :eek: </strong><hr></blockquote>
I also want to find out out more. I looked over the Power4 specs., and whilst it is 8 way superscalar, in that it can process 8 instructions per cycle, it can only complete (and I think issue) 5, as opposed to Hammer's 3. The true advantage is not as great as it might appear, and there are considerable limitations on how these 5 instructions can be combined, what the SIMD unit will do to this I don't know, it might have to replace instead of extend the execution units.
<strong>I also want to find out out more. I looked over the Power4 specs., and whilst it is 8 way superscalar, in that it can process 8 instructions per cycle, it can only complete (and I think issue) 5, as opposed to Hammer's 3. The true advantage is not as great as it might appear, and there are considerable limitations on how these 5 instructions can be combined, what the SIMD unit will do to this I don't know, it might have to replace instead of extend the execution units.</strong><hr></blockquote>
"Up to eight instructions can be issued each cycle, with a sustained completion rate of five instructions. Register rename pools and other outoforder resources coupled with the pipeline structure allow the design to have over 200 instructions in flight at any given time."
So you're right about the 8 issue vs 5 retire... seems odd, I wonder why they did that? Seems like the extra 3 issues are wasted. Perhaps this is so that the machine can quickly refill its pipelines after a branch misprediction? Nonetheless, 1.67 times more than the Hammer.
I too am very interested in the SIMD unit. I have a feeling, however, that it will be a full VMX implementation not some scheme which tries to reuse other processor resources.
"Up to eight instructions can be issued each cycle, with a sustained completion rate of five instructions. Register rename pools and other outoforder resources coupled with the pipeline structure allow the design to have over 200 instructions in flight at any given time."
So you're right about the 8 issue vs 5 retire... seems odd, I wonder why they did that? Seems like the extra 3 issues are wasted. Perhaps this is so that the machine can quickly refill its pipelines after a branch misprediction? Nonetheless, 1.67 times more than the Hammer. </strong><hr></blockquote>
I think it's because of instruction grouping, the Power4 issues instructions in groups of 5, within the group instructions can be out of order, but groups must execute in order, and one group is retired at a time. There are restrictions on what kind of instruction can go in each of the 5 slots of the group.
[quote]Originally posted by Programmer:
<strong>
I too am very interested in the SIMD unit. I have a feeling, however, that it will be a full VMX implementation not some scheme which tries to reuse other processor resources.</strong><hr></blockquote>
Oh yes, a full 128 bit VMX implementation, I just thought that they might have to lose some of the other execution units to make space in the issuing etc., but I hope not.
Comments
<strong>Maybe a 7470 or 7500 chip in Jan'. eg 7470 on proper DDR.</strong><hr></blockquote>
It has been stated the MPX bus won't go DDR before and I really see no reason to suspect that will change. The only way Powermacs will get a DDR bus is if th MPX bus is replaced. The most likely way Motorola will do that is an on-chip memory controller and RapidIO. I doubt we'll see that in Motorola's next revision though, which means late next year probably before you see that.
[quote]<strong>Thing is. Are Apple going Hyper or Rio? Are IBM going Rio or Hyper. I would have thought Rio. That would indicate a 7500 on Rio being Moto's last chip to take us through to next Summer...and IBM early 2004. Annoying.</strong><hr></blockquote>
IBM is a known supporter of RapidIO. Hypertransport really has other places on the board in my mind but I may be wrong.
[quote]<strong>Do Moto' think they can get the G4 2 gig and higher? Maybe they can. But I say they can sodding keep it...because it'll take them a couple of years to get there from now...</strong><hr></blockquote>
I'd suspect something along the lines of 1.5GHz then ~1.8GHz if Apple keeps the G4.
[quote]<strong>Jan' 2004 = IBM chip on Hypertransport?</strong><hr></blockquote>
I would suspect they use RIO if anything. Just wait until October and I suppose we'll know for certain.
[quote]<strong>[The current set up looks like a 'penultimate' topping out of the G4 to me. The G4 was supposed to top out at its current speed. No?</strong><hr></blockquote>
I'm really not sure where this comes from. It has been stated time and again the G4 has life left. Motorola didn't lie about a 167MHz FSB and they aren't lying about that. My suspicion is the next revision will probably be 1.5 GHz with a larger level 2 cache and finally on the 0.13 micron process.
But the POWER4 has a memory controller piggy backed on the L3 controller (or vice versa most likely) and IBM's bandwidth estimate might be
memory_controller_bandwidth + RIO bandwidth = 6.4GBps
I think this is the likely scenario. Being a forward thinking company, I would assume that IBM would have the BabyPOWER4 have an advanced memory interface like DDR-II 400 with 3.2GBps aggregate bandwidth (single channel) and that leaves 3.2GBps for peripheral devices like PCI-X bus(ses), firewire, Gb ethernet, multiple IDE interfaces, AGP 8X, etc. These peripherals would communicate with the processor(s) via RIO (a switched fabric).
A powermac based on this would look something like this:
[code]
PCI slots
____ ||||
=====\\____|CPU |_ |||| | AGP 8X
=====/ |____| | ____|___|_
RAM+L3 |________|PCI |--== ATA/1XX
____ | RIO |peripheral|
=====\\____|CPU |_|500MHz |__________|--= USB
=====/3.2 |____| 16bit | |
Gbps 3.2 Gb fire
Gbps eth. wire
</pre><hr></blockquote>
And better yet, it IBM implements 2 RIO busses on the processor, one can be dedicated to inter-processor communication. 16bit RIO only requires 70 odd pins or so.
<strong>Just for reference, the Sahara was introduced at the Microprocessor Forum last October, and then got into iBooks 7 months later this past May. At the conference, they said the Sahara would begin sampling in January. So we'll have to see when they say this new Power4 begins sampling - that may give us an idea as to when Apple could use it.</strong><hr></blockquote>
That is a good comparison allright, a previous IBM chip for Apple. One thing makes me doubt they will follow the same pattern however. A new G3 is not that big of a deal to most Mac users. A G5 for the PowerMac line is a huge deal. Everyone will be following this closely. If IBM says samples in January, folks can pretty much peg when Apple will come out with it. Now what would that do to Apple sales, say three to six months before the G5 ships? It is not like this is a speed bump. It is a big leap in performance. When everyone thinks a G5 is coming soon, few will buy a G4 PowerMac. IBM and Apple surely considered such customer reactions in making plans. Maybe I give them too much credit, but I don't think so. That is another reason I see an earlier introduction into the PowerMac.
Here is pure speculation, thinking of how the G5 might be introduced. It might ship very soon and appear in the top end of the PowerMac at a higher price. The G4 would keep selling at the lower end, as people see the distinction and many decide they do not need the G5's performance, and price. Fairly quickly, I would expect to see lower priced G5s with a lower clock rate moving down, and eventually into the lowest PowerMac. This would give a gentle ramp up to G5 production. The G5 would sell very well at the top end, and for a while keep the G4 selling in the lower end PowerMacs.
Okay, I admit I'm a wild optimist too, but this makes more sense to me than letting PowerMac customers see the G5 coming well in advance.
<strong>
<regarding use of the term "penultimate" w.r.t. the new G4s>
I'm really not sure where this comes from. It has been stated time and again the G4 has life left. Motorola didn't lie about a 167MHz FSB and they aren't lying about that. My suspicion is the next revision will probably be 1.5 GHz with a larger level 2 cache and finally on the 0.13 micron process.</strong><hr></blockquote>
[quote]
pe·nul·ti·mate Pronunciation Key (p-nlt-mt)
adj.
Next to last.
<hr></blockquote>
That is exactly what I meant -- we will probably see one more refinement of the G4 prior to Apple's adoption of the new IBM processor. A process shrink and larger L2 are the most likely candidates, although an on-chip memory controller & alternate bus (probably RIO) are an outside possibility. Topping out at 1.8 GHz according to what Motorola said a while back. MPX will not go DDR.
<strong>Just today I saw a paper on IBM's site that had a graph for RIO bandwidth. The 16 bit implementation running at 1GHz achieves 64Gbps, or about 8GBps, 25% more bandwidth than the 6.4GBps the BabyPOWER4 is supposed to deliver. A 500-700MHz implementation would deliver enough bandwidth for this chip and other components. </strong><hr></blockquote>
Its also worth noting that RIO has rougly 20-25% overhead due to packet headers and the like.
If it is G5 ready, that will qualify its looks...when it arrives...
The case seems to be dropping some hints to me...from what I've heard about the heat sink's size and all...
I'd love to see those Pentium 4 snail ad's...
Thought, now that Apple are openly using 'code names' for their OS...eg Jaguar. What chance we'll have a G5 'Hoover'....called something 'ard n' nasty?
'Cool Cat?'
Lemon Bon Bon
<strong>
That is exactly what I meant -- we will probably see one more refinement of the G4 prior to Apple's adoption of the new IBM processor. A process shrink and larger L2 are the most likely candidates, although an on-chip memory controller & alternate bus (probably RIO) are an outside possibility. Topping out at 1.8 GHz according to what Motorola said a while back. MPX will not go DDR.</strong><hr></blockquote>
With a process shrink, this gives some leeway on whet Motorola thinks would be useful for embedded applications; hopefully this is also in line with what would be useful for a desktop processor. For example, if they double the L2, and replace the L3 controller with a DDR memory controller, but keep MPX as the external bus, they can satisfy the embedded controller markets as well as the desktop (Apple) markets. Then even when Apple transitions the PowerMac to the BabyPOWER4, they will still have a processor to use with the PowerBook, iMac, and possibly iBook for some time to come.
<a href="http://www.eetimes.com/story/OEG20020805S0039"; target="_blank">let's hope so.</a>
Uncertain if this was the POWER4 group, or the POWER4-derived PPC group... but hints point at the latter.
<strong>
That is exactly what I meant -- we will probably see one more refinement of the G4 prior to Apple's adoption of the new IBM processor. A process shrink and larger L2 are the most likely candidates, although an on-chip memory controller & alternate bus (probably RIO) are an outside possibility. Topping out at 1.8 GHz according to what Motorola said a while back. MPX will not go DDR.</strong><hr></blockquote>
The current release will very likely be the penultimate one by choice rather than technical reasons. That's all I meant. I'm glad we agree on what's coming next though
ap
The POWER4 was designed to tackle some issues that IBM needed to take care of for a high performance modern CPU.
First issue was SMP optimization. They needed a CPU designed for high-throughput multitasking and the ability to handle multiple active processes. Secondly, the designed for a full-system design. They needed to redesign every bus in and out, every subsystem, for complete optimization and performance. Then they needed a highly scalable, high frequency design to deliver the best possible performance. Because, as we'll see later, total system performance depends on this point more so than before in traditional designs. They also needed RAS (Reliability, Availability, and Serviceability). They have included heavy duty ECC and redundant parts for this aspect, but much of it also has to do with total system design, but they made the processor much less prone to normal failures. And finally, compatibility with PowerPC be it either 32bit instructions or 64bit ones.
The POWER4 features 2 identical processor cores on one die. They each have an exclusive L1 (64KB instruction, 32KB data, ) cache and a unified 1.5MB of full speed L2 cache (256bit wide; 3 banks of 512KB each). L3 is on a separate chip and is controlled by a dedicated L3 controller and communicates with the external L3 at 128bits wide and at one third the processor speed (32MB maximum per module, but can be combines with the cache of other modules on the MCM to have a total of 128MB!). The POWER4 can also do out of order execution.
To communicate with other controllers and I/O, the POWER4 uses the GX bus. The GX bus is actually 2 32bit wide buses that operate at one third the processor speed also. Notice that all the buses so far will scale with processor frequency. As the processor gets faster, total system performance will scale proportionately, giving the system a better performance balance.
The POWER4 can issue up to 8 instructions per cycle (there are 8 execution units) with a sustained completion rate of 5 instructions. Each core has 2 double precision FPUs, 2 load/store units, 2 integer units, a beefy BPU for branch prediction, and another execution unit to perform logical operations on the condition register. The minimum penalty for a missed branch prediction is a loss of 12 cycles (12 pipeline stages) but the POWER4 has 16 pipeline stages. (This was difficult to determine but I found this obscure piece of information deep in an IBM research paper).
Memory management become tricky with the POWER4. Each processor can have an optional memory controller attached behind the L3 cache. On an IBM system the memory controller is actually attached to the memory card, and the controller is attached to the L3 eDRAM chip. Therefore maximum possible bandwidth to memory is only limited by the L3 cache limit. On a 1.3GHz POWER4 that is 6.933GBps. The memory controller attached to the L3 by means of 2 64bit buses, one in each direction, at one third the processor speed. The memory cards themselves use 400MHz (fixed frequency) DRAM memory chips with 2 bit ECC connected to memory controllers via 4 16bit bidirectional buses. This 400MHz DRAM gives you about... 6.4GBps.
IBM can connect 4 processors on one MCM to allow for 8 cores per MCM within the MCM they act like a switch. They can all share and snoop all the L3 cache (up to 128MB total). You can connect up to 4 of these MCMs to have a total of 32 cores in the system. All the MCMs in the system transfer data back and forth in a ring topology.
What a desktop version of the POWER4 may hold in store
First of all it would most likely have only one core in initial versions, but otherwise the core would be virtually identical to the one in the POWER4. Instead of 1.5MB of L2 cache, 3 banks of 256KB, or 768KB would be more likely.
The GX bus is overkill especially for something as simple at peripheral control. IBM is working on RapidIO implementations so it is likely they would have one RIO bus (16bit) to connect to the PCI bus/ ethernet/ firewire /etc. and one GX bus (at one quarter processor speed but this is best left to be a variable; 4:1, 5:1, 6:1 etc.) for inter-processor communication.
Since the L3 controller on the processor already support the memory access, you will need about 2-4MB of L3 cache (eDRAM) and to the cache a memory controller of Apple's choosing would interface with it. It can be anything since this approach is so flexible. Apple merely needs to create the interface. It can be DDR, DDR-II, RDRAM, QDR, whatever comes out in the future. The memory controller it self can house the eDRAM L3 cache to minimize design complexity on the motherboard.
Hope this bit of info helps.
2 months later I heard about Moto's 85xx embedded processor and feared this original G5 died with it's introduction. After the introduction of the G4 1Ghz MP powermac I thought the rumour about this particular G5 was a cruel tease of a friend of mine.
Now, 7 Months later this new IBM G5 processor appears as intended successor of the G4 and I am very currious about it's history: is this the same prototype my dear geek friend mentioned or is this something completly different. I know hardware testing is a long and painfull process espacially in this particular case with this "new" 64bit processor so I wonder; could this IBM power4light thing ended up a year ago in a prototype macintosh
or was it the cancelled 7500 from motorola?
[ 08-21-2002: Message edited by: gar ]</p>
<strong>It seems to me that once a year there are rumours about the next generation Powermac. About a year ago, I think it was october or november. I heard about a 64bit G5 prototype 1.6 Ghz MP with a 400Mhz FSB running a special version of Os X doing very fast tricks in the lowland.
2 months later I heard about Moto's 85xx embedded processor and feared this original G5 died with it's introduction. After the introduction of the G4 1Ghz MP powermac I thought the rumour about this particular G5 was a cruel tease of a friend of mine.
Now, 7 Months later this new IBM G5 processor appears as intended successor of the G4 and I am very currious about it's history: is this the same prototype my dear geek friend mentioned or is this something completly different. I know hardware testing is a long and painfull process espacially in this particular case with this "new" 64bit processor so I wonder; could this IBM power4light thing ended up a year ago in a prototype macintosh
or was it the cancelled 7500 from motorola?
</strong><hr></blockquote>
The really big difference here is that this is all based on information straight from IBM. In October we're going to get a lot more information, hopefully including a timeline.
That this PowerPC will be 8-way superscalar is simply amazing... I was just reading some of AMD's specs on their Hammer and it is only 3-way superscalar (backed by 9 execution units). This means that at the same clock rate the IBM chip can dispatch 2.67 times as many instructions! Now if it can't get them from memory fast enough, or if there aren't enough execution units to feed them to, this won't amount to anything... but it certainly has a lot of potential. It could be (if there are enough execution units) that at 2GHz this thing could seriously outperform a 4 GHz Hammer. I'd argue that between an "equivalent" (i.e. they can process an equal number of instructions per second, have the same memory bandwidth, etc) PowerPC and x86-64, the PowerPC will get significantly more work done -- the instruction set is substantially better and it has far more registers. And with a much lower clock rate the PowerPC will likely run cooler. I can't wait to hear more about this beast IBM is building. :eek:
<strong>
The really big difference here is that this is all based on information straight from IBM. In October we're going to get a lot more information, hopefully including a timeline.
That this PowerPC will be 8-way superscalar is simply amazing... I was just reading some of AMD's specs on their Hammer and it is only 3-way superscalar (backed by 9 execution units). This means that at the same clock rate the IBM chip can dispatch 2.67 times as many instructions! Now if it can't get them from memory fast enough, or if there aren't enough execution units to feed them to, this won't amount to anything... but it certainly has a lot of potential. It could be (if there are enough execution units) that at 2GHz this thing could seriously outperform a 4 GHz Hammer. I'd argue that between an "equivalent" (i.e. they can process an equal number of instructions per second, have the same memory bandwidth, etc) PowerPC and x86-64, the PowerPC will get significantly more work done -- the instruction set is substantially better and it has far more registers. And with a much lower clock rate the PowerPC will likely run cooler. I can't wait to hear more about this beast IBM is building. :eek: </strong><hr></blockquote>
Also consider that this will not be a MHz slouch. The POWER4 core has anywhere between 14 and 16 pipeline stages. Although less than the P4 this is more than the Hammer/Athlon. MHz is not the best way to measure performance, but add in the 8 way superscalar design and advanced branch predictor and you have a winning combination that will clock in slightly slower than the P4 but blow it completely away. Any real competition from Intel will come only from the Itanium2.
Off topic but still relevant :
<a href="http://researchweb.watson.ibm.com/journal/rd/462/shahidi.html"; target="_blank">http://researchweb.watson.ibm.com/journal/rd/462/shahidi.html</a>;
Interesting note that a version of the 604e was made on SOI and even booted MacOS.
<strong>
The really big difference here is that this is all based on information straight from IBM. In October we're going to get a lot more information, hopefully including a timeline.
That this PowerPC will be 8-way superscalar is simply amazing... I was just reading some of AMD's specs on their Hammer and it is only 3-way superscalar (backed by 9 execution units). This means that at the same clock rate the IBM chip can dispatch 2.67 times as many instructions! Now if it can't get them from memory fast enough, or if there aren't enough execution units to feed them to, this won't amount to anything... but it certainly has a lot of potential. It could be (if there are enough execution units) that at 2GHz this thing could seriously outperform a 4 GHz Hammer. I'd argue that between an "equivalent" (i.e. they can process an equal number of instructions per second, have the same memory bandwidth, etc) PowerPC and x86-64, the PowerPC will get significantly more work done -- the instruction set is substantially better and it has far more registers. And with a much lower clock rate the PowerPC will likely run cooler. I can't wait to hear more about this beast IBM is building. :eek: </strong><hr></blockquote>
I also want to find out out more. I looked over the Power4 specs., and whilst it is 8 way superscalar, in that it can process 8 instructions per cycle, it can only complete (and I think issue) 5, as opposed to Hammer's 3. The true advantage is not as great as it might appear, and there are considerable limitations on how these 5 instructions can be combined, what the SIMD unit will do to this I don't know, it might have to replace instead of extend the execution units.
michael
<strong>I also want to find out out more. I looked over the Power4 specs., and whilst it is 8 way superscalar, in that it can process 8 instructions per cycle, it can only complete (and I think issue) 5, as opposed to Hammer's 3. The true advantage is not as great as it might appear, and there are considerable limitations on how these 5 instructions can be combined, what the SIMD unit will do to this I don't know, it might have to replace instead of extend the execution units.</strong><hr></blockquote>
"Up to eight instructions can be issued each cycle, with a sustained completion rate of five instructions. Register rename pools and other outoforder resources coupled with the pipeline structure allow the design to have over 200 instructions in flight at any given time."
So you're right about the 8 issue vs 5 retire... seems odd, I wonder why they did that? Seems like the extra 3 issues are wasted. Perhaps this is so that the machine can quickly refill its pipelines after a branch misprediction? Nonetheless, 1.67 times more than the Hammer.
I too am very interested in the SIMD unit. I have a feeling, however, that it will be a full VMX implementation not some scheme which tries to reuse other processor resources.
<strong>
"Up to eight instructions can be issued each cycle, with a sustained completion rate of five instructions. Register rename pools and other outoforder resources coupled with the pipeline structure allow the design to have over 200 instructions in flight at any given time."
So you're right about the 8 issue vs 5 retire... seems odd, I wonder why they did that? Seems like the extra 3 issues are wasted. Perhaps this is so that the machine can quickly refill its pipelines after a branch misprediction? Nonetheless, 1.67 times more than the Hammer.
I think it's because of instruction grouping, the Power4 issues instructions in groups of 5, within the group instructions can be out of order, but groups must execute in order, and one group is retired at a time. There are restrictions on what kind of instruction can go in each of the 5 slots of the group.
[quote]Originally posted by Programmer:
<strong>
I too am very interested in the SIMD unit. I have a feeling, however, that it will be a full VMX implementation not some scheme which tries to reuse other processor resources.</strong><hr></blockquote>
Oh yes, a full 128 bit VMX implementation, I just thought that they might have to lose some of the other execution units to make space in the issuing etc., but I hope not.
Useful information on Power4 <a href="http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.pdf"; target="_blank">here</a>
michael