RapidIO in its current incarnation can do about 2 GB/sec, although it has room to grow. The 970 has aggregate bandwidth of 6.4 GB/sec (3.2 in each direction) at 1.8 GHz, and more as the clock rate climbs.</strong><hr></blockquote>
there you get an answer...</strong><hr></blockquote>
I was basing my number on a 16-bit wide 500 MHz implementation with 32-byte cache lines being the normally transfered data. This is 16 Gb/sec (== 2 GB/sec). If you consider that RIO will soon actually be shipping 1 GHz parts (?? I'm not sure ??) then they can do 4 GB/sec. The 1 GHz GPUL bus (for a hypothetical 2 GHz GPUL processor) will do 7.1 GB/sec.
To be fair the GPUL bus actually only does half its bandwidth in each direction, unlike the RIO which can actually get better than the quote numbers if operating unidirectionally. So if you have a case where the processor is either only outputting data or inputting data, then RIO will actually be faster in its high end configuration. This isn't a particularly interesting case, however, and the bi-directional case is far more important.
I was basing my number on a 16-bit wide 500 MHz implementation with 32-byte cache lines being the normally transfered data. This is 16 Gb/sec (== 2 GB/sec). If you consider that RIO will soon actually be shipping 1 GHz parts (?? I'm not sure ??) then they can do 4 GB/sec. The 1 GHz GPUL bus (for a hypothetical 2 GHz GPUL processor) will do 7.1 GB/sec.
To be fair the GPUL bus actually only does half its bandwidth in each direction, unlike the RIO which can actually get better than the quote numbers if operating unidirectionally. So if you have a case where the processor is either only outputting data or inputting data, then RIO will actually be faster in its high end configuration. This isn't a particularly interesting case, however, and the bi-directional case is far more important.</strong><hr></blockquote>
yes - you're absolutely right on this. my link to that page was for people like tiramisubomb (who asked) and shall in no way be a thing for you. i just clicked on 'reply' on the last message belonging to that topic... what i found interesting is that ibm is on the RapidIO trip too ;-)
First of all where did you see that it clocks at 450 DDR?
\tSecond, I was talking to an old friend that used to work for IBM this weekend. He had just come back from looking for another job with IBM. He had gone down to talk with some friends of his who still work in the Microprocessor devision of the company. They effectively told him that they could get him a job working on the new chip for Apple. That they needed a few extra guys on staff when they ramp up production next year. They were very straight forward with him on this subject. Although when question further about the this new chip they became secretive, especially toward the time of release etc. So, it really looks as if this chip is for apple. I mean I have no doubts any longer on the subject. We'll see the MPC7457 first though in Jan and then the 970 later toward the end of the year.
I was basing my number on a 16-bit wide 500 MHz implementation with 32-byte cache lines being the normally transfered data. This is 16 Gb/sec (== 2 GB/sec). If you consider that RIO will soon actually be shipping 1 GHz parts (?? I'm not sure ??) then they can do 4 GB/sec. The 1 GHz GPUL bus (for a hypothetical 2 GHz GPUL processor) will do 7.1 GB/sec.
To be fair the GPUL bus actually only does half its bandwidth in each direction, unlike the RIO which can actually get better than the quote numbers if operating unidirectionally. So if you have a case where the processor is either only outputting data or inputting data, then RIO will actually be faster in its high end configuration. This isn't a particularly interesting case, however, and the bi-directional case is far more important.</strong><hr></blockquote>
The IBM/RIO page also states the following:
Sustained Operations include all transaction overhead and assume fully loaded full duplex communications
1.\t32-byte Operation is 50% Efficient
2.\t256-byte Operation is >90% Efficient
For Unidirectional traffic 32-byte is >70% Efficient, 256-byte is >95% Efficient
My question is: _If_ they did go RapidIO-16bit, that ties up 76 pins. There isn't supposed to be a L3 cache. What in the bloody blazes are the other 500 of the 576 total pins for?
HyperTransport also doesn't tie up anywhere near that number of pins.
<strong>My question is: _If_ they did go RapidIO-16bit, that ties up 76 pins. There isn't supposed to be a L3 cache. What in the bloody blazes are the other 500 of the 576 total pins for?
HyperTransport also doesn't tie up anywhere near that number of pins.</strong><hr></blockquote>
Power supply.
IBM give a figure of 161 signal pins for the 970, I would expect about another 250-300 for power supply (the 7455 uses about 200 pins for power supplies). The remaining pins are probably unconnected, but might be used by other processors which might fit the same package, later.
Comments
<strong>
RapidIO in its current incarnation can do about 2 GB/sec, although it has room to grow. The 970 has aggregate bandwidth of 6.4 GB/sec (3.2 in each direction) at 1.8 GHz, and more as the clock rate climbs.</strong><hr></blockquote>
look here
<a href="http://www-3.ibm.com/chips/products/powerpc/newsletter/apr2001/tech-feat.html"; target="_blank">RapidIO on IBM's website</a>
there you get an answer...
<strong>
look here
<a href="http://www-3.ibm.com/chips/products/powerpc/newsletter/apr2001/tech-feat.html"; target="_blank">RapidIO on IBM's website</a>
there you get an answer...</strong><hr></blockquote>
I was basing my number on a 16-bit wide 500 MHz implementation with 32-byte cache lines being the normally transfered data. This is 16 Gb/sec (== 2 GB/sec). If you consider that RIO will soon actually be shipping 1 GHz parts (?? I'm not sure ??) then they can do 4 GB/sec. The 1 GHz GPUL bus (for a hypothetical 2 GHz GPUL processor) will do 7.1 GB/sec.
To be fair the GPUL bus actually only does half its bandwidth in each direction, unlike the RIO which can actually get better than the quote numbers if operating unidirectionally. So if you have a case where the processor is either only outputting data or inputting data, then RIO will actually be faster in its high end configuration. This isn't a particularly interesting case, however, and the bi-directional case is far more important.
<strong>
I was basing my number on a 16-bit wide 500 MHz implementation with 32-byte cache lines being the normally transfered data. This is 16 Gb/sec (== 2 GB/sec). If you consider that RIO will soon actually be shipping 1 GHz parts (?? I'm not sure ??) then they can do 4 GB/sec. The 1 GHz GPUL bus (for a hypothetical 2 GHz GPUL processor) will do 7.1 GB/sec.
To be fair the GPUL bus actually only does half its bandwidth in each direction, unlike the RIO which can actually get better than the quote numbers if operating unidirectionally. So if you have a case where the processor is either only outputting data or inputting data, then RIO will actually be faster in its high end configuration. This isn't a particularly interesting case, however, and the bi-directional case is far more important.</strong><hr></blockquote>
yes - you're absolutely right on this. my link to that page was for people like tiramisubomb (who asked) and shall in no way be a thing for you. i just clicked on 'reply' on the last message belonging to that topic... what i found interesting is that ibm is on the RapidIO trip too ;-)
then again <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
<strong>So now we're positive that the next Apple processor may or may not be coming from IBM.</strong><hr></blockquote>
Yep!!
<img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> something like that
\tSecond, I was talking to an old friend that used to work for IBM this weekend. He had just come back from looking for another job with IBM. He had gone down to talk with some friends of his who still work in the Microprocessor devision of the company. They effectively told him that they could get him a job working on the new chip for Apple. That they needed a few extra guys on staff when they ramp up production next year. They were very straight forward with him on this subject. Although when question further about the this new chip they became secretive, especially toward the time of release etc. So, it really looks as if this chip is for apple. I mean I have no doubts any longer on the subject. We'll see the MPC7457 first though in Jan and then the 970 later toward the end of the year.
Elio?
IBM Fishkill becomes operational at 130nm in mid-2003, moving to 90nm.
The PowerPC will start 130nm, moving to 90nm.
Q3 2003 seems like a reasonable date for the Power Mac G5.
Barto
<strong>
I was basing my number on a 16-bit wide 500 MHz implementation with 32-byte cache lines being the normally transfered data. This is 16 Gb/sec (== 2 GB/sec). If you consider that RIO will soon actually be shipping 1 GHz parts (?? I'm not sure ??) then they can do 4 GB/sec. The 1 GHz GPUL bus (for a hypothetical 2 GHz GPUL processor) will do 7.1 GB/sec.
To be fair the GPUL bus actually only does half its bandwidth in each direction, unlike the RIO which can actually get better than the quote numbers if operating unidirectionally. So if you have a case where the processor is either only outputting data or inputting data, then RIO will actually be faster in its high end configuration. This isn't a particularly interesting case, however, and the bi-directional case is far more important.</strong><hr></blockquote>
The IBM/RIO page also states the following:
Sustained Operations include all transaction overhead and assume fully loaded full duplex communications
1.\t32-byte Operation is 50% Efficient
2.\t256-byte Operation is >90% Efficient
For Unidirectional traffic 32-byte is >70% Efficient, 256-byte is >95% Efficient
HyperTransport also doesn't tie up anywhere near that number of pins.
(nice sentence structure, hey)
Only the one?
<strong>My question is: _If_ they did go RapidIO-16bit, that ties up 76 pins. There isn't supposed to be a L3 cache. What in the bloody blazes are the other 500 of the 576 total pins for?
HyperTransport also doesn't tie up anywhere near that number of pins.</strong><hr></blockquote>
Power supply.
IBM give a figure of 161 signal pins for the 970, I would expect about another 250-300 for power supply (the 7455 uses about 200 pins for power supplies). The remaining pins are probably unconnected, but might be used by other processors which might fit the same package, later.
michael