Intel touts power of upcoming Yonah laptop chip

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  • Reply 141 of 144
    Quote:

    Originally posted by melgross

    I don't think they can. But some makers will allow it.



    Mostly though, it's for desktops.



    I wonder if ATIaccelerator works for laptop gpu's? Anyone try it?




    yup! i get a 11-15% boost in gpu core and gpu mem on my (dad's) iBook g4 933mhz 32mb vram ati 9200 mobility... mmm mmm.... craptacular!!



    seriously though, ATIaccelerator2 is great, it works on laptop gpus definitely. you can feel the BURN as you hit 20% overclocks, then about 22-25% if you run openGL intensive stuff the video corrupts and then you have to reset to get everything back to normal.
  • Reply 142 of 144
    melgrossmelgross Posts: 33,570member
    Quote:

    Originally posted by sunilraman

    melgross, into overclocking? say it ain't so brotha...!!



    Geez, I'm not THAT conservative!
  • Reply 143 of 144
    thttht Posts: 5,530member
    Quote:

    Originally posted by Programmer

    The 60x bus couldn't really sustain more than ~250 MB/sec, IIRC. The MPX bus started at >750 MB/sec and is now up to >1.3 MB/sec. Sure it doesn't stand up to the Intel buses that came after, but for a while it was the fastest bus out there -- and that was while the 7400 was around and competitive. That was pretty major.



    I'm contending that the contemporary Pentium III bus performance at the same clock rate was still better, at least in some aspects such as burst performance. Also, when the 7400 was shipping in Power Mac G4, they shipped at 100 MHz FSB while Katmai B processors where at 133 MHz. I don't think you can claim fastest bus out there, yet.



    Quote:

    You are forgetting 1 cycle throughput vs. 2 on the G3. That means double the double precision performance. Adding a second FPU doubles it again, but I wouldn't ignore the first doubling.

    [deletia]

    Roughly the same, but I'm much more interested in FLOPS or bandwidth oriented operations.




    Went back and checked, and the architectural double precision improvement was even smaller than I thought. It was only DP multiplies that were improved. DP adds was the same as before. So, to explain the benchmarks, either Mac OS FPU apps consist of mostly adds and no multiplies, the 2 to 1 cycle multiply throughput wasn't really a big deal, or the documentation is in error. Moto never bothered to highlight the throughput improvement in any of their documentation. They did highlight the latency improvement, however.



    My bet is documentation error on the 2 cycle throughput.
  • Reply 144 of 144
    As I was going back and looking at the documentation it struck me that this is a funny discussion to be having now...



    Quote:

    Originally posted by THT

    I'm contending that the contemporary Pentium III bus performance at the same clock rate was still better, at least in some aspects such as burst performance. Also, when the 7400 was shipping in Power Mac G4, they shipped at 100 MHz FSB while Katmai B processors where at 133 MHz. I don't think you can claim fastest bus out there, yet.



    In terms of peak bandwidth you are correct, but not in terms of sustainable bandwidth. My experience using the G3, G4, and P1..3 was that the G4 turned in the best sustainable bandwidth (which is more important than peak rates) until DDR arrived. And MPX had better latencies (still do, I believe -- probably bested only by AMD's on-chip MC).



    Quote:

    Went back and checked, and the architectural double precision improvement was even smaller than I thought. It was only DP multiplies that were improved. DP adds was the same as before. So, to explain the benchmarks, either Mac OS FPU apps consist of mostly adds and no multiplies, the 2 to 1 cycle multiply throughput wasn't really a big deal, or the documentation is in error. Moto never bothered to highlight the throughput improvement in any of their documentation. They did highlight the latency improvement, however.



    The double precision multiply is given a rate of 2-1-1 which means that it sits in the first of the three pipeline stages for 2 cycles, preventing the following instruction from entering stage one until 2 cycles later. In typical FPU code I've found that many of the adds end up done as part of the fused multiply-add instruction, which reduces the importance of the add speed.



    I've got a Motorola document that lists all the changes 750->7400.
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