But in Xserves there are a total of two (2) expansion slots, and if you want any type of video out, you use a slot, thereby losing half of your expansion capabilities…
Sorry; there's a little terminology confusion here. Usually "integrated" graphics are in the northbridge, while "discrete" graphics are a separate chip. But discrete graphics don't have to take up a slot; I predict Apple will put a discrete graphics chip on the Intel Xserve motherboard, leaving all the slots free.
Not really all that necessary; it barely beats Opteron in some benchmarks, and it beats it by an OK maring in others. Considering that Opteron is using slower memory, is clocked lower, and is expected to move to a 65nm process soon, it's not that impressive.
What is impressive is seeing Intel admit their mistake with NetBurst and move on. To greener pastures.
Not really all that necessary; it barely beats Opteron in some benchmarks, and it beats it by an OK maring in others. Considering that Opteron is using slower memory, is clocked lower, and is expected to move to a 65nm process soon, it's not that impressive.
What is impressive is seeing Intel admit their mistake with NetBurst and move on. To greener pastures.
Actually, according to the tests, and the description, that's not true.
first of All, there is this:
" there is still a lot of performance left on the table for Woodcrest. Current compilers, JVMs and applications have not been optimized for Woodcrest, and our system is using slower FBD-533 memory, rather than FBD-667."
Jon's conclusion, after much ado, is what matters in his article:
"In sum, when the more integer-intensive benchmarks start coming out, you should expect to see Woodcrest's lead over Opteron widen, AM2 or no AM2. Also, Woodcrest has much stronger SSE hardware, so its vector performance should be significantly higher than Opteron for properly optimized SSE code."
And, don't get into the MHz myth again. They are different designs. The actual clock speed doesn't matter. Power 5 is also clocked slower, so what?
Actually, according to the tests, and the description, that's not true.
From your own source:
Quote:
As background, TR's review pit a 3.0GHz Woodcrest system against a 2.6GHz Opteron system. Woodcrest's lead in a few of the tests was spectacular, but for the most part it ranged from "solid" to "impressive." The results were perhaps a little less awe-inspiring than some would expect, given Woodcrest's 400MHz clockspeed advantage over Opteron, and the fact that the Woodcrest system sported faster FB-DIMMs (compare the Opteron system's 400MHz DDR memory).
Quote:
Jon's conclusion, after much ado, is what matters in his article
The conclusion is only as important as the body itself.
Quote:
And, don't get into the MHz myth again.
Your own source uses the MHz "myth" (don't use Jobs' marketing BS please!) as a point of comparison.
Quote:
They are different designs. The actual clock speed doesn't matter.
Sure, but Core Solo, Pentium M, Athlon XP and Pentium 4 are all part of the same architecture too. Yet a 1.6 GHz Core Solo is faster than a 1.6 GHz Pentium M, which is faster than a 1.6 GHz Athlon XP, which is faster than a 1.6 GHz Pentium 4. Same amount of cores (one). Same architecture (x86). Same clock speed (1.6 GHz). Yet, awfully large differences. Of course, front-side bus and cache size play a large role, but that's hardly all there is to it. If they all had a 100 MHz bus and 512 KB of L2 cache (and no L3 cache), the Core Solo would likely still be fastest.
The problem with Woodcrest (and what's going to delegate it to the workstation class machines) is the Front Side Bus. It took the Pentium 4 something like...400 clocks to fill the L2. The Opteron does it in under 10. HyperTransport is much more scaleable then the 50 year old FSB design and Intel needs to realize that, join the HT consortium, and throw it into Core 3. Woodcrest looks like a very viable Power Mac replacement chip though.
The problem with Woodcrest (and what's going to delegate it to the workstation class machines) is the Front Side Bus. It took the Pentium 4 something like...400 clocks to fill the L2. The Opteron does it in under 10. HyperTransport is much more scaleable then the 50 year old FSB design and Intel needs to realize that, join the HT consortium, and throw it into Core 3. Woodcrest looks like a very viable Power Mac replacement chip though.
FSB isn't the issues. Woodcrest uses a DiB (Dual Independent Bus) the L2 cache is 4 or 8MB and ondie running at cpu speed. The FSB of Woodcrest has been cranked up to 1333Mhz.
Intel has CSI which is their Hypertransport like product. Frankly ondie memory controllers are wonderful if your applications are sensitive to memory latency but if you just need bandwidth a fast FSB is fine and allows for updating the controller a lot easier.
so far, even the DDR2 socket designs have shown no improvement from the increased memory speeds, so it doesn't matter. As the Woodcrests were using slower memory then they can, even though it was faster than that in the Opterons, it more than balances out.
Quote:
The conclusion is only as important as the body itself.
You should have read the articles he linked to.
Quote:
Your own source uses the MHz "myth" (don't use Jobs' marketing BS please!) as a point of comparison.
True, but, again read the other articles.
Quote:
They are both part of the same architecture.
But not the same designs. What is the speed of the Zeons that the Opterons were beating? And what was their speed? Different designs, and not totally the same architecture either. Netburst was very different from the Opterons. The new Core design is closer to the way AMD has been doing things, but with several advantages, as was noted. As was also noted in the links, that Woodcrest has a way to go in performance improvement. It has much more "leg" than the K8, which is reaching its limits.
FSB isn't the issues. Woodcrest uses a DiB (Dual Independent Bus) the L2 cache is 4 or 8MB and ondie running at cpu speed. The FSB of Woodcrest has been cranked up to 1333Mhz.
Intel has CSI which is their Hypertransport like product. Frankly ondie memory controllers are wonderful if your applications are sensitive to memory latency but if you just need bandwidth a fast FSB is fine and allows for updating the controller a lot easier.
With that much L2 on a server, you run the risk of cache thrashing, which will severely limit the life of the processor. Hypertransport is pretty much useless with one processor, but 2+ processors really shows its strength. Processor 1<->Processor 2 is much faster then Processor 1 <-> Northbridge <-> Processor 2.
With that much L2 on a server, you run the risk of cache thrashing, which will severely limit the life of the processor. Hypertransport is pretty much useless with one processor, but 2+ processors really shows its strength. Processor 1<->Processor 2 is much faster then Processor 1 <-> Northbridge <-> Processor 2.
That's a new one. Where did you read that a large cache gives problems with cache thashing? normally, it a cache that's too small that has that problem. Besides, if the look ahead which determines what will be in the cache is good, these problems won't occur. What does this have to do with the life of the CPU?
That's a new one. Where did you read that a large cache gives problems with cache thashing? normally, it a cache that's too small that has that problem. Besides, if the look ahead which determines what will be in the cache is good, these problems won't occur. What does this have to do with the life of the CPU?
Agreed, cache thrashing is too little cache, hitting the cache before memory and never getting anything because nothing valuable is stored in cache. Only downfall of too much cache is it starts to take too long to go through the cache to make sure what the cpu is looking for isn't in there. Which of course beats the purpose of cache...... since it's supposed to be extremely quick.
Agreed, cache thrashing is too little cache, hitting the cache before memory and never getting anything because nothing valuable is stored in cache. Only downfall of too much cache is it starts to take too long to go through the cache to make sure what the cpu is looking for isn't in there. Which of course beats the purpose of cache...... since it's supposed to be extremely quick.
The whole point to cache is that is is much faster than main memory. It also doesn't have the delays associated with having to go to main memory. The information in cache is known, so the cpu doesn't have to search through the cache to find what it wants. It just gets it. Very little delay involved.
But, what about the statement that it leads to a shortened cpu life?
Comments
Originally posted by emig647
there isn't a clean way to say... use xx percent of the gpu vs. cpu when creating this image. It basically does all of that for you.
I'm in a rush but I just wanted to say
I said that..
"Doesn't the lib determine what percentages can, or need to be offloaded in other similar situations already?"
Originally posted by MacRonin
But in Xserves there are a total of two (2) expansion slots, and if you want any type of video out, you use a slot, thereby losing half of your expansion capabilities…
Sorry; there's a little terminology confusion here. Usually "integrated" graphics are in the northbridge, while "discrete" graphics are a separate chip. But discrete graphics don't have to take up a slot; I predict Apple will put a discrete graphics chip on the Intel Xserve motherboard, leaving all the slots free.
http://www.realworldtech.com/forums/...7567&roomid=11
SpecIntBase
970MP @ 2.5GHz - 1539
Woodcrest @3GHz- 3012
SpecFPBase
970MP @ 2.5GHz - 1906
Woodcrest @3GHz- 2783
SpecIntRateBase (2 socket)
970MP - 64.2
Woodcrest - 123
SpecFPRateBase (2 socket)
970MP - 56.1
Woodcrest - 83
Looks like Apple will be touting a 2X performance improvement.
Originally posted by wmf
Here are some quad Woodcrest vs. quad G5 numbers:
http://www.realworldtech.com/forums/...7567&roomid=11
Looks like Apple will be touting a 2X performance improvement.
Looks like I will be too.
Originally posted by onlooker
Looks like I will be too.
Did you see the dicussion? Was that the real Linus Torvalds? And he likes it, he really likes it.
Originally posted by wmf
Here are some quad Woodcrest vs. quad G5 numbers:
http://www.realworldtech.com/forums/...7567&roomid=11
Looks like Apple will be touting a 2X performance improvement.
Will a 3 ghz Conroe then be basically about the same as a Quad g5 performance wise?
IBwhat? Whatscale? P.What Semi? I can't hear nuthin'...I've got this quad-Woodcrest screaming here.
Originally posted by kim kap sol
Oh shiii...I'd better get some ear plugs so I don't hear the quad-Woodcrest screaming.
IBwhat? Whatscale? P.What Semi? I can't hear nuthin'...I've got this quad-Woodcrest screaming here.
Make sure they aren't cheap ones.
http://arstechnica.com/news.ars/post/20060524-6898.html
Originally posted by backtomac
Did you see the dicussion? Was that the real Linus Torvalds? And he likes it, he really likes it.
Yep, that's him alright. First time I see him posting outside kernel mailing lists. Quite... interesting.
Woodcrest is shaping up to be pretty impressive indeed.
Originally posted by melgross
Make sure they aren't cheap ones.
http://arstechnica.com/news.ars/post/20060524-6898.html
Not really all that necessary; it barely beats Opteron in some benchmarks, and it beats it by an OK maring in others. Considering that Opteron is using slower memory, is clocked lower, and is expected to move to a 65nm process soon, it's not that impressive.
What is impressive is seeing Intel admit their mistake with NetBurst and move on. To greener pastures.
Originally posted by Gene Clean
Not really all that necessary; it barely beats Opteron in some benchmarks, and it beats it by an OK maring in others. Considering that Opteron is using slower memory, is clocked lower, and is expected to move to a 65nm process soon, it's not that impressive.
What is impressive is seeing Intel admit their mistake with NetBurst and move on. To greener pastures.
Actually, according to the tests, and the description, that's not true.
first of All, there is this:
" there is still a lot of performance left on the table for Woodcrest. Current compilers, JVMs and applications have not been optimized for Woodcrest, and our system is using slower FBD-533 memory, rather than FBD-667."
Jon's conclusion, after much ado, is what matters in his article:
"In sum, when the more integer-intensive benchmarks start coming out, you should expect to see Woodcrest's lead over Opteron widen, AM2 or no AM2. Also, Woodcrest has much stronger SSE hardware, so its vector performance should be significantly higher than Opteron for properly optimized SSE code."
And, don't get into the MHz myth again. They are different designs. The actual clock speed doesn't matter. Power 5 is also clocked slower, so what?
Originally posted by melgross
Actually, according to the tests, and the description, that's not true.
From your own source:
As background, TR's review pit a 3.0GHz Woodcrest system against a 2.6GHz Opteron system. Woodcrest's lead in a few of the tests was spectacular, but for the most part it ranged from "solid" to "impressive." The results were perhaps a little less awe-inspiring than some would expect, given Woodcrest's 400MHz clockspeed advantage over Opteron, and the fact that the Woodcrest system sported faster FB-DIMMs (compare the Opteron system's 400MHz DDR memory).
Jon's conclusion, after much ado, is what matters in his article
The conclusion is only as important as the body itself.
And, don't get into the MHz myth again.
Your own source uses the MHz "myth" (don't use Jobs' marketing BS please!) as a point of comparison.
They are different designs. The actual clock speed doesn't matter.
They are both part of the same architecture.
Power 5 is also clocked slower, so what?
Different architecture - different rules.
Originally posted by Gene Clean
They are both part of the same architecture.
Sure, but Core Solo, Pentium M, Athlon XP and Pentium 4 are all part of the same architecture too. Yet a 1.6 GHz Core Solo is faster than a 1.6 GHz Pentium M, which is faster than a 1.6 GHz Athlon XP, which is faster than a 1.6 GHz Pentium 4. Same amount of cores (one). Same architecture (x86). Same clock speed (1.6 GHz). Yet, awfully large differences. Of course, front-side bus and cache size play a large role, but that's hardly all there is to it. If they all had a 100 MHz bus and 512 KB of L2 cache (and no L3 cache), the Core Solo would likely still be fastest.
Originally posted by theapplegenius
The problem with Woodcrest (and what's going to delegate it to the workstation class machines) is the Front Side Bus. It took the Pentium 4 something like...400 clocks to fill the L2. The Opteron does it in under 10. HyperTransport is much more scaleable then the 50 year old FSB design and Intel needs to realize that, join the HT consortium, and throw it into Core 3. Woodcrest looks like a very viable Power Mac replacement chip though.
FSB isn't the issues. Woodcrest uses a DiB (Dual Independent Bus) the L2 cache is 4 or 8MB and ondie running at cpu speed. The FSB of Woodcrest has been cranked up to 1333Mhz.
Intel has CSI which is their Hypertransport like product. Frankly ondie memory controllers are wonderful if your applications are sensitive to memory latency but if you just need bandwidth a fast FSB is fine and allows for updating the controller a lot easier.
Originally posted by Gene Clean
From your own source:
so far, even the DDR2 socket designs have shown no improvement from the increased memory speeds, so it doesn't matter. As the Woodcrests were using slower memory then they can, even though it was faster than that in the Opterons, it more than balances out.
The conclusion is only as important as the body itself.
You should have read the articles he linked to.
Your own source uses the MHz "myth" (don't use Jobs' marketing BS please!) as a point of comparison.
True, but, again read the other articles.
They are both part of the same architecture.
But not the same designs. What is the speed of the Zeons that the Opterons were beating? And what was their speed? Different designs, and not totally the same architecture either. Netburst was very different from the Opterons. The new Core design is closer to the way AMD has been doing things, but with several advantages, as was noted. As was also noted in the links, that Woodcrest has a way to go in performance improvement. It has much more "leg" than the K8, which is reaching its limits.
[/QUOTE]
Originally posted by hmurchison
FSB isn't the issues. Woodcrest uses a DiB (Dual Independent Bus) the L2 cache is 4 or 8MB and ondie running at cpu speed. The FSB of Woodcrest has been cranked up to 1333Mhz.
Intel has CSI which is their Hypertransport like product. Frankly ondie memory controllers are wonderful if your applications are sensitive to memory latency but if you just need bandwidth a fast FSB is fine and allows for updating the controller a lot easier.
With that much L2 on a server, you run the risk of cache thrashing, which will severely limit the life of the processor. Hypertransport is pretty much useless with one processor, but 2+ processors really shows its strength. Processor 1<->Processor 2 is much faster then Processor 1 <-> Northbridge <-> Processor 2.
Originally posted by theapplegenius
With that much L2 on a server, you run the risk of cache thrashing, which will severely limit the life of the processor. Hypertransport is pretty much useless with one processor, but 2+ processors really shows its strength. Processor 1<->Processor 2 is much faster then Processor 1 <-> Northbridge <-> Processor 2.
That's a new one. Where did you read that a large cache gives problems with cache thashing? normally, it a cache that's too small that has that problem. Besides, if the look ahead which determines what will be in the cache is good, these problems won't occur. What does this have to do with the life of the CPU?
Originally posted by melgross
That's a new one. Where did you read that a large cache gives problems with cache thashing? normally, it a cache that's too small that has that problem. Besides, if the look ahead which determines what will be in the cache is good, these problems won't occur. What does this have to do with the life of the CPU?
Agreed, cache thrashing is too little cache, hitting the cache before memory and never getting anything because nothing valuable is stored in cache. Only downfall of too much cache is it starts to take too long to go through the cache to make sure what the cpu is looking for isn't in there. Which of course beats the purpose of cache...... since it's supposed to be extremely quick.
Originally posted by emig647
Agreed, cache thrashing is too little cache, hitting the cache before memory and never getting anything because nothing valuable is stored in cache. Only downfall of too much cache is it starts to take too long to go through the cache to make sure what the cpu is looking for isn't in there. Which of course beats the purpose of cache...... since it's supposed to be extremely quick.
The whole point to cache is that is is much faster than main memory. It also doesn't have the delays associated with having to go to main memory. The information in cache is known, so the cpu doesn't have to search through the cache to find what it wants. It just gets it. Very little delay involved.
But, what about the statement that it leads to a shortened cpu life?