There is no G5

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  • Reply 81 of 456
    qaziiqazii Posts: 305member
    [quote]Originally posted by suckfuldotcom:

    <strong>



    Ok, so the standards for 8xxx-ness are:



    -10+ stage pipeline



    and at least some of the following:



    -64 bit implementation w/32 bit backwards compatibility

    -new bus topology

    -DDRRAM support

    -faster bus

    -extensible architecture



    How many is 'some'? I'm gonna say it should be at least 4 of them, just because the must column is so short.



    Whaddya think?



    SdC</strong><hr></blockquote>



    Since you're just talking about the processor, why do you care about the bus, DDRRAM, etc.? You could see a Apollo-based Power Mac with those things, or a G5 without them (remember Yikes?).



    Does the computer have to be shipping? Or just announced?



    I would suggest you decide on your dispute-resolution panel now...otherwise you may argue on who is on it after the questionable machine has been released. You would both naturally want people who would agree with you in the unlikely case that the Mac community cannot agree whether it is a G5.



    [quote]<strong>

    Ok, so the standards for 8xxx-ness are:

    </strong><hr></blockquote>

    Unless I am mistaken, I believe the 8 is supposed to refer to an embedded market processor. In other words, 84xx would be an embedded version of the G4. The G5, I believe, was the 75xx before the it was changed to 85xx. Perhaps this was part of Apple's campaign to cover up evidence. Apple's G5 MIGHT be a 75xx. Thus, maybe you should specify x5xx instead of 8xxx.



    Other possible criteria:

    # of pins

    # of transistors

    fabrication process (according to geek.com Apollo is .15 while G5 is .13)

    power used

    speed (After all, isn't this really what matters? I'm not talking clock speed; I'm talking speed by some objective standard, such as SpecInt/SpecFP)



    [ 01-10-2002: Message edited by: qazII ]</p>
  • Reply 82 of 456
    slackerslacker Posts: 127member
    qazII,



    I agree that there are other things to be looked at to tell the difference between a G4 and a G5. That's why I'm not overly concerned about setting down more ground rules, I think when it's released we'll all now if we've been had or not.



    The G5 should be so obviously different from a G4 (even Apollo) that there isn't much debate. As for setting up a panel, I don't think it will havve to come to that but if it does we can submit names to each other or maybe let the site admins pick.



    As I said before I can't hold him to his word, If I win and he doesn't pay I'm not going to track him down and beat him up. Just like no one knows if I'm the type of person who'll keep their word and pay up. I will pay up, but you have no way of verifying that or putting any credibility to it. So it's just my word and his word. I like to think my word is worth something and if I lose when I pay up you will all have to respect for at least being an honest person (maybe not that bright, but honest).
  • Reply 83 of 456
    programmerprogrammer Posts: 3,457member
    Well Epson certainly thinks the G5 exists.
  • Reply 84 of 456
    moogsmoogs Posts: 4,296member
    I think they hired Ed Hamrick and we just haven't heard about it yet.
  • Reply 85 of 456
    I just had a thought (no, its not that lonely!)...



    Please bear with me for a moment, and hold your objections. Suppose for a moment that on Feb 19, Apple introduces a new line of towers. One or two low-end Apollo based machines, and one or two mid-range G5 based machines. Shipping immediately. Lets say they're as fast as the rumours have suggested -- 6-8 times faster than the current top-of-the-line. Wow. We're all shocked and increadibly pleased (except for the I-told-you-so's, and the never-quite-good-enoughs)...



    ... and then the reality hits us. Everybody wants one. Or two. Or more. Apple will be buried with orders. And I mean buried... swamped, smothered, overwhelmed. There's no way they could keep up with production, especially of the CPU. Wait times are going to be months long. The backlog will make all previous backlogs look like instant shipping.



    Apple knows this and it'll have to do a couple things to mitigate this logistical nightmare:



    - Price the G5s higher. Much higher.

    - No MP G5s.

    - Push the intro (and announcement) back as long as possible to get the biggest production run at it they can (hence no MWSF intro).

    - Intro G4 models at higher clock rates to attact some buyers away from the G5. These would have to be MP models if they can get enough of the new Apollos.





    See you in line at the AppleStore...
  • Reply 86 of 456
    jrcjrc Posts: 817member
    [quote]Originally posted by Programmer:

    <strong>I just had a thought (no, its not that lonely!)...



    Please bear with me for a moment, and hold your objections. Suppose for a moment that on Feb 19, Apple introduces a new line of towers. One or two low-end Apollo based machines, and one or two mid-range G5 based machines. Shipping immediately. Lets say they're as fast as the rumours have suggested -- 6-8 times faster than the current top-of-the-line. Wow. We're all shocked and increadibly pleased (except for the I-told-you-so's, and the never-quite-good-enoughs)...



    ... and then the reality hits us. Everybody wants one. Or two. Or more. Apple will be buried with orders. And I mean buried... swamped, smothered, overwhelmed. There's no way they could keep up with production, especially of the CPU. Wait times are going to be months long. The backlog will make all previous backlogs look like instant shipping.



    Apple knows this and it'll have to do a couple things to mitigate this logistical nightmare:



    - Price the G5s higher. Much higher.

    - No MP G5s.

    - Push the intro (and announcement) back as long as possible to get the biggest production run at it they can (hence no MWSF intro).

    - Intro G4 models at higher clock rates to attact some buyers away from the G5. These would have to be MP models if they can get enough of the new Apollos.





    See you in line at the AppleStore...</strong><hr></blockquote>



    I think that's EXACTLY what they should do. This might fit into a lot of people's "If only they had a prosumer machine" category. Mine included.



    Only problem is the iMac pricing/features overlap with a potential machine like that, IMO. I still think they should have $1,500 or lower models. This would create a little dilemma for some folks that are eyeing that price range and might not be able to make a decision between iMac/small tower.



    But, it'd be a quandry I'd love to be in right now.
  • Reply 87 of 456
    bungebunge Posts: 7,329member
    I think it would be difficult to have a sub $1500 MP G4 machine. Granted, if the speed difference between a single G5 and an MP G4 is great enough, then the products would work, although I don't know about the pricing.



    If the pricing worked out that way, Apple would sell more machines than they could make.



    This dual pro strategy is something I've been thinking about. With Avid users leaning towards FCP and Maya users moving to the Mac, there's headroom for high pricing on super fast machines. If they can cluster or rackmount all the better.



    If people are spending 10s of thousands of dollars on solutions right now, why sell them a top of the line PowerMac for $3500? They're obviously willing to pay for speed, so make a $5000 model MP G5. I doubt it would have to sell much to recoup the R & D.
  • Reply 88 of 456
    If Apple can sell a G4 800 with an LCD and Superdrive for $1799, then you'd imagine that the next Powermac series might look something like this (assumes some kind of G5 is available soon, which I'm not sure I believe):



    $1599 - dual G4 867

    $2499 - dual G4 1000

    $3499 - some kinda G5



    Plenty of people would pay the premium for the "next gen" chip, and those that didn't want to go that far could still get a machine at the entry level that's faster than the fastest Powermac is now.
  • Reply 89 of 456
    Oh, and I do agree that there would be a market for a $5000+ machine that had a truly high-end capability, whether this was quad-Apollo, dual G5, octo-G3, or who knows what. Apple wouldn't even have to market it to the general public. They could treat it like their servers, and not really announce or market it, because the people who need one wouldn't be browsing at CompUSA for one -- they'd check online.
  • Reply 90 of 456
    I really don't see a conflict if the prices of the low end power mac are less than the high end iMac. You still have to buy a monitor for the PMac. There are lots of arguments to go either way. Low end PMac is expandable, processor upgradeable, PCI cards, etc.... Very nice, but the iMac high end has superdrive. What do you really want in a computer? I've always opted for PMacs for upgrade ability and expandability, but I think the top of the line iMac with superdrive might be the way to go (if I were to buy one today, but I'm waiting for the G5).



    But if you need those PCI slots you get the PowerMac, I just think most people will stick with what they need. Did this make any sense probably not.
  • Reply 91 of 456
    outsideroutsider Posts: 6,008member
    Programmer, I agree with your post. I was just stating that the G5 will have at least the same processing parity with the G4... if not higher. Another thing is there is nothing wrong with increasing the pipeline... as long as you beef up the BPU. If the BPU is only 95% accurate you will notice the difference if you use a similar MHz machine with a BPU that is 99.5% accurate. By devoting more transistors to the BPU you can get away with lenghtening the pipeline to 12, 14, 20, 40 stages as long as you devote more and more resources to the BPU. I can picture future processors with dozens (40 to 100) of pipeline stages and half the CPU transistors devoted to Branch prediction. We'd measure a BPU with how many places of 9's it's accurate. A 7-9 precision BPU would be 99.99999% accurate. We already measure server uptime like that.
  • Reply 92 of 456
    I don't think it's the end of the world if the top iMac costs more than the lowest Powermac, as you say. The problem now is not this price overlap but the fact that the top iMac is cheaper and more powerful than the bottom Powermac+LCD. In other words, it's the fact that the price/performance ratio of the iMac is so much better than that of the Powermac.



    As mentioned in another thread, it's similar to the time Apple released the iBook SE which was at least as good as the entry level G3 Powerbook, and much cheaper. Most people wouldn't buy a $2499 Powerbook when you can get a $1799 iBook that's faster.
  • Reply 93 of 456
    [quote]Originally posted by Outsider:

    <strong>Another thing is there is nothing wrong with increasing the pipeline... as long as you beef up the BPU. If the BPU is only 95% accurate you will notice the difference if you use a similar MHz machine with a BPU that is 99.5% accurate. By devoting more transistors to the BPU you can get away with lenghtening the pipeline to 12, 14, 20, 40 stages as long as you devote more and more resources to the BPU. I can picture future processors with dozens (40 to 100) of pipeline stages and half the CPU transistors devoted to Branch prediction. We'd measure a BPU with how many places of 9's it's accurate. A 7-9 precision BPU would be 99.99999% accurate. We already measure server uptime like that.</strong><hr></blockquote>



    I disagree with that... the longer it takes to propogate through the pipeline the bigger your problems of data inter-dependency between instructions become. And branch prediction cannot get as good as you seem to think it can -- current BPUs in the Intel chips are about as good as its worth doing. Some code is predictable, and that code is now being predicted. Other code is not predictable, and it will never be predicted. We profile our code a great deal and some of it branch predicts nicely (typically signal processing style algorithms which are crunching long data arrays), but some of it just sucks and its here that the long pipeline machines just have a hard time with it. The P4 is great at signal processing (audio, video, 3D graphics, image processing, etc), but on intense logic its not so good.



    Good engineering solutions are rarely at one extreme or the other, and so it is in this case. Pipelines should get longer, but not extremely so.



    I think we'll see higher speeds in the future from better process technologies, and multi-core or hyper-threading type approaches. Asynchronously clocked chips are also being developed where there isn't one clock for the entire chip, and I think these hold a lot of promise.



    [ 01-11-2002: Message edited by: Programmer ]</p>
  • Reply 94 of 456
    outsideroutsider Posts: 6,008member
    Yes but how about extremely long pipelines with trap doors. When a particular instruction is done it can exit the pipeline at any given stage or be moved up several stages if there is a bubble. Some instructions won't use and the stages in a pipeline so it should be able to warp ahead to the stage that it can use.



    Also how about incorporating multiple pipeline stages and register sets. Not only one or two but 4 or 8. As long as you have enough execution units (say 5-6 integer units and 3-4 FPU units).



    Also about BPU design, I read somewhere baout IBM using AI to help improve predictions to almost 100% by using stored information and a learning feature.
  • Reply 95 of 456
    sizzle chest:



    I agree with you, but this is where the choice needs to be made. Will you be happy with a G4 iMac that you can't upgrade the chip (maybe in the future, we'll see when someone guts one) and you can't upgrade video, add 2nd monitor (except mirroring), No PCI cards.



    Do you need the flexibility or not? If not by all means get that iMac, otherwise the PMac.



    I've got a 7600 running with more add on equipment than it originally came with. At one point I had an OrangePC 620 compatibility card to run windows in it (anyone want to buy it?). Now I have a ATI graphics with all the in/out ports, USB card, Firewire card, all 8 RAM slots filled, an extra internal HD, and have been thru to processor upgrades from 604 to G3 to G4. I was able to keep up with new technology without having to buy new machines each year (Now I do need a new one and have been waiting for 8 months for the G5 and will wait until it's released).



    If you don't need (or want) all the flexibility of the tower by an iMac and then get a new one every 2 or 3 years.
  • Reply 96 of 456
    airslufairsluf Posts: 1,861member
  • Reply 97 of 456
    [quote]Originally posted by Outsider:

    <strong>Yes but how about extremely long pipelines with trap doors. When a particular instruction is done it can exit the pipeline at any given stage or be moved up several stages if there is a bubble. Some instructions won't use and the stages in a pipeline so it should be able to warp ahead to the stage that it can use.



    Also how about incorporating multiple pipeline stages and register sets. Not only one or two but 4 or 8. As long as you have enough execution units (say 5-6 integer units and 3-4 FPU units).



    Also about BPU design, I read somewhere baout IBM using AI to help improve predictions to almost 100% by using stored information and a learning feature.</strong><hr></blockquote>



    The trap doors only help if you can use them, and only if they come early enough. If you have to wait 20 stages before you reach the trap door, you still have to wait.



    The large number of execution units and register sets is essentially "hyper-threading". This lets you share the execution units between threads, hopefully getting better utilization.



    The IBM BPU thing -- this only works if your stored information is accurate. The current processors all have "branch hit tables" to store branch histories, and they record the pattern of a couple of recent branches to try and look for repetitive patterns. Branch prediction works well if there is a pattern to the branching. This is fine for exceptional conditions (usually not taken), error handling (errors are usually infrequent), and long loops (usually branch to top of loop). For logic that takes the branch 50% of the time in a random pattern, however, you're outta luck -- no prediction is going to help. I've seen cases where the branch prediction turned out to be optimally bad, blowing the whole pipeline on each branch! The best that can be done is to move the test as far from the branch as possible, and the PowerPC is already really good at that. Often, however, there just isn't anything to do between the test and the branch and you end up waiting.



    On the upside the most common branches in modern code are those in long loops, and the processors are already really good at handling them. So good, in fact, that I would find it of dubious value to throw even more transistors at it.
  • Reply 98 of 456
    [quote]Originally posted by AirSluf:

    <strong>As more and more software becomes truly object oriented, branch prediction will suffer as well. There will be much more work done with dynamic linking at runtime as hardware speed and knowledge erode the speed penalties compared to statically compiled code, then most of the executed branches left will be loops. Loop repetition is relatively easy to predict, that's where nearly all of the current 95+% success rate is already.</strong><hr></blockquote>



    This can be dealt with to some extent, fortunately. The P4 does a poor job of it, but a smarter design could do a lot better. Objects, once created, tend not to change their type so they become much easier to predict after creation.
  • Reply 99 of 456
    outsideroutsider Posts: 6,008member
    Or how about this: have two identicle pipelines running in parallel the same instruction flow. When a branch occurs, the pipelines go off in different directions, one is the most likely and the other is the second most likely. If one stalls then it is cleared and the other takes over. (if that one is correct that is) The other pipeline can even be cleared and reloaded with the info in the correct incase there is another branch.
  • Reply 100 of 456
    [quote]Originally posted by Outsider:

    <strong>Or how about this: have two identicle pipelines running in parallel the same instruction flow. When a branch occurs, the pipelines go off in different directions, one is the most likely and the other is the second most likely. If one stalls then it is cleared and the other takes over. (if that one is correct that is) The other pipeline can even be cleared and reloaded with the info in the correct incase there is another branch.</strong><hr></blockquote>



    Isn't that just wasting die space? Add another functional unit instead.
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