Do you guys know of any web sites that provide a basic grounding in this processor design theory and pipeline stuff? I mean something which wouldn't require a degree in CS to understand (at least at a fundamental level)? I seem to remember seeing a thread in here (I think Eskimo posted it but I'm not sure) that kind of explained how CPU's are manufactured in common man's language...that was great. If there is something similar to understand how modern CPU's like the G4 work (or work differently from a P4), that would be cool.
There's that arstech or something geek-techish that someone here I'm sure could provide a link for. It's pretty filled with tech info and it's platform nuetral (I believe) and did have a pipeline comparision between the G4 and the Pllll, and might have other articles related to pipelines.
<strong>Do you guys know of any web sites that provide a basic grounding in this processor design theory and pipeline stuff? I mean something which wouldn't require a degree in CS to understand (at least at a fundamental level)? I seem to remember seeing a thread in here (I think Eskimo posted it but I'm not sure) that kind of explained how CPU's are manufactured in common man's language...that was great. If there is something similar to understand how modern CPU's like the G4 work (or work differently from a P4), that would be cool.</strong><hr></blockquote>
Go to <a href="http://www.mackido.com"; target="_blank">www.mackido.com</a> - look under hardware -> Pipelines (or G4)...this site is truly excellent...but some of the stuff is a bit old...
<strong>Do you guys know of any web sites that provide a basic grounding in this processor design theory and pipeline stuff? I mean something which wouldn't require a degree in CS to understand (at least at a fundamental level)? I seem to remember seeing a thread in here (I think Eskimo posted it but I'm not sure) that kind of explained how CPU's are manufactured in common man's language...that was great. If there is something similar to understand how modern CPU's like the G4 work (or work differently from a P4), that would be cool.</strong><hr></blockquote>
Try <a href="http://www.arstechnica.com/"; target="_blank">ArsTechica</a>, they even have a series of articles comparing P4 and G4
4. If I lose that would cut into my Xmas 2002 in Vegas fund (what can I say, my family likes to party). I need those coins for the slots and those greenbacks for the tables.</strong><hr></blockquote>
You guys are nuts ... how can either of you be sure, that the other doesn't have inside information. One of you could be Steve Jobs.
[quote] Also about BPU design, I read somewhere baout IBM using AI to help improve predictions to almost 100% by using stored information and a learning feature. <hr></blockquote>
If this is true, then IBM are crazy. AtAT has a much better record with predictions than this place. Perhaps they're trying to develop a JYD-style BPU that gets Apple executives drunk to make them spill the beans.
Ask Intel, that's basically what their HyperThreading technology is doing/going to do.</strong><hr></blockquote>
No, Hyperthreading still uses the same resources as an ordinary P4 (although there are a few extra pieces of hardware built in) ie. one pipeline, one set of registers (with lots of rename registers), one set of functional units, but picks instructions from two separate threads (programmes or parts thereof) to run together so as to be able to use as many functional units as possible. Instructions from separate threads should'nt block each other as they don't depend on each other, and hence some inefficiency is avoided.
Don't mistake what i'm saying with a dual core processor.. i'm thinking of a normal single core processor using 2 sets of registers and just beefing up the number execution units and hyper-threading abilities. I know it's not a new and original idea but it's a practical one. It's the future so might as well get on the bandwagon.
Hyper-threading must have enough registers to have (at least) two "apparent" sets of user registers. If the processor is running 2 threads it needs to be able to hold 2 contexts. The execution units will be shared.
Re: a pipeline taking each branch. I think this may have been attempted on a very limited scale -- i.e. do the fetch and decode on both sides of the branch. The problem with running two full pipelines is two-fold: you waste a lot of resources if you don't branch for a while, and what happens if you have two branches in a row? No, I think the PowerPC guys are doing pretty well with the seperation of the compare and the branch thanks to the PPC ISA. This will let them get away with about 10 stages at minimal cost, and going longer just won't be a payoff. Instead they'll go hyper-threaded or multi-core so that more execution units can be added and still be utilized. My guess is that a 10 stage pipeline and upcoming improvements in process will give the G5 really long legs -- enough to keep up with Intel (if not ahead), and it will deal with most code better than the P4 does.
You guys are nuts ... how can either of you be sure, that the other doesn't have inside information. One of you could be Steve Jobs.</strong><hr></blockquote>
I am Steve Jobs, but I only get paid $1 a year and can't afford my own iPod
Actually, I'm not even an outsider. I'd have to move closer than I am now to even be considered an outsider. You know the expression "middle of nowhere?" I'd have to go 50 miles just to be there, apple-info-wise.
Does anyone have faith in the NMR? I'm not saying I don't, it's just that usually I don't bother to read his articles so I don't really follow his news. How were his MacWorld predictions?
The first line where you tell us the G5s wont come out till 2003 at the earliest or what? I trust my gut, which happens to work in Motorola. Does that mean I know when the G5 is coming? no, but I sure as hell have a better idea of it.
Comments
<strong>Do you guys know of any web sites that provide a basic grounding in this processor design theory and pipeline stuff? I mean something which wouldn't require a degree in CS to understand (at least at a fundamental level)? I seem to remember seeing a thread in here (I think Eskimo posted it but I'm not sure) that kind of explained how CPU's are manufactured in common man's language...that was great. If there is something similar to understand how modern CPU's like the G4 work (or work differently from a P4), that would be cool.</strong><hr></blockquote>
Go to <a href="http://www.mackido.com"; target="_blank">www.mackido.com</a> - look under hardware -> Pipelines (or G4)...this site is truly excellent...but some of the stuff is a bit old...
/Cyber
<strong>Do you guys know of any web sites that provide a basic grounding in this processor design theory and pipeline stuff? I mean something which wouldn't require a degree in CS to understand (at least at a fundamental level)? I seem to remember seeing a thread in here (I think Eskimo posted it but I'm not sure) that kind of explained how CPU's are manufactured in common man's language...that was great. If there is something similar to understand how modern CPU's like the G4 work (or work differently from a P4), that would be cool.</strong><hr></blockquote>
Try <a href="http://www.arstechnica.com/"; target="_blank">ArsTechica</a>, they even have a series of articles comparing P4 and G4
and <a href="http://www.extremetech.com/"; target="_blank">Extreme tech</a> have a lot of good stuff, but the real nitty-gritty is at <a href="http://www.realworldtech.com/index.cfm"; target="_blank">realworldtech</a>, especially the articles by Paul Demone
Michael
<strong>
4. If I lose that would cut into my Xmas 2002 in Vegas fund (what can I say, my family likes to party). I need those coins for the slots and those greenbacks for the tables.</strong><hr></blockquote>
You guys are nuts ... how can either of you be sure, that the other doesn't have inside information. One of you could be Steve Jobs.
[quote] Also about BPU design, I read somewhere baout IBM using AI to help improve predictions to almost 100% by using stored information and a learning feature. <hr></blockquote>
If this is true, then IBM are crazy. AtAT has a much better record with predictions than this place. Perhaps they're trying to develop a JYD-style BPU that gets Apple executives drunk to make them spill the beans.
<strong>
Isn't that just wasting die space? Add another functional unit instead.</strong><hr></blockquote>
Ask Intel, that's basically what their HyperThreading technology is doing/going to do.
<strong>
Ask Intel, that's basically what their HyperThreading technology is doing/going to do.</strong><hr></blockquote>
No, Hyperthreading still uses the same resources as an ordinary P4 (although there are a few extra pieces of hardware built in) ie. one pipeline, one set of registers (with lots of rename registers), one set of functional units, but picks instructions from two separate threads (programmes or parts thereof) to run together so as to be able to use as many functional units as possible. Instructions from separate threads should'nt block each other as they don't depend on each other, and hence some inefficiency is avoided.
Michael
Re: a pipeline taking each branch. I think this may have been attempted on a very limited scale -- i.e. do the fetch and decode on both sides of the branch. The problem with running two full pipelines is two-fold: you waste a lot of resources if you don't branch for a while, and what happens if you have two branches in a row? No, I think the PowerPC guys are doing pretty well with the seperation of the compare and the branch thanks to the PPC ISA. This will let them get away with about 10 stages at minimal cost, and going longer just won't be a payoff. Instead they'll go hyper-threaded or multi-core so that more execution units can be added and still be utilized. My guess is that a 10 stage pipeline and upcoming improvements in process will give the G5 really long legs -- enough to keep up with Intel (if not ahead), and it will deal with most code better than the P4 does.
<strong>
You guys are nuts ... how can either of you be sure, that the other doesn't have inside information. One of you could be Steve Jobs.</strong><hr></blockquote>
I am Steve Jobs, but I only get paid $1 a year and can't afford my own iPod
Weird.
Actually, I'm not even an outsider. I'd have to move closer than I am now to even be considered an outsider. You know the expression "middle of nowhere?" I'd have to go 50 miles just to be there, apple-info-wise.
SdC
Apollo Power Macs "in the 1.4 GHz range", "Jan. 20 or thereabouts."
Screed ...Zed's dead, baby. Zed's dead.
[ 01-14-2002: Message edited by: sCreeD ]</p>
He also called for a G5, so batting 500 right now and I hope he ends up batting a 1000 and we get G5s!!
I also call for G5s.
What's that? Can't read? Short attention span from MTV and Cap'n Crunch? I thought so.
SdC
<strong>Not sure about NMR's record, but apllenut called the iMac with G4 and superdrive.
He also called for a G5, so batting 500 right now and I hope he ends up batting a 1000 and we get G5s!!</strong><hr></blockquote>
me too
Look, it's Old Man River!