<strong>data throughput is 2.1GB for the memory bus. Even if the G4 can't use it, a dual config CAN take advantage because now each G4 can fully saturate it's own bus without choking off the data supply to the other G4. As I understand it, the G4's themselves would still have less than optimal bandwidth, but at least they won't be fighting each other for the memory bandwidth.
And I was sure that OSX supported 4+ GB of main memory. Does Apple have some sort of aversion to 1GB dimms?</strong><hr></blockquote>
Nope! Unfortunately you're wrong. The G4 uses a shared memory bus, like the PIII and P4 and unlike the Athlon which uses independent buses for each CPU in dual configurations.
What this means is that when you have a dual G4 system, both CPUs have to share the measly 1 GB/s bandwidth of the 133 Mhz bus, no matter how much bandwidth the RAM is connected to the memory controller with.
Is it possible that one of the G4 access the memory while the cycle of memory is in the raising phase, while the other G4 access the memory on the other phase. It will make 133 mhz per processor but much better than 133 mhz divided by two.</strong><hr></blockquote>
We don't know the particulars of Apple's memory controller yet. It is still possible that it talks to system memory at DDR266 speed on one end and doles out data to the each of the G4's independently a 133Mhz SDR speeds on the other end.
Lets wait and see before we turn violently from "WOW!" to "What a POS!" in just 4 short pages. We are an amazing group. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
In this case it's more like so very typical of Motorola (& IBM it's not like they're offering something much better). Because the problem is with the G4 and not with the chipset.
Theoretically, this new chipset could still offer slightly increased performance under very specific situations, due to having excess memory bandwidth for doing AGP or DMA transfers when the CPU bus is already saturated.
But benchmarks have shown such improvements to be negligible and only in rare cases, when Pentium III and Athlon were paired with higher bandwidth memory than the processor could handle.
<strong>We don't know the particulars of Apple's memory controller yet. It is still possible that it talks to system memory at DDR266 speed on one end and doles out data to the each of the G4's independently a 133Mhz SDR speeds on the other end. </strong><hr></blockquote>
.
Yes we do. Observe the pipe that connects both CPUs to the memory controller. That pipe is 1GB/s wide, simple as that. No ifs ands or buts
<strong>Only the data paths from the memory controller to the DRAM slots is double-clocked. The processor front-side bus still is the same od 133MHz bus that's already in the current towers.</strong><hr></blockquote>
So if this DDR RAM won't help performance, why did Apple use it? Is it just about buzzword compliance, or is there any technical reason why they would use it?
If this controller is just a straight forward DDR266 controller and not really a 'custom' asic, then that might be a better sign for the future than if it truly were some sort of custom asic designed to compensate for a G4 archaism.
It would mean that a better PPC (with modern memory) is eminent, but just wasn't ready in time for this product. No use waiting for it when they could get an acceptable product out now. Especially since NOW is the time to capitalize on the UNIX abilities of OSX for the enterprise, web hosting, server, and A/V storage markets.
I'm waiting for DDR pro-products. Really, everything except for maybe the iBooks and CRTmacs should be on a DDR bus, considering what they cost, Powermacs AND PowerBooks should be using DDR right now!
So if this DDR RAM won't help performance, why did Apple use it? Is it just about buzzword compliance, or is there any technical reason why they would use it?</strong><hr></blockquote>
All of the above. Mostly buzzword compliance, and they probably developed the DDR chipset for the upcoming verison of the G4 that does support a DDR bus anyway, so why not use it.
Also, as Razzfazz also pointed out, since these things are supposed to be operating 4 drives in software RAID and stuff, the extra bandwidth from the memory could improve DMA performance, in some cases.
<strong>bodhi, we get it. you don't like 'em. </strong><hr></blockquote>
It's just frustrating on many levels of what Apple is capable of doing but their hands are tied with Mot. I think I read somewhere that the G4 cannot handle a faster bus than 133? Is that the case?
The <a href="http://www.apple.com/xserve/support.html"; target="_blank">support</a> options look good, and attractively priced too. I hope they can keep to their word.
It's just frustrating on many levels of what Apple is capable of doing but their hands are tied with Mot. I think I read somewhere that the G4 cannot handle a faster bus than 133? Is that the case?</strong><hr></blockquote>
You've hit the nail on the head. As good as the G4 architecture is, it also seems to be the weak link in the proverbial chain.
Jumping into the Server Arena isn't for the faint of heart. Apple simply could not even think about this 2 years ago. I think the XServe is a Great start and I look for Apple to improve. As Belle say..it's the Support that will make or break Apple here not bus speeds.
<strong>Jumping into the Server Arena isn't for the faint of heart. Apple simply could not even think about this 2 years ago. I think the XServe is a Great start and I look for Apple to improve. As Belle say..it's the Support that will make or break Apple here not bus speeds.</strong><hr></blockquote>
<strong>I think I read somewhere that the G4 cannot handle a faster bus than 133? Is that the case?</strong><hr></blockquote>Their specs list the bus speed of the recent and current G4s as 133. But anyway, I think this Xserve pretty much confirms it. If the RAM in the thing could support 266, but the bus remains at 133 anyway...
Well we may be disapointed by the pseudo DDR thing, but as soon as Apple will able to get the next generation of G4 with DDR maxbus he will upgrade easily (no need to change or improve is mobo) the xserver. It's a just question of months.
Comments
<strong>data throughput is 2.1GB for the memory bus. Even if the G4 can't use it, a dual config CAN take advantage because now each G4 can fully saturate it's own bus without choking off the data supply to the other G4. As I understand it, the G4's themselves would still have less than optimal bandwidth, but at least they won't be fighting each other for the memory bandwidth.
And I was sure that OSX supported 4+ GB of main memory. Does Apple have some sort of aversion to 1GB dimms?</strong><hr></blockquote>
Nope! Unfortunately you're wrong. The G4 uses a shared memory bus, like the PIII and P4 and unlike the Athlon which uses independent buses for each CPU in dual configurations.
What this means is that when you have a dual G4 system, both CPUs have to share the measly 1 GB/s bandwidth of the 133 Mhz bus, no matter how much bandwidth the RAM is connected to the memory controller with.
It's sad cause it's true.
<strong>Apple says 4x ATA-100 controller will give theoretical max of 266 MB/s. Shouldn't this be 400 MB/s?</strong><hr></blockquote>
The ATA controller is probably a PCI32/66 or PCI64/33 device, and as such can only trasnfer at up to 266MB/s.
Bye,
RazzFazz
<strong>
Is it possible that one of the G4 access the memory while the cycle of memory is in the raising phase, while the other G4 access the memory on the other phase. It will make 133 mhz per processor but much better than 133 mhz divided by two.</strong><hr></blockquote>
Nope, that's not possible.
Bye,
RazzFazz
Lets wait and see before we turn violently from "WOW!" to "What a POS!" in just 4 short pages. We are an amazing group. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
<strong>
So very typical of Apple isn't it?
[ 05-14-2002: Message edited by: Bodhi ]</strong><hr></blockquote>
In this case it's more like so very typical of Motorola (& IBM it's not like they're offering something much better). Because the problem is with the G4 and not with the chipset.
Theoretically, this new chipset could still offer slightly increased performance under very specific situations, due to having excess memory bandwidth for doing AGP or DMA transfers when the CPU bus is already saturated.
But benchmarks have shown such improvements to be negligible and only in rare cases, when Pentium III and Athlon were paired with higher bandwidth memory than the processor could handle.
<strong>We don't know the particulars of Apple's memory controller yet. It is still possible that it talks to system memory at DDR266 speed on one end and doles out data to the each of the G4's independently a 133Mhz SDR speeds on the other end. </strong><hr></blockquote>
.
Yes we do. Observe the pipe that connects both CPUs to the memory controller. That pipe is 1GB/s wide, simple as that. No ifs ands or buts
[ 05-14-2002: Message edited by: timortis ]</p>
<strong>Only the data paths from the memory controller to the DRAM slots is double-clocked. The processor front-side bus still is the same od 133MHz bus that's already in the current towers.</strong><hr></blockquote>
So if this DDR RAM won't help performance, why did Apple use it? Is it just about buzzword compliance, or is there any technical reason why they would use it?
It would mean that a better PPC (with modern memory) is eminent, but just wasn't ready in time for this product. No use waiting for it when they could get an acceptable product out now. Especially since NOW is the time to capitalize on the UNIX abilities of OSX for the enterprise, web hosting, server, and A/V storage markets.
I'm waiting for DDR pro-products. Really, everything except for maybe the iBooks and CRTmacs should be on a DDR bus, considering what they cost, Powermacs AND PowerBooks should be using DDR right now!
<strong>
So if this DDR RAM won't help performance, why did Apple use it? Is it just about buzzword compliance, or is there any technical reason why they would use it?</strong><hr></blockquote>
All of the above. Mostly buzzword compliance, and they probably developed the DDR chipset for the upcoming verison of the G4 that does support a DDR bus anyway, so why not use it.
Also, as Razzfazz also pointed out, since these things are supposed to be operating 4 drives in software RAID and stuff, the extra bandwidth from the memory could improve DMA performance, in some cases.
<strong>bodhi, we get it. you don't like 'em.
It's just frustrating on many levels of what Apple is capable of doing but their hands are tied with Mot. I think I read somewhere that the G4 cannot handle a faster bus than 133? Is that the case?
<strong>
It's just frustrating on many levels of what Apple is capable of doing but their hands are tied with Mot. I think I read somewhere that the G4 cannot handle a faster bus than 133? Is that the case?</strong><hr></blockquote>
You've hit the nail on the head. As good as the G4 architecture is, it also seems to be the weak link in the proverbial chain.
<strong>It's just frustrating on many levels of what Apple is capable of doing but their hands are tied with Mot.</strong><hr></blockquote>
Heh, it's true. But what can Apple do about it?
<strong>
Heh, it's true. But what can Apple do about it?</strong><hr></blockquote>
Develop a PPC with AMD!
Seriously - Eskimo, could you shed some light on these specs? What do you say about the 133MHz bus and the DDR ram?
<strong>Jumping into the Server Arena isn't for the faint of heart. Apple simply could not even think about this 2 years ago. I think the XServe is a Great start and I look for Apple to improve. As Belle say..it's the Support that will make or break Apple here not bus speeds.</strong><hr></blockquote>
Agreed. The support is fantastic.
<strong>Develop a PPC with AMD!</strong><hr></blockquote>
A nice thought, but who's to say they could do any better?
<strong>I think I read somewhere that the G4 cannot handle a faster bus than 133? Is that the case?</strong><hr></blockquote>Their specs list the bus speed of the recent and current G4s as 133. But anyway, I think this Xserve pretty much confirms it. If the RAM in the thing could support 266, but the bus remains at 133 anyway...