Does this mean a 2GHz chip? It can't! Can it?</strong><hr></blockquote>
No, it means a 2 GHz bus. It is asynchronous from the chip, remember? It would be a switch to have the bus at a higher clock rate than the chip, wouldn't it? But its 4x narrower, so the next speed up is on the order of "only" 4x.
In short, the e500 core sucks. In a little more detail, the MPC 8540 really sucks for Apple.
Dorsal M looks to be talking from whitepapers to me, and all that doesn't even seem correct. From a MIPS point view the 8540 gets 2300 MIPS at 1 GHz on 0.13u process. The 7455 get 2300 MIPS at 1 GHz on a 0.18u SOI process. This is telling me that the 8540 is 4 stage execution pipeline, not 7. I can guarantee that a 7455 when manufactured on a 0.13u process will clock 50% higher than the 8540 and therefore have 50% greater performance. There is nothing to gain from the 8540 for Apple. Nothing. If Apple wants a low Watt processor, IBM's 750fx will be fine, and is already shipping, as well as a 1 GHz 7455 of which a 1 GHz 8540 purports to match in performance 6 months from now.
If there is a 4-way superscaler out-of-order superpipelined (10+ stages) Book E base PPC coming out, then it holds promise for Apple. The MPC 8540 and e500 which it's based do not.
Does the E500 core have an FPU, or would that be a seperate addition to the overall chip like Altivec? I'm just curious, because if it's included in the core, a multi-core chip would then have an automatic increase in FPU performance.
Quote from above: "Sony Computer Entertainment Inc. (SCEI), IBM Corp. and Toshiba Corp. announced a major partnership aimed at creating a processor architecture ? code-named Cell ? that will be optimized for multimedia packet processing over the broadband network."
This processor is supposed to become the CPU of the PlayStation3. But who knows ...
As far as I can say Altivec has been implemented as APU, connected to the e500 via OCEAN. It seems the same is true for the FPU, it looks like the FPU is not part of the e500 itself. I hope this doesn't affect the performance in a negative way.</strong>
It doesn't make sense for APUs to be connected by the Ocean fabric. APUs have to be directly connected to the e500's dispatch unit, completion unit and registers. So they must be inside the e500 core itself.
The e500 then has another unit outside of it that controls access to L2 cache and the memory controller. It is this unit that connects the e500 core to the Ocean fabric. The Ocean fabric then acts as a network for all the I/O on the CPU. Ie, PCI, Ethernet, DMA, RapidIO, etc.
<strong>RIO is capable of over 7GBps bandwidth running at 16bit.
This will rock, hehe...</strong>
RapidIO is 4 bytes per clock per channel and seems to have limit of 1 GHz in the spec. For a 16 bit 1 GHz RapidIO bus that's 16 bit x 2 (it's DDR) x 1 GHz = 4 GBytes/s. One can probably increase the bandwidth more by adding more buses. But the RapidIO devices coming out in the near future probably won't clock over 500 MHz.
<strong>The beauty of Book E is the modularity. The way Motorola designed it was so a customer can pick and choose the components.
Right, customers can even design their own circuits an connect them as APUs via the OCEAN crossbar switch.</strong>
I don't think so.
The Ocean fabric connects I/O, not processor execution units. It can maybe connect multiple e500 cores together, but I really doubt that.
I have not been following the G5 discussion too closely, so please forgive me for my question:
Will the G5 (64-bit version) be similar in construction to the AMD hammers in that it will basically still be a 32-bit processor with an added 64-bit unit?
Dorsal M looks to be talking from whitepapers to me, and all that doesn't even seem correct. <hr></blockquote>
[quote]Originally posted by Bodhi:
Keep in mind that everything Dorsal said is publiclly available. Perfect example is that diagram from Motorola's site.
Not discounting what Dorsal is saying...just trying to keep things in perspective.
<hr></blockquote>
You know, I'm not trying to pick on the guy, since he's about the only that keeps this place exciting nowadays. How many people can get pages and pages of replies on just a couple of posts?
However, speaking as a pathological liar, you have to keep your story straight (honest-- I wouldn't be making this up).
Let's do a little karaoke while I type along:
When that shark bites
The original Dorsal was supposed to be testing hardware.
With its teeth babe
His posts were about how fast the widgets went, and what widgets were lying around the board.
Scarlet billows start to spread...
Now the posts are more like design papers (white papers).
...Oh the line forms on the right, babe.
I'm not sure what this all means, but I've always had this thing about being shark bait. I'm beginning to think Dorsal is blowing bubbles.
BTW: Haven't you ever wondered what really happened to Miss Lotte Lenya?
The Hammer family will not only be a 64-bit family--it's already (see the early tests on the prototypes) a huge accomplishment efficiency-wise. The Opteron is already 40% (or so THG quoted some e-zine saying) faster than an Athlon at the same clock speed executing non-optimized 32-bit code. :eek:
That's no 64-bit myth, that's a hell of great design... Apple simply can't afford to be left behind on this issue, period. We need a 64-bit PowerPC CPU, because so the market dictates.</strong><hr></blockquote>
A large portion of the Hammer-series' performance gain has come through the use of an on-chip memory controller and other architechtural changes/improvements. The addition of 64-bit instructions hasn't been to improve performance for your average consumer it has been added so AMD could go after new markets.
AMD originally planned the Hammer series to target servers and workstations with the old Athlon core remaining along side it for some time in the consumer sector. Unfortunately the old Athlon core has basically hit the end of its usefulness and can't go any further. Now what would have been the Clawhammers will take over there forcing the chip to have much greater adoption in the mainstream.
Intel is simply doing the same thing but actually has a 2nd chip with some life left in it. McKinley and its more evolved counterparts aren't going to be aimed at the consumer space in the near future, the PIV is there for that. Later there will be a move to switch people over but you have a while before it happens.
Now if Apple wants to go after the 64-bit marketspace then that's fine they will need a 64-bit chip to do so. They may or may not decide to go there that's a matter for management.
If all they will continue to do is aim at the consumer space 64-bit computing isn't necessary or useful yet. If Apple doesn't release a 64-bit chip until 2003 or 2004 it will not be doomed and in fact it won't really matter in the least to their current markets except from a marketing point of view.
All that said when they do release their next generation chip there is no reason it shouldn't be designed with a 64-bit future in mind even if they only do it for marketing reasons.
[quote]Marketing is everything (look at the consoles).<hr></blockquote>
Consoles are largely about the game developers that are onside for a certain console. In Japan a lot of people have bought PS2 consoles simply due to Square's development for the platform.
When the Xbox came out they released it with a series of big Xbox only titles to try and lure people to buy the console for just certain titles. Nintendo did the same thing with the Gamecube.
It's no big secret if you want to play games any current generation console can do the job but if you want to play certain games often only one console has rights to them. That's what drives the console market more than anything. Certainly what motivated my buying.
<strong>Will the G5 (64-bit version) be similar in construction to the AMD hammers in that it will basically still be a 32-bit processor with an added 64-bit unit?</strong><hr></blockquote>
I think it will indeed be made in a fab on a Silicon wafer
<strong>The Ocean fabric connects I/O, not processor execution units. It can maybe connect multiple e500 cores together, but I really doubt that.</strong><hr></blockquote>
I haven't seen anything particularly detailed about OCEAN -- do you have any reference materials? If it was sufficiently fast it should be possible to pass instructions to and from on-chip units for dispatch & retirement. This is what Dorsal was implying, but unless we have some real documentation on OCEAN its hard to verify / deny. I said earlier that this thread might be the make/break thread for Dorsal, but perhaps it will be this particular post that proves he does or doesn't know what the hell he's talking about.
The PowerMac G4 as we know it will be retired. Well the architecture will at least. We will see changes to the system bus, processor and general layout. Motorola has been hard at work with the 130nm G4. It will scale nicely (at least 1.5GHz by the summer) and have improved bus features. Memory access will be stellar. And you'll see why. not only will DDR SDRAM make a debut but it will not connect to the processor iin a conventional manner. More to come. Cache will also be increased on the processor level. Twice what is seen now. You will see a collaboration with another hardware company, but this will not surprise some of you in the know.
More to come.</strong><hr></blockquote>
This jibes with what I've heard as well, but as I understand it, this motherboard has been unfortunately delayed, and a stop-gap DDR motherboard is what we'll see first. We shall see...
<strong>This jibes with what I've heard as well, but as I understand it, this motherboard has been unfortunately delayed, and a stop-gap DDR motherboard is what we'll see first. We shall see...</strong><hr></blockquote>
But what is the difference between the "real" mobo and the "stop-gap" one? Is it the processor <-> memory connection or the chipset DSPs you were talking about?
I hear that Apple will put out an RDF on the AGP so the PCI is 8x faster than the DDR on the UMA, but only if the 3GIO is ready from the OEM at a good MSRP. Then again I heard this on the D/L from someone at MOSR so I guess I'm SOL.
<strong>I hear that Apple will put out an RDF on the AGP so the PCI is 8x faster than the DDR on the UMA, but only if the 3GIO is ready from the OEM at a good MSRP. Then again I heard this on the D/L from someone at MOSR so I guess I'm SOL.
Comments
<strong>
Does this mean a 2GHz chip? It can't! Can it?</strong><hr></blockquote>
No, it means a 2 GHz bus. It is asynchronous from the chip, remember? It would be a switch to have the bus at a higher clock rate than the chip, wouldn't it? But its 4x narrower, so the next speed up is on the order of "only" 4x.
describes the architecture from a 32-bit perspective. Although some 64-bit resources are
discussed, this manual does not completely describe details of the 64-bit?only features of
the architecture, in particular with respect to the memory management model, registers, and
instruction set.
In short, the e500 core sucks. In a little more detail, the MPC 8540 really sucks for Apple.
Dorsal M looks to be talking from whitepapers to me, and all that doesn't even seem correct. From a MIPS point view the 8540 gets 2300 MIPS at 1 GHz on 0.13u process. The 7455 get 2300 MIPS at 1 GHz on a 0.18u SOI process. This is telling me that the 8540 is 4 stage execution pipeline, not 7. I can guarantee that a 7455 when manufactured on a 0.13u process will clock 50% higher than the 8540 and therefore have 50% greater performance. There is nothing to gain from the 8540 for Apple. Nothing. If Apple wants a low Watt processor, IBM's 750fx will be fine, and is already shipping, as well as a 1 GHz 7455 of which a 1 GHz 8540 purports to match in performance 6 months from now.
If there is a 4-way superscaler out-of-order superpipelined (10+ stages) Book E base PPC coming out, then it holds promise for Apple. The MPC 8540 and e500 which it's based do not.
Just a thought.
This processor is supposed to become the CPU of the PlayStation3. But who knows ...
[ 06-17-2002: Message edited by: THT ]</p>
what I remember :
Cell-processor will be suitable for computers though and allow you to combine the power of multiple PS3 processors over networks (maybe pc's)
speed of this new processors would be way faster then anything we can see today (think 'bout 100s of time faster)
There is an Altivec add on built for the e500.
As far as I can say Altivec has been implemented as APU, connected to the e500 via OCEAN. It seems the same is true for the FPU, it looks like the FPU is not part of the e500 itself. I hope this doesn't affect the performance in a negative way.</strong>
It doesn't make sense for APUs to be connected by the Ocean fabric. APUs have to be directly connected to the e500's dispatch unit, completion unit and registers. So they must be inside the e500 core itself.
The e500 then has another unit outside of it that controls access to L2 cache and the memory controller. It is this unit that connects the e500 core to the Ocean fabric. The Ocean fabric then acts as a network for all the I/O on the CPU. Ie, PCI, Ethernet, DMA, RapidIO, etc.
<strong>RIO is capable of over 7GBps bandwidth running at 16bit.
This will rock, hehe...</strong>
RapidIO is 4 bytes per clock per channel and seems to have limit of 1 GHz in the spec. For a 16 bit 1 GHz RapidIO bus that's 16 bit x 2 (it's DDR) x 1 GHz = 4 GBytes/s. One can probably increase the bandwidth more by adding more buses. But the RapidIO devices coming out in the near future probably won't clock over 500 MHz.
<strong>The beauty of Book E is the modularity. The way Motorola designed it was so a customer can pick and choose the components.
Right, customers can even design their own circuits an connect them as APUs via the OCEAN crossbar switch.</strong>
I don't think so.
The Ocean fabric connects I/O, not processor execution units. It can maybe connect multiple e500 cores together, but I really doubt that.
Will the G5 (64-bit version) be similar in construction to the AMD hammers in that it will basically still be a 32-bit processor with an added 64-bit unit?
Dorsal M looks to be talking from whitepapers to me, and all that doesn't even seem correct. <hr></blockquote>
[quote]Originally posted by Bodhi:
Keep in mind that everything Dorsal said is publiclly available. Perfect example is that diagram from Motorola's site.
Not discounting what Dorsal is saying...just trying to keep things in perspective.
<hr></blockquote>
You know, I'm not trying to pick on the guy, since he's about the only that keeps this place exciting nowadays. How many people can get pages and pages of replies on just a couple of posts?
However, speaking as a pathological liar, you have to keep your story straight (honest-- I wouldn't be making this up).
Let's do a little karaoke while I type along:
When that shark bites
The original Dorsal was supposed to be testing hardware.
With its teeth babe
His posts were about how fast the widgets went, and what widgets were lying around the board.
Scarlet billows start to spread...
Now the posts are more like design papers (white papers).
...Oh the line forms on the right, babe.
I'm not sure what this all means, but I've always had this thing about being shark bait. I'm beginning to think Dorsal is blowing bubbles.
BTW: Haven't you ever wondered what really happened to Miss Lotte Lenya?
<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
lemon bon bon
<strong>
The Hammer family will not only be a 64-bit family--it's already (see the early tests on the prototypes) a huge accomplishment efficiency-wise. The Opteron is already 40% (or so THG quoted some e-zine saying) faster than an Athlon at the same clock speed executing non-optimized 32-bit code. :eek:
That's no 64-bit myth, that's a hell of great design... Apple simply can't afford to be left behind on this issue, period. We need a 64-bit PowerPC CPU, because so the market dictates.</strong><hr></blockquote>
A large portion of the Hammer-series' performance gain has come through the use of an on-chip memory controller and other architechtural changes/improvements. The addition of 64-bit instructions hasn't been to improve performance for your average consumer it has been added so AMD could go after new markets.
AMD originally planned the Hammer series to target servers and workstations with the old Athlon core remaining along side it for some time in the consumer sector. Unfortunately the old Athlon core has basically hit the end of its usefulness and can't go any further. Now what would have been the Clawhammers will take over there forcing the chip to have much greater adoption in the mainstream.
Intel is simply doing the same thing but actually has a 2nd chip with some life left in it. McKinley and its more evolved counterparts aren't going to be aimed at the consumer space in the near future, the PIV is there for that. Later there will be a move to switch people over but you have a while before it happens.
Now if Apple wants to go after the 64-bit marketspace then that's fine they will need a 64-bit chip to do so. They may or may not decide to go there that's a matter for management.
If all they will continue to do is aim at the consumer space 64-bit computing isn't necessary or useful yet. If Apple doesn't release a 64-bit chip until 2003 or 2004 it will not be doomed and in fact it won't really matter in the least to their current markets except from a marketing point of view.
All that said when they do release their next generation chip there is no reason it shouldn't be designed with a 64-bit future in mind even if they only do it for marketing reasons.
[quote]Marketing is everything (look at the consoles).<hr></blockquote>
Consoles are largely about the game developers that are onside for a certain console. In Japan a lot of people have bought PS2 consoles simply due to Square's development for the platform.
When the Xbox came out they released it with a series of big Xbox only titles to try and lure people to buy the console for just certain titles. Nintendo did the same thing with the Gamecube.
It's no big secret if you want to play games any current generation console can do the job but if you want to play certain games often only one console has rights to them. That's what drives the console market more than anything. Certainly what motivated my buying.
Edit: Added console stuff.
[ 06-17-2002: Message edited by: Telomar ]
[ 06-18-2002: Message edited by: Telomar ]</p>
<strong>Will the G5 (64-bit version) be similar in construction to the AMD hammers in that it will basically still be a 32-bit processor with an added 64-bit unit?</strong><hr></blockquote>
I think it will indeed be made in a fab on a Silicon wafer
<strong>The Ocean fabric connects I/O, not processor execution units. It can maybe connect multiple e500 cores together, but I really doubt that.</strong><hr></blockquote>
I haven't seen anything particularly detailed about OCEAN -- do you have any reference materials? If it was sufficiently fast it should be possible to pass instructions to and from on-chip units for dispatch & retirement. This is what Dorsal was implying, but unless we have some real documentation on OCEAN its hard to verify / deny. I said earlier that this thread might be the make/break thread for Dorsal, but perhaps it will be this particular post that proves he does or doesn't know what the hell he's talking about.
<strong>
The PowerMac G4 as we know it will be retired. Well the architecture will at least. We will see changes to the system bus, processor and general layout. Motorola has been hard at work with the 130nm G4. It will scale nicely (at least 1.5GHz by the summer) and have improved bus features. Memory access will be stellar. And you'll see why. not only will DDR SDRAM make a debut but it will not connect to the processor iin a conventional manner. More to come. Cache will also be increased on the processor level. Twice what is seen now. You will see a collaboration with another hardware company, but this will not surprise some of you in the know.
More to come.</strong><hr></blockquote>
This jibes with what I've heard as well, but as I understand it, this motherboard has been unfortunately delayed, and a stop-gap DDR motherboard is what we'll see first. We shall see...
great, wtf am I doing here.
G-news
<strong>This jibes with what I've heard as well, but as I understand it, this motherboard has been unfortunately delayed, and a stop-gap DDR motherboard is what we'll see first. We shall see...</strong><hr></blockquote>
But what is the difference between the "real" mobo and the "stop-gap" one? Is it the processor <-> memory connection or the chipset DSPs you were talking about?
Later
<strong>I hear that Apple will put out an RDF on the AGP so the PCI is 8x faster than the DDR on the UMA, but only if the 3GIO is ready from the OEM at a good MSRP. Then again I heard this on the D/L from someone at MOSR so I guess I'm SOL.
Later
That's all under NDA.