<strong>Okay, maybe I'm too optimistic, but why are many pushing the date so far out to get the IBM G5? Isn't it very possible that Apple realized long ago that Motorola would not be the most reliable supplier? Wouldn't Apple think twice about who should build the G5? Work could have started well over a year ago, maybe two. And with both Apple and nVidia as charter members of HyperTransport, wouldn't Apple be asking for such a bus on the G5? I believe samples of the G5 could have been undergoing tests for over six month already. I think it reasonable that IBM would delay talking about the G5, until it is about ready for production fab. I don't say that my opinion is right, but that it has just as good a chance of being right as those who expect a G5 at MWNY or later. I may be disappointed after October 15 or after MWSF, but I hope not.
To me, the new PowerMac case is a give away. It appears to be for higher power chips. It was introduced now for two reasons possibly. 1) It gives the impression that Apple is doing more to the PowerMac line now, when sales are hurting. 2) It makes for a quicker and easier introduction of the G5 when it is ready. There will be no new tooling for a new case. Sure, many would like to see some super nifty case for the G5, but I'll bet they will be happy just to get the G5 in today's case.</strong><hr></blockquote>
To supplement this line of thought, I can imagine a set of commercial circumstances where Apple annointed IBM to supply the fifth-generation PPC somewhile ago (thus providing the commercial justification for the technical and financial investment), but both parties elected to keep the development of said processor under embargo until a) it was no longer practicable to keep it quiet and b) Intel/AMD et al could not practically do anything to counter the development given their committed roadmaps and existing inertia.
To analogise, I develop cold fusion in absolute secrecy but only release the information to the public domain when all of my competitors have put a noose around their own neck building nuclear (fission) reactors: They are now imprisoned by their own inertia and their existing business model - they cannot drop the cost of the energy they generate as they have interest to pay on the debt used to fund the plants and they cannot walk away from the plants unless their position becomes commercially untenable resulting in Chapter 11 and worse.
If I were AIM, I would let Intel/AMD dig a hole and then push them into it: Itanium could be one half of that hole and P4 could be the other - I suspect the former is a lame duck, and I can hear the wheels of the latter slipping on the track as the fraudulent usage of clockspeed as the defining factor in a system's performance becomes more apparent.
Actually, the most interesting thing this says is:
[quote]<strong>a fully compliant implementation of the 64-bit PowerPC (TM) instruction set architecture</strong><hr></blockquote>
So, there is a 64-bit future for PPC - but we kind of knew that already.
And Rivina is nothing more than one instance of that future - "a fully compliant implementation" not "the definitive or sole implementation". There probably are other implementations, it's just we don't know about them.
[quote]Originally posted by Mark- Card Carrying FanaticRealist:
<strong>
. . . And Rivina is nothing more than one instance of that future - "a fully compliant implementation" not "the definitive or sole implementation". There probably are other implementations, it's just we don't know about them.
</strong><hr></blockquote>
Yes. The October 15th chip likely evolved from this Rivina. However, I am not as confident now that Apple was on top of processor development for a long time. Some of those reports gave me a cold chill, that Apple may have dropped the ball. Yet it is difficult to believe IBM developed such a processor without working with Apple, a really big potential customer. Maybe recent reports are just Apple's diversionary tactics to keep the troops in the dark. I hope.
Rivina looks like an advanced prototype. For one it lacks an L2 cache, something most modern processors have on die. Secondly only one integer unit? (FXU). 2 is a minimum now and even 2 FPU's is getting standard for a modern CPU. And lastly, this is made on a relatively old process. It is 2 generations behind modern processes. I think this processor will rear its head again... when it grows up a little more.
<strong>Apple's problems with processors is the with the G4 they bought on to once suppliers propriatary chip, thus limiting internal competition within the allicance to develop faster chips. Apple should have worked hard to keep IBM and Moto building and developing compatible chips that Apple could use.</strong><hr></blockquote>
Motorola owns the AltiVec trademark, and (most aspects of) the implementation of the VMX/Velocity Engine in the G4, but the spec for the unit is not proprietary to Motorola. Apple pushed for it - IIRC, the lead on the project was even an Apple employee, and IBM has a couple of patents related to it. IBM didn't ship a G4 when Mot did because it was too dead set on sticking to its RISC philosophy, rather than polluting its elegant designs with 162 extra instructions that could be farmed off to a coprocessor.
IBM has since come around, and is now on the same page as Apple and Motorola with respect to onboard vector coprocessors. Because of the patent- and technology-sharing enabled within (and around) the AIM alliance, there is nothing on Earth preventing IBM from implementing a vector unit that's compatible with the same spec that AltiVec is compatible with and shipping it on a PPC.
<strong>Rivina looks like an advanced prototype. For one it lacks an L2 cache, something most modern processors have on die. Secondly only one integer unit? (FXU). 2 is a minimum now and even 2 FPU's is getting standard for a modern CPU. And lastly, this is made on a relatively old process. It is 2 generations behind modern processes. I think this processor will rear its head again... when it grows up a little more.</strong><hr></blockquote>
You are right Apple Outsider it's an old prototype, checking the IBM link i have discovered that the paper discribing this chip was written in 2000, explaining many strange things about his species, the 0,22 process, the lack of L2 cache ...and the waste of space (look at the picture, many surfaces are unemployed).
It's seems that IBM have many projects in his hat, and has the strenght to make a new chip for Apple.
The new rumor about Apple not using IBM's new chip is so iffy that <a href="http://www.mosr.com"; target="_blank">even MOSR is having difficulty swallowing it.</a>
<strong>The new rumor about Apple not using IBM's new chip is so iffy</strong><hr></blockquote>
Might as well give my take on this. Having looked hard, I see no way in which AltiVec is incompatible with a power4 core. Certainly the core would have to be redesigned to allow for the extra registers/queues/decode/dispatch/etc., but it should be perfectly doable as some aspects of the core will have to be redesigned anyway.
IBM have, however, been working on book E implementations similar to Motorola's 8560 and 8540, these can have additional processing units attached to them, but not additional registers, meaning that it is technically impossible to add AltiVec to them without redesigning the core.
I suspect there is some confusion by the person originally quoted (IBM rep.) between the two chips. (Although it is possible, if very unlikely, that the new chip is a book E redesign of the power4 core.) Apple would have rightly rejected that were it to have been offered as a chip for their next power Mac.
"The 1GHz-plus multicore superscalar processor will incorporate a single-instruction, multiple-data engine along the same lines as Motorola's Altivec and support for RapidIO. "
"IBM will also add a SIMD engine to some of its upcoming PowerPC chips. ... IBM has the option to adopt Altivec, the multimedia SIMD engine used now by Motorola"
"Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition. Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs. "AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' " \t
[[[Yet it is difficult to believe IBM developed such a processor without working with Apple, a really big potential customer. ]]]
If not for Apple, then who the heck is IBM developing a *desktop* processor for in these already dismal times. Even the cheepy PCs aren't selling all that well and no one but Apple and Dell are making a profit at it. Other questions also arise:
- Who is the target base?
- Who will design the mobos for this desktop chip?
- What OS will it run?
- Who will code for this new beast?
- What tools will be available to work with it?
- Who will develop the tools?
- What does IBM look to accomplish by reentering the desktop market on it's own with a completely new processor?
- Who will develop the required apps that are needed to compete in the desktop arena? (Photoshop, AutoCAD, Lightwave, Office etc.)
- Why on earth add a *brand new* vector unit? They could use AltiVec. It's been out there, is widely used and has the support and tools already in place. (It just doesn't make sense.)
The list of questions goes on...
As stated in previously, IBM LACKS ALL of the above. In short, they don't have any answers or solutions to any of those questions if Apple *isn't* the answers. Apple certainly does seem to fit an awful lot of those questions.
Apple has:
- The installed base
- The Apps (consumer/commercial/UNIX et. al.)
- The development
- The Operating system
- wide support for *vector-development*/optimization from third-parties
- The demand
- Time-tested platform.
Again, the list goes on...
Furthermore, if the unit on the new chip *isn't* AltiVec then what the heck is IBM going through the trouble of adding AltiVec support into their Linux for? Remember this URL:
"The 1GHz-plus multicore superscalar processor will incorporate a single-instruction, multiple-data engine along the same lines as Motorola's Altivec and support for RapidIO. "
"IBM will also add a SIMD engine to some of its upcoming PowerPC chips. ... IBM has the option to adopt Altivec, the multimedia SIMD engine used now by Motorola"
"Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition. Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs. "AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' " \t
It seems that the next chip will be not strictly a power 4 derivative, but rather a book e core. This core can be very different than the one of Mot (8450) because book e definite mainly a set of instructions and a flexible architecture. Nothing prevent a book e core from IBM to be more superscalar or deeply pipelined than the mot counterpart.
The rivina prototype show that IBM has enough room to develop many differents versions of this chip. It means that for the future chip used in desktop he may not use the power 4 core, but a new core complying with the book e specifications.
Why is everyone so quick to assume that this new rumor is false? It makes far more sense that IBM would NOT be developing a desktop Power derivative CPU for Apple that includes Altivec. Why? Because IBM HATES Altivec, it doesn't fit with their philosophy of CPU design.
In favor of Macs using a new Power derivative, we have only a short abstract of a new desktop Power CPU. This CPU will supposedly have an SIMD unit, but it is not called Altivec nor is there any reason to think it is Altivec compatible, other than the # of instructions.
In contrast we have an explicit rumor that states IBM is NOT going to develop a desktop CPU for Apple that uses Altivec or is Altivec compatible.
For nearly a year rumor sites have been shoveling BS about the G4's successor, and NONE of these rumors has yet to be confirmed. The ugly truth is that Apple is going to continue taking it over a barrel with regards to computing performance and power, and there isn't a damn thing they can do about it short of switching to x86. Jobs has even said that Apple will have options AFTER the migration to OS X is complete. If IBM really was about to deliver a desktop Power CPU that is altivec compatible, then Apple would have no need to wait on migration to OS X, because the CPU would feature backwards compatibility.
Face it everyone: There is no future for Apple in computing performance. Apple has painted themselves into a corner by putting all their eggs in the G4 basket, and they are at the mercy of Motorola's G4 plans. Currently, the G4 will continue to get small, incremental updates that fall short of what is needed if Apple is going to make computers that are competitive with Wintel performance.
It sucks but it's true: This new rumor is highly believable because it doesn't predict anything positive for Apple. We've been swallowing rumors about major design revisions to the G4, and about an ass-kickin' G5 for too long, and not a single of these rumors has ever come to fruition. Apple will keep taking it in the arse from Motorola until either Apple or Moto go under.....and the way Powermacs are comparing to Wintels, it's not going to be long before Apple's antiquated hardware pulls them under.
Just accept it: game over. We're all going to be stuck using Wintels within 5 years. I've already resigned to the fact that I'll not be able to replace my Powermac G4 with another Mac, all because Apple is going down.
As proof, we need only look at the success of OS X. OS X, particularly Jaguar, is consistently described as a superior alternative to Windows by its reviewers...even Wintel dorks are praising Jaguar as the best computer OS available today. Yet even with OS X's clear superiority to Windows, Mac sales are dismal, adoption of OS X is stagnating, and the Mac community is still waiting on many key developers for OS X support.
If something as awesome as OS X doesn't help Apple's market share grow, then something as pathetic as Apple's hardware will only serve as Apple's ball and chain. Even when Apple demolishes the competition, they can only stand still and hang onto their current market share by their fingernails.
<strong>It seems that the next chip will be not strictly a power 4 derivative, but rather a book e core. This core can be very different than the one of Mot (8450) because book e definite mainly a set of instructions and a flexible architecture. Nothing prevent a book e core from IBM to be more superscalar or deeply pipelined than the mot counterpart.</strong><hr></blockquote>
As long as they don't try to implement the vector unit with register sharing, Ã* la SSE2. There's no way IBM could split a 128-bit vector into two integer registers and attempt a permute instruction on them at any reasonable speed. It would be like the bad old days when VAXen roamed the earth: The VAX CPU family had an instruction to solve quadratic equations(!!) that took something like 40 cycles to run. This is exactly the kind of silliness that RISC tried to get away from in the first place.
For a vector processor as ambitious as VMX is to work, it has to be on-chip and it has to have its own register set. Maybe IBM can fudge a few of the instructions, but there's no way they can simulate the whole thing on a standard RISC core and expect any kind of performance at all.
As long as they don't try to implement the vector unit with register sharing, Ã* la SSE2. There's no way IBM could split a 128-bit vector into two integer registers and attempt a permute instruction on them at any reasonable speed. It would be like the bad old days when VAXen roamed the earth: The VAX CPU family had an instruction to solve quadratic equations(!!) that took something like 40 cycles to run. This is exactly the kind of silliness that RISC tried to get away from in the first place.
For a vector processor as ambitious as VMX is to work, it has to be on-chip and it has to have its own register set. Maybe IBM can fudge a few of the instructions, but there's no way they can simulate the whole thing on a standard RISC core and expect any kind of performance at all.</strong><hr></blockquote>
Do you mean that the new chip if it exist cannot be based upon a book e architecture due to the lack of 128 bot register ?
[quote] Because IBM HATES Altivec, it doesn't fit with their philosophy of CPU design. <hr></blockquote>
Uh, no. IBM hated SIMD, not Altivec in particular. The fact that this new chip has a SIMD unit should clue you in to the fact that they've changed their mind...
[quote] This CPU will supposedly have an SIMD unit, but it is not called Altivec nor is there any reason to think it is Altivec compatible, other than the # of instructions. <hr></blockquote>
Why would it be called Altivec? That's Moto's name for their implementation of VMX. Hell, Apple refers to it as the Velocity Engine. It stands to reason that IBM would make their SIMD Altivec compatible-- they helped create it, for one thing. Why shitcan all that research? Also, they'd be able to take immediate advantage of the fact that there are programmers who know how to write code for it, and all of the code that's been written by Apple & Moto. It really wouldn't make sense for it not to be Altivec compatible.
[quote] In contrast we have an explicit rumor that states IBM is NOT going to develop a desktop CPU for Apple that uses Altivec or is Altivec compatible. <hr></blockquote>
Uh, no. We've got an off-the-cuff remark from someone who spoke to an IBM engineer who may or may not know who IBM's clients are for the new chip. To present it as anything more than that is silly.
Besides, we'll know one way or the other for certain on Oct. 15. Don't get your panties in a bunch over little rumors like this.
[quote] Face it everyone: There is no future for Apple in computing performance. <hr></blockquote>
Ask the mot guy two questions : is this new desktop chip have a new core, 32 bits or 64 bits and a new bus interface aka rapid I/O
</strong><hr></blockquote>
I think we already know the answers to all of those questions
A Mot chip would probably be primarily 32 bit, though it might have a 64 bit mode. It would have RIO - all their newer products do, and it's a big step up from MAXbus -> almost mandatory.
An IBM chip would be a close relative to the one they are going to discuss Oct 15 on the Microprocessor forum. -> 64bit, possibly with a 32 bit mode Yes to a vector unit, yes to RIO, yes to it being 'AltiVec' though it would be called by IBM's name for the same - VMX. One question is - does it have _all_ of the G4's AV instructions included? If it started as a design to fill some of IBM's needs for 64bit chips, the AV unit might be two 64-bit logic units tied together... which makes some of the AV instructions tough. Would it still be a great chip? Sure! For IBM. It might not pass muster for Apple if the 'missing instructions' were particularly important somewhere crucial in the OS.
The thing is: I don't think I care anymore which manufacturer it comes from. If it comes from IBM, great - they've made a compelling case for their CPU and their willingness to perform. I can live with that. And the suspected IBM chip sounds great (Plus there's no way _any_ IBM proposed chip would ever be a FP slouch, where my particular interests lie)
If it comes from Mot then they must have _really_ convinced Apple that it is a screamer. After dropping the ball not once but _twice_, there had better be some serious smoke out of their next offering. I can deal with that, even if I have to throw out my smoke detector
Do you mean that the new chip if it exist cannot be based upon a book e architecture due to the lack of 128 bot register ?</strong><hr></blockquote>
Not really. Not because it's technically impossible, but because it's pointless. This might be another reason why IBM has resisted AltiVec - it's an add-on to the core, not an auxiliary unit.
<strong>If it comes from Mot then they must have _really_ convinced Apple that it is a screamer. After dropping the ball not once but _twice_, there had better be some serious smoke out of their next offering. I can deal with that, even if I have to throw out my smoke detector </strong><hr></blockquote>
Mot doesn't really need to do much. Take a 7455, add an FP unit, a memory controller and RIO support, keep it MP friendly, and die-shrink it to .09. There's your screaming 32-bit chip. The biggest advances would be the additional FP and (especially) the RapidIO, since the current 7455 is hobbled by low bandwidth.
Not really. Not because it's technically impossible, but because it's pointless. This might be another reason why IBM has resisted AltiVec - it's an add-on to the core, not an auxiliary unit.</strong><hr></blockquote>
So Amorph you consider this as craps ? :
"Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition. Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs. "AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' "
Comments
<strong>Okay, maybe I'm too optimistic, but why are many pushing the date so far out to get the IBM G5? Isn't it very possible that Apple realized long ago that Motorola would not be the most reliable supplier? Wouldn't Apple think twice about who should build the G5? Work could have started well over a year ago, maybe two. And with both Apple and nVidia as charter members of HyperTransport, wouldn't Apple be asking for such a bus on the G5? I believe samples of the G5 could have been undergoing tests for over six month already. I think it reasonable that IBM would delay talking about the G5, until it is about ready for production fab. I don't say that my opinion is right, but that it has just as good a chance of being right as those who expect a G5 at MWNY or later. I may be disappointed after October 15 or after MWSF, but I hope not.
To me, the new PowerMac case is a give away. It appears to be for higher power chips. It was introduced now for two reasons possibly. 1) It gives the impression that Apple is doing more to the PowerMac line now, when sales are hurting. 2) It makes for a quicker and easier introduction of the G5 when it is ready. There will be no new tooling for a new case. Sure, many would like to see some super nifty case for the G5, but I'll bet they will be happy just to get the G5 in today's case.</strong><hr></blockquote>
To supplement this line of thought, I can imagine a set of commercial circumstances where Apple annointed IBM to supply the fifth-generation PPC somewhile ago (thus providing the commercial justification for the technical and financial investment), but both parties elected to keep the development of said processor under embargo until a) it was no longer practicable to keep it quiet and b) Intel/AMD et al could not practically do anything to counter the development given their committed roadmaps and existing inertia.
To analogise, I develop cold fusion in absolute secrecy but only release the information to the public domain when all of my competitors have put a noose around their own neck building nuclear (fission) reactors: They are now imprisoned by their own inertia and their existing business model - they cannot drop the cost of the energy they generate as they have interest to pay on the debt used to fund the plants and they cannot walk away from the plants unless their position becomes commercially untenable resulting in Chapter 11 and worse.
If I were AIM, I would let Intel/AMD dig a hole and then push them into it: Itanium could be one half of that hole and P4 could be the other - I suspect the former is a lame duck, and I can hear the wheels of the latter slipping on the track as the fraudulent usage of clockspeed as the defining factor in a system's performance becomes more apparent.
[quote]<strong>a fully compliant implementation of the 64-bit PowerPC (TM) instruction set architecture</strong><hr></blockquote>
So, there is a 64-bit future for PPC - but we kind of knew that already.
And Rivina is nothing more than one instance of that future - "a fully compliant implementation" not "the definitive or sole implementation". There probably are other implementations, it's just we don't know about them.
<strong>
. . . And Rivina is nothing more than one instance of that future - "a fully compliant implementation" not "the definitive or sole implementation". There probably are other implementations, it's just we don't know about them.
</strong><hr></blockquote>
Yes. The October 15th chip likely evolved from this Rivina. However, I am not as confident now that Apple was on top of processor development for a long time. Some of those reports gave me a cold chill, that Apple may have dropped the ball. Yet it is difficult to believe IBM developed such a processor without working with Apple, a really big potential customer. Maybe recent reports are just Apple's diversionary tactics to keep the troops in the dark. I hope.
<strong>Apple's problems with processors is the with the G4 they bought on to once suppliers propriatary chip, thus limiting internal competition within the allicance to develop faster chips. Apple should have worked hard to keep IBM and Moto building and developing compatible chips that Apple could use.</strong><hr></blockquote>
Motorola owns the AltiVec trademark, and (most aspects of) the implementation of the VMX/Velocity Engine in the G4, but the spec for the unit is not proprietary to Motorola. Apple pushed for it - IIRC, the lead on the project was even an Apple employee, and IBM has a couple of patents related to it. IBM didn't ship a G4 when Mot did because it was too dead set on sticking to its RISC philosophy, rather than polluting its elegant designs with 162 extra instructions that could be farmed off to a coprocessor.
IBM has since come around, and is now on the same page as Apple and Motorola with respect to onboard vector coprocessors. Because of the patent- and technology-sharing enabled within (and around) the AIM alliance, there is nothing on Earth preventing IBM from implementing a vector unit that's compatible with the same spec that AltiVec is compatible with and shipping it on a PPC.
[edited for clarity]
[ 09-08-2002: Message edited by: Amorph ]</p>
<strong>Rivina looks like an advanced prototype. For one it lacks an L2 cache, something most modern processors have on die. Secondly only one integer unit? (FXU). 2 is a minimum now and even 2 FPU's is getting standard for a modern CPU. And lastly, this is made on a relatively old process. It is 2 generations behind modern processes. I think this processor will rear its head again... when it grows up a little more.</strong><hr></blockquote>
You are right Apple Outsider it's an old prototype, checking the IBM link i have discovered that the paper discribing this chip was written in 2000, explaining many strange things about his species, the 0,22 process, the lack of L2 cache ...and the waste of space (look at the picture, many surfaces are unemployed).
It's seems that IBM have many projects in his hat, and has the strenght to make a new chip for Apple.
[ 09-08-2002: Message edited by: CharlesS ]</p>
<strong>The new rumor about Apple not using IBM's new chip is so iffy</strong><hr></blockquote>
Might as well give my take on this. Having looked hard, I see no way in which AltiVec is incompatible with a power4 core. Certainly the core would have to be redesigned to allow for the extra registers/queues/decode/dispatch/etc., but it should be perfectly doable as some aspects of the core will have to be redesigned anyway.
IBM have, however, been working on book E implementations similar to Motorola's 8560 and 8540, these can have additional processing units attached to them, but not additional registers, meaning that it is technically impossible to add AltiVec to them without redesigning the core.
I suspect there is some confusion by the person originally quoted (IBM rep.) between the two chips. (Although it is possible, if very unlikely, that the new chip is a book E redesign of the power4 core.) Apple would have rightly rejected that were it to have been offered as a chip for their next power Mac.
Michael
"The 1GHz-plus multicore superscalar processor will incorporate a single-instruction, multiple-data engine along the same lines as Motorola's Altivec and support for RapidIO. "
From here:
<a href="http://www.electronicstimes.com/tech/news/OEG20010601S0027"; target="_blank">http://www.electronicstimes.com/tech/news/OEG20010601S0027</a>;
----------------------------------------------------------------------------------
"IBM will also add a SIMD engine to some of its upcoming PowerPC chips. ... IBM has the option to adopt Altivec, the multimedia SIMD engine used now by Motorola"
From here:
<a href="http://news.com.com/2100-1001-257421.html?legacy=cnet"; target="_blank">http://news.com.com/2100-1001-257421.html?legacy=cnet</a>;
----------------------------------------------------------------------------------------------------
"Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition. Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs. "AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' " \t
From here:
\t
<a href="http://www.eetimes.com/story/OEG19990507S0003"; target="_blank">http://www.eetimes.com/story/OEG19990507S0003</a>;
--------------------------------------------------------------
--
Ed M.
If not for Apple, then who the heck is IBM developing a *desktop* processor for in these already dismal times. Even the cheepy PCs aren't selling all that well and no one but Apple and Dell are making a profit at it. Other questions also arise:
- Who is the target base?
- Who will design the mobos for this desktop chip?
- What OS will it run?
- Who will code for this new beast?
- What tools will be available to work with it?
- Who will develop the tools?
- What does IBM look to accomplish by reentering the desktop market on it's own with a completely new processor?
- Who will develop the required apps that are needed to compete in the desktop arena? (Photoshop, AutoCAD, Lightwave, Office etc.)
- Why on earth add a *brand new* vector unit? They could use AltiVec. It's been out there, is widely used and has the support and tools already in place. (It just doesn't make sense.)
The list of questions goes on...
As stated in previously, IBM LACKS ALL of the above. In short, they don't have any answers or solutions to any of those questions if Apple *isn't* the answers. Apple certainly does seem to fit an awful lot of those questions.
Apple has:
- The installed base
- The Apps (consumer/commercial/UNIX et. al.)
- The development
- The Operating system
- wide support for *vector-development*/optimization from third-parties
- The demand
- Time-tested platform.
Again, the list goes on...
Furthermore, if the unit on the new chip *isn't* AltiVec then what the heck is IBM going through the trouble of adding AltiVec support into their Linux for? Remember this URL:
<a href="http://gcc.gnu.org/ml/gcc-patches/2002-08/msg01480.html"; target="_blank">http://gcc.gnu.org/ml/gcc-patches/2002-08/msg01480.html</a>;
It's gotta be AltiVec on that thing. This CPU fits Apple's plans to perfectly.
I brought up many of these points in an earlier post that can be found <a href="http://forums.appleinsider.com/cgi-bin/ultimatebb.cgi?ubb=get_topic&f=1&t=002302&p=9"; target="_blank">here</a>
--
Ed M.
<strong>---------------------------------------------------------------------------------
"The 1GHz-plus multicore superscalar processor will incorporate a single-instruction, multiple-data engine along the same lines as Motorola's Altivec and support for RapidIO. "
From here:
<a href="http://www.electronicstimes.com/tech/news/OEG20010601S0027"; target="_blank">http://www.electronicstimes.com/tech/news/OEG20010601S0027</a>;
----------------------------------------------------------------------------------
"IBM will also add a SIMD engine to some of its upcoming PowerPC chips. ... IBM has the option to adopt Altivec, the multimedia SIMD engine used now by Motorola"
From here:
<a href="http://news.com.com/2100-1001-257421.html?legacy=cnet"; target="_blank">http://news.com.com/2100-1001-257421.html?legacy=cnet</a>;
----------------------------------------------------------------------------------------------------
"Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition. Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs. "AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' " \t
From here:
\t
<a href="http://www.eetimes.com/story/OEG19990507S0003"; target="_blank">http://www.eetimes.com/story/OEG19990507S0003</a>;
--------------------------------------------------------------
--
Ed M.</strong><hr></blockquote>
Thanks for the info and the links.
It seems that the next chip will be not strictly a power 4 derivative, but rather a book e core. This core can be very different than the one of Mot (8450) because book e definite mainly a set of instructions and a flexible architecture. Nothing prevent a book e core from IBM to be more superscalar or deeply pipelined than the mot counterpart.
The rivina prototype show that IBM has enough room to develop many differents versions of this chip. It means that for the future chip used in desktop he may not use the power 4 core, but a new core complying with the book e specifications.
In favor of Macs using a new Power derivative, we have only a short abstract of a new desktop Power CPU. This CPU will supposedly have an SIMD unit, but it is not called Altivec nor is there any reason to think it is Altivec compatible, other than the # of instructions.
In contrast we have an explicit rumor that states IBM is NOT going to develop a desktop CPU for Apple that uses Altivec or is Altivec compatible.
For nearly a year rumor sites have been shoveling BS about the G4's successor, and NONE of these rumors has yet to be confirmed. The ugly truth is that Apple is going to continue taking it over a barrel with regards to computing performance and power, and there isn't a damn thing they can do about it short of switching to x86. Jobs has even said that Apple will have options AFTER the migration to OS X is complete. If IBM really was about to deliver a desktop Power CPU that is altivec compatible, then Apple would have no need to wait on migration to OS X, because the CPU would feature backwards compatibility.
Face it everyone: There is no future for Apple in computing performance. Apple has painted themselves into a corner by putting all their eggs in the G4 basket, and they are at the mercy of Motorola's G4 plans. Currently, the G4 will continue to get small, incremental updates that fall short of what is needed if Apple is going to make computers that are competitive with Wintel performance.
It sucks but it's true: This new rumor is highly believable because it doesn't predict anything positive for Apple. We've been swallowing rumors about major design revisions to the G4, and about an ass-kickin' G5 for too long, and not a single of these rumors has ever come to fruition. Apple will keep taking it in the arse from Motorola until either Apple or Moto go under.....and the way Powermacs are comparing to Wintels, it's not going to be long before Apple's antiquated hardware pulls them under.
Just accept it: game over. We're all going to be stuck using Wintels within 5 years. I've already resigned to the fact that I'll not be able to replace my Powermac G4 with another Mac, all because Apple is going down.
As proof, we need only look at the success of OS X. OS X, particularly Jaguar, is consistently described as a superior alternative to Windows by its reviewers...even Wintel dorks are praising Jaguar as the best computer OS available today. Yet even with OS X's clear superiority to Windows, Mac sales are dismal, adoption of OS X is stagnating, and the Mac community is still waiting on many key developers for OS X support.
If something as awesome as OS X doesn't help Apple's market share grow, then something as pathetic as Apple's hardware will only serve as Apple's ball and chain. Even when Apple demolishes the competition, they can only stand still and hang onto their current market share by their fingernails.
Game over.
<strong>It seems that the next chip will be not strictly a power 4 derivative, but rather a book e core. This core can be very different than the one of Mot (8450) because book e definite mainly a set of instructions and a flexible architecture. Nothing prevent a book e core from IBM to be more superscalar or deeply pipelined than the mot counterpart.</strong><hr></blockquote>
As long as they don't try to implement the vector unit with register sharing, Ã* la SSE2. There's no way IBM could split a 128-bit vector into two integer registers and attempt a permute instruction on them at any reasonable speed. It would be like the bad old days when VAXen roamed the earth: The VAX CPU family had an instruction to solve quadratic equations(!!) that took something like 40 cycles to run. This is exactly the kind of silliness that RISC tried to get away from in the first place.
For a vector processor as ambitious as VMX is to work, it has to be on-chip and it has to have its own register set. Maybe IBM can fudge a few of the instructions, but there's no way they can simulate the whole thing on a standard RISC core and expect any kind of performance at all.
<strong>
As long as they don't try to implement the vector unit with register sharing, Ã* la SSE2. There's no way IBM could split a 128-bit vector into two integer registers and attempt a permute instruction on them at any reasonable speed. It would be like the bad old days when VAXen roamed the earth: The VAX CPU family had an instruction to solve quadratic equations(!!) that took something like 40 cycles to run. This is exactly the kind of silliness that RISC tried to get away from in the first place.
For a vector processor as ambitious as VMX is to work, it has to be on-chip and it has to have its own register set. Maybe IBM can fudge a few of the instructions, but there's no way they can simulate the whole thing on a standard RISC core and expect any kind of performance at all.</strong><hr></blockquote>
Do you mean that the new chip if it exist cannot be based upon a book e architecture due to the lack of 128 bot register ?
Uh, no. IBM hated SIMD, not Altivec in particular. The fact that this new chip has a SIMD unit should clue you in to the fact that they've changed their mind...
[quote] This CPU will supposedly have an SIMD unit, but it is not called Altivec nor is there any reason to think it is Altivec compatible, other than the # of instructions. <hr></blockquote>
Why would it be called Altivec? That's Moto's name for their implementation of VMX. Hell, Apple refers to it as the Velocity Engine. It stands to reason that IBM would make their SIMD Altivec compatible-- they helped create it, for one thing. Why shitcan all that research? Also, they'd be able to take immediate advantage of the fact that there are programmers who know how to write code for it, and all of the code that's been written by Apple & Moto. It really wouldn't make sense for it not to be Altivec compatible.
[quote] In contrast we have an explicit rumor that states IBM is NOT going to develop a desktop CPU for Apple that uses Altivec or is Altivec compatible. <hr></blockquote>
Uh, no. We've got an off-the-cuff remark from someone who spoke to an IBM engineer who may or may not know who IBM's clients are for the new chip. To present it as anything more than that is silly.
Besides, we'll know one way or the other for certain on Oct. 15. Don't get your panties in a bunch over little rumors like this.
[quote] Face it everyone: There is no future for Apple in computing performance. <hr></blockquote>
Tell us what you really think, JYD.
[quote] Game over. <hr></blockquote>
You'll be back. They always come back.
<strong>
Ask the mot guy two questions : is this new desktop chip have a new core, 32 bits or 64 bits and a new bus interface aka rapid I/O
</strong><hr></blockquote>
I think we already know the answers to all of those questions
A Mot chip would probably be primarily 32 bit, though it might have a 64 bit mode. It would have RIO - all their newer products do, and it's a big step up from MAXbus -> almost mandatory.
An IBM chip would be a close relative to the one they are going to discuss Oct 15 on the Microprocessor forum. -> 64bit, possibly with a 32 bit mode
The thing is: I don't think I care anymore which manufacturer it comes from. If it comes from IBM, great - they've made a compelling case for their CPU and their willingness to perform. I can live with that. And the suspected IBM chip sounds great
If it comes from Mot then they must have _really_ convinced Apple that it is a screamer. After dropping the ball not once but _twice_, there had better be some serious smoke out of their next offering. I can deal with that, even if I have to throw out my smoke detector
<strong>
Do you mean that the new chip if it exist cannot be based upon a book e architecture due to the lack of 128 bot register ?</strong><hr></blockquote>
Not really. Not because it's technically impossible, but because it's pointless. This might be another reason why IBM has resisted AltiVec - it's an add-on to the core, not an auxiliary unit.
<strong>If it comes from Mot then they must have _really_ convinced Apple that it is a screamer. After dropping the ball not once but _twice_, there had better be some serious smoke out of their next offering. I can deal with that, even if I have to throw out my smoke detector
Mot doesn't really need to do much. Take a 7455, add an FP unit, a memory controller and RIO support, keep it MP friendly, and die-shrink it to .09. There's your screaming 32-bit chip. The biggest advances would be the additional FP and (especially) the RapidIO, since the current 7455 is hobbled by low bandwidth.
<strong>
Not really. Not because it's technically impossible, but because it's pointless. This might be another reason why IBM has resisted AltiVec - it's an add-on to the core, not an auxiliary unit.</strong><hr></blockquote>
So Amorph you consider this as craps ? :
"Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition. Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs. "AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' "