But it really depends on how Apple viewed the 1.8 addition, if they think that it was an update then they would have a different out look on it than we do. Did anything else change with the rest of the line? Like a slightly different chip set for the entire line? It doesn't have to be a faster processor to make it an update. Look at it like this: Apple waited a year and had little to show for it. IBM knows that they let Steve down not a way to a good working relationship. IBM and Apple know that they really need to come through. IBM recognized maybe early that clock speed was ending its life as an easy way to add performance. IBM had lots of experience using many different technologies on other chips for other customers. Maybe IBM made the original cell using a G5 and VMX units, ok maybe not. But I expect big things, because IBM has had lots of time to work on the problem. Time will tell.
Nice to hear some very positive G5 thoughts in here. I hope your right.
This will surely get a lot of attention at FOSE, April 5-7
Mar 1, 9:30 PM (ET)
By MATTHEW FORDAHL
SAN FRANCISCO (AP) - Promising improved performance without greatly increased power needs, Intel Corp. (INTC) unveiled details Tuesday of upcoming microprocessors that will put two or more computing engines on a single chip.
The world's largest chip maker plans to use the technology across its processor lines, from those powering mobile computers to the brains of high-end servers. In all, Intel has 15 projects under way developing dual-core or multi-core chips.
Intel plans to launch dual-core desktop chips in the second quarter, offering two varieties geared toward high-end and mainstream users, respectively. It's also planning dual-core and multicore chips for servers and notebooks for release later this year and in 2006.
The high-end desktop chip, dubbed the Intel Pentium Processor Extreme Edition, will run at 3.2 gigahertz - slower than the 3.8 GHz of today's top-of-the-line Pentium 4. Still, during one demonstration, it performed a task in half the time of its single-core counterpart.
Stephen Smith, vice president of Intel's Digital Enterprise Group, said performance improvements will vary depending on the job. Multicore chips offer the greatest improvement when the software is designed to distribute tasks over the multiple engines.
But the technology also should improve performance when multiple programs are running at the same time, he added. All modern PCs typically have several pieces of software working in the background, including antivirus tools, network utilities and others.
Also, the Extreme Edition's cores will use a technology that essentially nearly doubles the amount of work that can be handled by each core. Because of this, the operating system will work as though there are four cores, instead of the physical two.
The mainstream processor, dubbed the Pentium D, won't have that feature enabled. Smith also did not indicate that chip's clock speed.
The new processors' prices were not disclosed.
Intel isn't alone in bringing multicore chips to market. Rival Advanced Micro Devices also has plans to launch dual-core chips later this year.
And a trio of companies - International Business Machines Corp. (IBM), Toshiba Corp. and Sony Corp. (SNE) - are building a multicore chip based on a completely new architecture. It's expected to power Sony's next-generation PlayStation game console, among other devices.
The industry's move toward multicore processors comes as the number of transistors crammed on a single chip continues to increase in accordance with a famous prediction made by Intel co-founder Gordon Moore in 1965.
But while higher clock speeds are resulting in greater power demands, that is not translating into major gains in performance, threatening the historical growth in computing capabilities.
"It's the way the industry is going to be able to continue Moore's Law going forward by increasing the processing power in an exponential fashion over time," Intel CEO Craig Barrett told reporters at the company's forum for developers.
I thought IBM already made dual core Power processors, and announced this was going into the 9xx PPC architecture way before AMD. I like how they forgot to mention that processor. I hope IBM, and Apple beat them all to the punch on this. Come on WWDC.
... "It's the way the industry is going to be able to continue Moore's Law going forward by increasing the processing power in an exponential fashion over time," Intel CEO Craig Barrett told reporters at the company's forum for developers.
That's funny. After they say that growth in transistors is not increasing performance, then this. I guess the exponent in the "exponential growth" is less than 1.
I thought IBM already made dual core Power processors, and announced this was going into the 9xx PPC architecture way before AMD.
Yes, they make for quite some time now dual core Power processors, but where did they announce that this technology will make it down to the PPC9xx? I am not aware of any announcement like this.
Quote:
I hope IBM, and Apple beat them all to the punch on this. Come on WWDC.
IBM has beaten them long ago. But I doubt the duette Apple/IBM is so close to a dual core PPC9xx-based Power Mac release. Even if this happens in WWDC, in practice we talk rather about a parallel (PPC vs. x86) introduction of dual core processors and no about some advantage of the PPC side. Sad I would say, if one takes into account the long experience of IBM in these matters.
At early appearances I think AMD will still have a leg up on all of them, unless IBM starts using an on die memory controller which is what seems to give AMD all that power. You would think that being in a multi billion dollar company IBM processor designers would have figured this out already, and know exactly what to do. But you never know...
WOW! You design computer processors. You must be really smart? Duuuhhh.. I guess. \
At early appearances I think AMD will still have a leg up on all of them, unless IBM starts using an on die memory controller which is what seems to give AMD all that power. You would think that being in a multi billion dollar company IBM processor designers would have figured this out already, and know exactly what to do. But you never know...
WOW! You design computer processors. You must be really smart? Duuuhhh.. I guess. \
Actually the power5 and power4 processors have on-die memory controllers, its just the 970 family that doesn't. I think this has something to do with apple? I also believe IBM was the FIRST company to design on-die memory controllers.
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
Sure, it's possible. Just run two busses off the chip to a dual-ported memory controller.
You'll never see that in practice, though, because there's no reason to prefer that arrangement to an integrated memory controller. Busses traced across the motherboard are slower, more prone to interference, and more costly than on-chip busses.
I expect dual-core PPCs to start popping out of the woodwork this year and early next year. This is going to be an industry-wide transition.
You'll never see that in practice, though, because there's no reason to prefer that arrangement to an integrated memory controller. Busses traced across the motherboard are slower, more prone to interference, and more costly than on-chip busses.
I started thinking about that after I posted, anything is possible but who would be stupid enough to do it, the performance decrease would be too much... But like you said its more expensive and more prone to interference. Thanks AMorph.
Before people get all moist over Ondie memory controller let's temper that with a little info.
It's my understanding that on ondie memory controller benefits you chiefly in applications where memory latency is more imporant than overall bandwidth. Thus an Opteron will "kill" a Xeon in applications where latency is the prime pain point rather than massive througput.
I think sometimes at the desktop level IBM/Intel are loathe to utilize the extra transistors needed. Plus you have to make sure you have supported the right memory types or you'll have to add and external controller. I realize that now DDR is standard but soon we'll have XDR from Rambus and FB-DIMM from Intel. The market is going to have a bit of a shakeup possibly.
Before people get all moist over Ondie memory controller let's temper that with a little info.
It's my understanding that on ondie memory controller benefits you chiefly in applications where memory latency is more imporant than overall bandwidth. Thus an Opteron will "kill" a Xeon in applications where latency is the prime pain point rather than massive througput.
I think sometimes at the desktop level IBM/Intel are loathe to utilize the extra transistors needed. Plus you have to make sure you have supported the right memory types or you'll have to add and external controller. I realize that now DDR is standard but soon we'll have XDR from Rambus and FB-DIMM from Intel. The market is going to have a bit of a shakeup possibly.
You said a lot, but are you just throwing that out there, or is there a point to it. I'm getting interested in this possible on die controller news, but I'm not sure what it was you were getting at. Were you getting at anything?
I think he means there are advantages and disadvantages to onchip memory controllers. Also that the technology can change from pros and cons to just pros?
I think he means there are advantages and disadvantages to onchip memory controllers. Also that the technology can change from pros and cons to just pros?
Mainly my post is meant to temper excessive enthusiasm. Because on the intarweb you'll frequently see.
"OMFG!!!!!!!1111 Apple duzn't have teh Ondie mem controllerz..tehy suck!"
I think OMC will come (Freescale and 9XX chips) but I realize why IBM isn't putting them in the cpus yet. Sorry that my point wasn't that clear. I sincerely try to look at both sides of the coin but I have my bias like anyone.
Actually the power5 and power4 processors have on-die memory controllers, its just the 970 family that doesn't. I think this has something to do with apple? I also believe IBM was the FIRST company to design on-die memory controllers.
Actually I think power has dedicated interfaces to off chip controllers. They aren't hooking directly to DDR memory with those guys.
Quote:
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
Sadly this is wrong. Modern processors have an independant bus interface. That bus interface unit can be designed to communicate with two or more processors. Actually the unit is often communicating with the Cache. Adding another processor is not a big deal. What you do end up with is the potential for a squeeze on the FSB, that is not enough band width to effectively support both processors.
AS to what IBM/Apple will actually offer up that will be very interesting indeed. First we have to wonder how far the FSB can go beyond 1.5GHz. My thinking is that they would be far better off with an onboard memory controller, but Apple would really have to model this with the work loads they expect. There may be advantage to having the DMA circuitry off chip as the inteaction with the video card may be an issue.
Frankly I suspect that inorder to be really successfull and accomplish what Apple would want to accomplish they would have to implement a PPC chip with both a memory controller and an interface to the video card. Today that Video interface would be PCI-Express.
Actually I think power has dedicated interfaces to off chip controllers. They aren't hooking directly to DDR memory with those guys.
Power4 has an inline cache and memory architecture where the memory controllers are off-chip, inline with the off-chip L3 cache and on-chip L3 cache controllor. The main memory controller is in the off-chip L3 device. Main memory traffic had to go through all levels of cache to get to the processor.
Power5 has more of a backside cache and memory architecture where there is an on-chip backside L3 cache controller with off-chip L3 cache and an on-chip main memory controller. That is, main memory traffic didn't have to go through the L3 cache bus to get to L2 cache like in Power4. Main memory traffic can go directly to L2.
Quote:
Sadly this is wrong. Modern processors have an independant bus interface. That bus interface unit can be designed to communicate with two or more processors. Actually the unit is often communicating with the Cache. Adding another processor is not a big deal. What you do end up with is the potential for a squeeze on the FSB, that is not enough band width to effectively support both processors.
Very true, and in fact, reality for Intel. Intel's first gen dual core chips will use one Pentium GTL+ (whatever it is called and is now) front side bus to the system ASIC. The Pentium bus is a shared processor bus much like the Moto G4 processors where multiple processors can reside on one bus. Intel is just putting two Prescotts on one processor bus on the same chip. Said processor bus goes to the northbride (system ASIC) for main memory.
Always fear Intel though. They will be moving to multiple processor buses (FSBs) in later generations. Centrino dual-core chips will likely have an on-die memory controller, so all their bases are covered.
Quote:
AS to what IBM/Apple will actually offer up that will be very interesting indeed. First we have to wonder how far the FSB can go beyond 1.5GHz. My thinking is that they would be far better off with an onboard memory controller, but Apple would really have to model this with the work loads they expect. There may be advantage to having the DMA circuitry off chip as the inteaction with the video card may be an issue.
Simplest case should just be dual-core 970 with a large shared L2 cache (2 MB?) using the elastic processor bus. Provides minimal changes, like drop-in replacement, for Apple's architecture. I'm expecting Antares to be like this.
If it is dual-core with on-die memory controller, Apple will have to come up with a brand new Macintosh architecture with new core logic chipsets. That's a lot of work.
Quote:
Frankly I suspect that inorder to be really successfull and accomplish what Apple would want to accomplish they would have to implement a PPC chip with both a memory controller and an interface to the video card. Today that Video interface would be PCI-Express.
Hey, I suggested that 6 years ago. Also, Apple should have started an in-house fabless chip design group to design their processors and chipsets as well. As it was and is now, they can't even get IBM and Moto to do the little things to improve performance like more L2 cache or better FSB. They could have supported PC4000 or PC4400 DDR SDRAM for their 2+ GHz G5 systems too, but haven't, so they themselves have been laggards.
Comments
Originally posted by Brendon
But it really depends on how Apple viewed the 1.8 addition, if they think that it was an update then they would have a different out look on it than we do. Did anything else change with the rest of the line? Like a slightly different chip set for the entire line? It doesn't have to be a faster processor to make it an update. Look at it like this: Apple waited a year and had little to show for it. IBM knows that they let Steve down not a way to a good working relationship. IBM and Apple know that they really need to come through. IBM recognized maybe early that clock speed was ending its life as an easy way to add performance. IBM had lots of experience using many different technologies on other chips for other customers. Maybe IBM made the original cell using a G5 and VMX units, ok maybe not. But I expect big things, because IBM has had lots of time to work on the problem. Time will tell.
Nice to hear some very positive G5 thoughts in here. I hope your right.
This will surely get a lot of attention at FOSE, April 5-7
Mar 1, 9:30 PM (ET)
By MATTHEW FORDAHL
SAN FRANCISCO (AP) - Promising improved performance without greatly increased power needs, Intel Corp. (INTC) unveiled details Tuesday of upcoming microprocessors that will put two or more computing engines on a single chip.
The world's largest chip maker plans to use the technology across its processor lines, from those powering mobile computers to the brains of high-end servers. In all, Intel has 15 projects under way developing dual-core or multi-core chips.
Intel plans to launch dual-core desktop chips in the second quarter, offering two varieties geared toward high-end and mainstream users, respectively. It's also planning dual-core and multicore chips for servers and notebooks for release later this year and in 2006.
The high-end desktop chip, dubbed the Intel Pentium Processor Extreme Edition, will run at 3.2 gigahertz - slower than the 3.8 GHz of today's top-of-the-line Pentium 4. Still, during one demonstration, it performed a task in half the time of its single-core counterpart.
Stephen Smith, vice president of Intel's Digital Enterprise Group, said performance improvements will vary depending on the job. Multicore chips offer the greatest improvement when the software is designed to distribute tasks over the multiple engines.
But the technology also should improve performance when multiple programs are running at the same time, he added. All modern PCs typically have several pieces of software working in the background, including antivirus tools, network utilities and others.
Also, the Extreme Edition's cores will use a technology that essentially nearly doubles the amount of work that can be handled by each core. Because of this, the operating system will work as though there are four cores, instead of the physical two.
The mainstream processor, dubbed the Pentium D, won't have that feature enabled. Smith also did not indicate that chip's clock speed.
The new processors' prices were not disclosed.
Intel isn't alone in bringing multicore chips to market. Rival Advanced Micro Devices also has plans to launch dual-core chips later this year.
And a trio of companies - International Business Machines Corp. (IBM), Toshiba Corp. and Sony Corp. (SNE) - are building a multicore chip based on a completely new architecture. It's expected to power Sony's next-generation PlayStation game console, among other devices.
The industry's move toward multicore processors comes as the number of transistors crammed on a single chip continues to increase in accordance with a famous prediction made by Intel co-founder Gordon Moore in 1965.
But while higher clock speeds are resulting in greater power demands, that is not translating into major gains in performance, threatening the historical growth in computing capabilities.
"It's the way the industry is going to be able to continue Moore's Law going forward by increasing the processing power in an exponential fashion over time," Intel CEO Craig Barrett told reporters at the company's forum for developers.
Originally posted by FallenFromTheTree
... "It's the way the industry is going to be able to continue Moore's Law going forward by increasing the processing power in an exponential fashion over time," Intel CEO Craig Barrett told reporters at the company's forum for developers.
That's funny. After they say that growth in transistors is not increasing performance, then this. I guess the exponent in the "exponential growth" is less than 1.
Originally posted by onlooker
I thought IBM already made dual core Power processors, and announced this was going into the 9xx PPC architecture way before AMD.
Yes, they make for quite some time now dual core Power processors, but where did they announce that this technology will make it down to the PPC9xx? I am not aware of any announcement like this.
I hope IBM, and Apple beat them all to the punch on this. Come on WWDC.
IBM has beaten them long ago. But I doubt the duette Apple/IBM is so close to a dual core PPC9xx-based Power Mac release. Even if this happens in WWDC, in practice we talk rather about a parallel (PPC vs. x86) introduction of dual core processors and no about some advantage of the PPC side. Sad I would say, if one takes into account the long experience of IBM in these matters.
WOW! You design computer processors. You must be really smart? Duuuhhh.. I guess.
Originally posted by onlooker
At early appearances I think AMD will still have a leg up on all of them, unless IBM starts using an on die memory controller which is what seems to give AMD all that power. You would think that being in a multi billion dollar company IBM processor designers would have figured this out already, and know exactly what to do. But you never know...
WOW! You design computer processors. You must be really smart? Duuuhhh.. I guess.
Actually the power5 and power4 processors have on-die memory controllers, its just the 970 family that doesn't. I think this has something to do with apple?
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
Originally posted by emig647
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
That, I did not know, nor do I know if it's true, but it's good to hear as long as IBM takes great advantage of it.
That is like music to my ears.
Originally posted by emig647
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
Sure, it's possible. Just run two busses off the chip to a dual-ported memory controller.
You'll never see that in practice, though, because there's no reason to prefer that arrangement to an integrated memory controller. Busses traced across the motherboard are slower, more prone to interference, and more costly than on-chip busses.
I expect dual-core PPCs to start popping out of the woodwork this year and early next year. This is going to be an industry-wide transition.
Originally posted by Amorph
You'll never see that in practice, though, because there's no reason to prefer that arrangement to an integrated memory controller. Busses traced across the motherboard are slower, more prone to interference, and more costly than on-chip busses.
I started thinking about that after I posted, anything is possible but who would be stupid enough to do it, the performance decrease would be too much... But like you said its more expensive and more prone to interference. Thanks AMorph.
It's my understanding that on ondie memory controller benefits you chiefly in applications where memory latency is more imporant than overall bandwidth. Thus an Opteron will "kill" a Xeon in applications where latency is the prime pain point rather than massive througput.
I think sometimes at the desktop level IBM/Intel are loathe to utilize the extra transistors needed. Plus you have to make sure you have supported the right memory types or you'll have to add and external controller. I realize that now DDR is standard but soon we'll have XDR from Rambus and FB-DIMM from Intel. The market is going to have a bit of a shakeup possibly.
Originally posted by hmurchison
Before people get all moist over Ondie memory controller let's temper that with a little info.
It's my understanding that on ondie memory controller benefits you chiefly in applications where memory latency is more imporant than overall bandwidth. Thus an Opteron will "kill" a Xeon in applications where latency is the prime pain point rather than massive througput.
I think sometimes at the desktop level IBM/Intel are loathe to utilize the extra transistors needed. Plus you have to make sure you have supported the right memory types or you'll have to add and external controller. I realize that now DDR is standard but soon we'll have XDR from Rambus and FB-DIMM from Intel. The market is going to have a bit of a shakeup possibly.
You said a lot, but are you just throwing that out there, or is there a point to it. I'm getting interested in this possible on die controller news, but I'm not sure what it was you were getting at. Were you getting at anything?
Originally posted by emig647
I think he means there are advantages and disadvantages to onchip memory controllers. Also that the technology can change from pros and cons to just pros?
Mainly my post is meant to temper excessive enthusiasm. Because on the intarweb you'll frequently see.
"OMFG!!!!!!!1111 Apple duzn't have teh Ondie mem controllerz..tehy suck!"
I think OMC will come (Freescale and 9XX chips) but I realize why IBM isn't putting them in the cpus yet. Sorry that my point wasn't that clear. I sincerely try to look at both sides of the coin but I have my bias like anyone.
What remains to be seen,
is who will cross it first and how.
Originally posted by emig647
Actually the power5 and power4 processors have on-die memory controllers, its just the 970 family that doesn't. I think this has something to do with apple?
Actually I think power has dedicated interfaces to off chip controllers. They aren't hooking directly to DDR memory with those guys.
Either way, someone correct me if I'm wrong but I don't believe dual core is possible without on-die memory controllers.
Sadly this is wrong. Modern processors have an independant bus interface. That bus interface unit can be designed to communicate with two or more processors. Actually the unit is often communicating with the Cache. Adding another processor is not a big deal. What you do end up with is the potential for a squeeze on the FSB, that is not enough band width to effectively support both processors.
AS to what IBM/Apple will actually offer up that will be very interesting indeed. First we have to wonder how far the FSB can go beyond 1.5GHz. My thinking is that they would be far better off with an onboard memory controller, but Apple would really have to model this with the work loads they expect. There may be advantage to having the DMA circuitry off chip as the inteaction with the video card may be an issue.
Frankly I suspect that inorder to be really successfull and accomplish what Apple would want to accomplish they would have to implement a PPC chip with both a memory controller and an interface to the video card. Today that Video interface would be PCI-Express.
Dave
Originally posted by hmurchison
Before people get all moist over Ondie memory controller let's temper that with a little info.
Isn't the on-die memory controller at least required for a portable G5 since the existing Powermac memory controller is a furnace?
Originally posted by wizard69
Actually I think power has dedicated interfaces to off chip controllers. They aren't hooking directly to DDR memory with those guys.
Power4 has an inline cache and memory architecture where the memory controllers are off-chip, inline with the off-chip L3 cache and on-chip L3 cache controllor. The main memory controller is in the off-chip L3 device. Main memory traffic had to go through all levels of cache to get to the processor.
Power5 has more of a backside cache and memory architecture where there is an on-chip backside L3 cache controller with off-chip L3 cache and an on-chip main memory controller. That is, main memory traffic didn't have to go through the L3 cache bus to get to L2 cache like in Power4. Main memory traffic can go directly to L2.
Sadly this is wrong. Modern processors have an independant bus interface. That bus interface unit can be designed to communicate with two or more processors. Actually the unit is often communicating with the Cache. Adding another processor is not a big deal. What you do end up with is the potential for a squeeze on the FSB, that is not enough band width to effectively support both processors.
Very true, and in fact, reality for Intel. Intel's first gen dual core chips will use one Pentium GTL+ (whatever it is called and is now) front side bus to the system ASIC. The Pentium bus is a shared processor bus much like the Moto G4 processors where multiple processors can reside on one bus. Intel is just putting two Prescotts on one processor bus on the same chip. Said processor bus goes to the northbride (system ASIC) for main memory.
Always fear Intel though. They will be moving to multiple processor buses (FSBs) in later generations. Centrino dual-core chips will likely have an on-die memory controller, so all their bases are covered.
AS to what IBM/Apple will actually offer up that will be very interesting indeed. First we have to wonder how far the FSB can go beyond 1.5GHz. My thinking is that they would be far better off with an onboard memory controller, but Apple would really have to model this with the work loads they expect. There may be advantage to having the DMA circuitry off chip as the inteaction with the video card may be an issue.
Simplest case should just be dual-core 970 with a large shared L2 cache (2 MB?) using the elastic processor bus. Provides minimal changes, like drop-in replacement, for Apple's architecture. I'm expecting Antares to be like this.
If it is dual-core with on-die memory controller, Apple will have to come up with a brand new Macintosh architecture with new core logic chipsets. That's a lot of work.
Frankly I suspect that inorder to be really successfull and accomplish what Apple would want to accomplish they would have to implement a PPC chip with both a memory controller and an interface to the video card. Today that Video interface would be PCI-Express.
Hey, I suggested that 6 years ago.