Does anyone know if IBM is going to be using hypertransport technology? I know they have partnered up[ with AMD for some kind of processor research stuff, or something, but the spread of speed between the PPC, and the x86 world is increasing by a lot now.
This has now become a major concern of mine.</strong><hr></blockquote>
Doesn't matter much what IBM will use.
The question is will Apple?
Remember how a several months ago, before we knew about the 970, everyone on here was talking about HT and RIO? We all could see that Apple was a member of the HT consortium, but not a member for RIO. Yet Motorola was in with the RIO crowd.
[quote]Originally posted by Transcendental Octothorpe:
<strong>
Remember how a several months ago, before we knew about the 970, everyone on here was talking about HT and RIO? We all could see that Apple was a member of the HT consortium, but not a member for RIO. Yet Motorola was in with the RIO crowd.
Remember how confused were all were by that?
Makes a whole load of sense now, don't it?
</strong><hr></blockquote>
Yeah but the IBM powerpc roadmap shows rapidio on it. Nothing about HT.
Thanks for bringing that up. I know roadmaps are just that, and leave specifics out, but it really appears that this roadmap doesn't refer to the 970.
The 970 and its' future iterations certainly fit Multcore Superscalar, SMP capapble, and Integrated SIMD engine, but Rapid I/O and n-way Crossbar Coreconnect don't. I believe IBM will be introducing a 32 bit cpu based on this roadmap, I just have absolutely no basis other than this roadmap and that it seems like a next logical step.
In cpu's capable of simultaneous multithreading (hyper-threading), if one thread has a branch misdirect, are both threads flushed?</strong>
No I wouldn't think so. I believe a "flush" just means that the fetch/dispatcher puts a hold on the instruction stream, instructions in the pipeline are pushed out of the pipeline, then the fetch/dispatch units start down the correct set of instructions.
In an SMT system, properly designed fetch, dispatch, branch prediction and completion units would handle threads on a per thread basis. Which means one thread keeps on going while the thread with a branch misprediction waits for the mispredicted instructions to clear the units, and starts over whence its done.
IBM has posted their CeBit Press page and there is a Rev 1 PPC 970 blade board with photo!
[quote] The new IBM PowerPC 970 is the heart of the PowerPC Blade. It is based on the 64-Bit Power 4 architecture which is also used in the processors of the IBM eServer pSeries. The 64-bit microprozessor
· Offers full symmetrical multi-processing
· Has a high reliability (with parity L1, ECC L2 and parity checked system bus)
· Is manufactured in the latest 0,13 micrometer Copper/SOI CMOS technology
· Runs at frequences ranging from 1.8 GHz - 2.5 Ghz
Therefore the IBMPowerPC 970 is the fastest PowerPC so far.
[quote]Originally posted by Transcendental Octothorpe:
<strong>....
rickag, gee, I don't see the POWER4 or POWER5 on that roadmap either. They must not be making those after all...</strong><hr></blockquote>That is the roadmap for the PowerPC. The POWER4 and POWER5 are not PowerPCs.
[quote]Originally posted by Transcendental Octothorpe:
<strong>It doesn't matter at all if IBM will use HT in any of their chips.
If Apple uses their own chipset to go with the 970, they can put HT in it, and all will be well.</strong><hr></blockquote>
The RapidIO and HyperTransport protocols/speeds are similar enough that the RIO folk are claiming it would require only a pretty trivial 'bridge' to connect them anyway. Seeing how some RapidIO parts are FPGAs (programable _hardware_) I'm with TO in that I don't see that it matters at all.
Mot & IBM both are on the RIO steering comittee btw.
I know I've seen the answer to this somewhere - and I've even claimed an answer somewhere, but when push comes to shove I can't find it, and nothing in IBM's MPF presentation indicates it:
How, exactly, does the 970 support SMP?
The description of the bus indicates that its protocol supports cooperation with another 970, but all signs point to a single bus on the processor, connected to a companion chip. I have been led to believe that two GigaBusses can be attached to the 970 - one to the companion, one to another 970 - but I can't find any indication of that, and I can't make sense of that in a NUMA architecture: The bus clocks so high, even accounting for clock-doubling, that I can't see how it would work as a CPU interconnect unless the two chips were right next to each other - but then you couldn't have plug-in daughtercards, each with its own CPU and RAM. Right? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
If, on the other hand, what IBM means is that the 970's bus supports communication with another processor through the companion chip, assuming that the companion chip bridges to some other interface that relays the right information to another 970's companion chip, then you have your modular NUMA architecture, at an obvious cost in overhead.
The careful wording by IBM "The PowerPC Blade offers outstanding performance and is superior to Intel Blades for certain applications in the High Perfomance Computing Sector." refering to their own current blades with Intel Xeon 2.0 or 2.4 suggest that good, really good things are coming this way <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
At least my take on this is that for FPU and AV stuff the 970 will be much better than the Xeon and I asume the integer performance will be at least comparable. It sounds like a pretty decent stepup from the G4s <img src="graemlins/cancer.gif" border="0" alt="[cancer]" />
If, on the other hand, what IBM means is that the 970's bus supports communication with another processor through the companion chip, assuming that the companion chip bridges to some other interface that relays the right information to another 970's companion chip, then you have your modular NUMA architecture, at an obvious cost in overhead.
There's several reliable quotes from Sandon (the IBM Chip research guy) claiming 'designed with SMP in mind', and 'up to 8x' lying around.</strong><hr></blockquote>
Oh, I don't doubt for a moment that the 970 is all about SMP. The MPF presentation said as much. I just want to know how.
Thank you for the response concerning misdirects and branch predictions in SMT. It does seem logical that engineers would design their systems so that misdirects in one thread not affect a second thread.
Comments
<strong>
Does anyone know if IBM is going to be using hypertransport technology? I know they have partnered up[ with AMD for some kind of processor research stuff, or something, but the spread of speed between the PPC, and the x86 world is increasing by a lot now.
This has now become a major concern of mine.</strong><hr></blockquote>
Doesn't matter much what IBM will use.
The question is will Apple?
Remember how a several months ago, before we knew about the 970, everyone on here was talking about HT and RIO? We all could see that Apple was a member of the HT consortium, but not a member for RIO. Yet Motorola was in with the RIO crowd.
Remember how confused were all were by that?
Makes a whole load of sense now, don't it?
In cpu's capable of simultaneous multithreading(hyper-threading), if one thread has a branch misdirect, are both threads flushed?
I read a couple of articles @ Arse and couldn't find the answer. I probably just missed it in the articles or I totally don't understand the concept.
<strong>
Remember how a several months ago, before we knew about the 970, everyone on here was talking about HT and RIO? We all could see that Apple was a member of the HT consortium, but not a member for RIO. Yet Motorola was in with the RIO crowd.
Remember how confused were all were by that?
Makes a whole load of sense now, don't it?
</strong><hr></blockquote>
Yeah but the IBM powerpc roadmap shows rapidio on it. Nothing about HT.
Thanks for bringing that up. I know roadmaps are just that, and leave specifics out, but it really appears that this roadmap doesn't refer to the 970.
The 970 and its' future iterations certainly fit Multcore Superscalar, SMP capapble, and Integrated SIMD engine, but Rapid I/O and n-way Crossbar Coreconnect don't. I believe IBM will be introducing a 32 bit cpu based on this roadmap, I just have absolutely no basis other than this roadmap and that it seems like a next logical step.
In cpu's capable of simultaneous multithreading (hyper-threading), if one thread has a branch misdirect, are both threads flushed?</strong>
No I wouldn't think so. I believe a "flush" just means that the fetch/dispatcher puts a hold on the instruction stream, instructions in the pipeline are pushed out of the pipeline, then the fetch/dispatch units start down the correct set of instructions.
In an SMT system, properly designed fetch, dispatch, branch prediction and completion units would handle threads on a per thread basis. Which means one thread keeps on going while the thread with a branch misprediction waits for the mispredicted instructions to clear the units, and starts over whence its done.
<strong>
Yeah but the IBM powerpc roadmap shows rapidio on it. Nothing about HT.
</strong><hr></blockquote>
Look,
It doesn't matter at all if IBM will use HT in any of their chips.
If Apple uses their own chipset to go with the 970, they can put HT in it, and all will be well.
rickag, gee, I don't see the POWER4 or POWER5 on that roadmap either. They must not be making those after all...
[quote] The new IBM PowerPC 970 is the heart of the PowerPC Blade. It is based on the 64-Bit Power 4 architecture which is also used in the processors of the IBM eServer pSeries. The 64-bit microprozessor
· Offers full symmetrical multi-processing
· Has a high reliability (with parity L1, ECC L2 and parity checked system bus)
· Is manufactured in the latest 0,13 micrometer Copper/SOI CMOS technology
· Runs at frequences ranging from 1.8 GHz - 2.5 Ghz
Therefore the IBMPowerPC 970 is the fastest PowerPC so far.
Further technical highlights of the PowerPC 970:
· Onchip 512 KB L2 Cache
· Altivec ? Vector/SIMD unit
· 6,4 GB/s I/O system bus throughput
<hr></blockquote>
There is also a photo but it is pretty big.
<a href="http://www-5.ibm.com/de/pressroom/cebit2003/i/highres/bladeprototype_300_Dpi.jpg"; target="_blank">PPC 970 blade board pic</a>
<a href="http://www-5.ibm.com/de/pressroom/cebit2003/en/highlights/powerpcblade.html"; target="_blank">Press page</a> :cool: :cool:
[ 02-26-2003: Message edited by: boy named sue ]Links
[ 02-26-2003: Message edited by: boy named sue ]Spelling
[ 02-27-2003: Message edited by: boy named sue ]</p>
<strong>....
rickag, gee, I don't see the POWER4 or POWER5 on that roadmap either. They must not be making those after all...</strong><hr></blockquote>That is the roadmap for the PowerPC. The POWER4 and POWER5 are not PowerPCs.
<strong>It doesn't matter at all if IBM will use HT in any of their chips.
If Apple uses their own chipset to go with the 970, they can put HT in it, and all will be well.</strong><hr></blockquote>
The RapidIO and HyperTransport protocols/speeds are similar enough that the RIO folk are claiming it would require only a pretty trivial 'bridge' to connect them anyway. Seeing how some RapidIO parts are FPGAs (programable _hardware_) I'm with TO in that I don't see that it matters at all.
Mot & IBM both are on the RIO steering comittee btw.
How, exactly, does the 970 support SMP?
The description of the bus indicates that its protocol supports cooperation with another 970, but all signs point to a single bus on the processor, connected to a companion chip. I have been led to believe that two GigaBusses can be attached to the 970 - one to the companion, one to another 970 - but I can't find any indication of that, and I can't make sense of that in a NUMA architecture: The bus clocks so high, even accounting for clock-doubling, that I can't see how it would work as a CPU interconnect unless the two chips were right next to each other - but then you couldn't have plug-in daughtercards, each with its own CPU and RAM. Right? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
If, on the other hand, what IBM means is that the 970's bus supports communication with another processor through the companion chip, assuming that the companion chip bridges to some other interface that relays the right information to another 970's companion chip, then you have your modular NUMA architecture, at an obvious cost in overhead.
Or is this poor software guy missing something?
<strong>
How, exactly, does the 970 support SMP?
...
Or is this poor software guy missing something?
IBM wants to use it in Blades. (<a href="http://www-5.ibm.com/de/pressroom/cebit2003/en/highlights/powerpcblade.html"; target="_blank">Proof</a>)
There's several reliable quotes from Sandon (the IBM Chip research guy) claiming 'designed with SMP in mind', and 'up to 8x' lying around.
There's one or two "quotes" that claim up to 32x. Those aren't as likely.
If they're designed for blades, there'd be a lot of interest in minimizing how much 'infrastructure' the chip needs to run.
Oh, and note the range in the 'proof' link. 'PPC 970, 1.8-2.5GHz'.
Woot
At least my take on this is that for FPU and AV stuff the 970 will be much better than the Xeon and I asume the integer performance will be at least comparable. It sounds like a pretty decent stepup from the G4s <img src="graemlins/cancer.gif" border="0" alt="[cancer]" />
<strong>
If, on the other hand, what IBM means is that the 970's bus supports communication with another processor through the companion chip, assuming that the companion chip bridges to some other interface that relays the right information to another 970's companion chip, then you have your modular NUMA architecture, at an obvious cost in overhead.
</strong><hr></blockquote>
I can't point you to a link or anything, but
<strong>
There's several reliable quotes from Sandon (the IBM Chip research guy) claiming 'designed with SMP in mind', and 'up to 8x' lying around.</strong><hr></blockquote>
Oh, I don't doubt for a moment that the 970 is all about SMP. The MPF presentation said as much. I just want to know how.
Apparently, it's
Thank you for the response concerning misdirects and branch predictions in SMT. It does seem logical that engineers would design their systems so that misdirects in one thread not affect a second thread.
<strong>That is the roadmap for the PowerPC. The POWER4 and POWER5 are not PowerPCs.</strong><hr></blockquote>
Thank you Mr. Me.
Transcendental Octothorpe
I did actually go to IBM's website and read the roadmap and look at the "Documentation by Family", before I posted.
And I still say,"I just have absolutely no basis other than this roadmap and that it seems like a next logical step."
[ 02-27-2003: Message edited by: rickag ]</p>
<strong>
I can't point you to a link or anything, but
Three words.
Apple Processor Interface
So I'm guessing Apple has their own companion chip (or analogous interface) ready and waiting.
Whee.