I wish I could give you more details, but without knowing the name, I can't look it up (my attempts at finding it have failed so far), and I don't have sufficient personal experience.
I have less than that.
I won't be getting mine until after MacWorld, but if I remember then, I'll post the results.
I wish I could give you more details, but without knowing the name, I can't look it up (my attempts at finding it have failed so far), and I don't have sufficient personal experience.
I think it might be Physical Address Extension. It bumps the limit to 36 bits addressing, or 64GB.
No it doesn't. This is an architectural limitation, the chipset has nothing to do with it.
I stand by what I said. The 3 GB limitation of the current MBP is due to the chipset (Napa), not the processor or the OS. Merom is a 64 bit processor, Tiger is a 64 bit operating system (where it counts, just not all the way up to the GUI like Leopard will be/is).
When the MacBook Pro comes with Santa Rosa instead of Napa, I expect the 3 GB (ish) ceiling to disappear.
The Mac Pro doesn't need to use that. Woodcrests are IA-64 (or whatever the 64 bit x86 architecture is called), not IA-32.
Woodcrests are not IA-64 (that's Itanium), and while they do have x86-64, there is currently no version of Mac OS X that allows 64-bit mode on Intel. Leopard will. Tiger does not.
I stand by what I said. The 3 GB limitation of the current MBP is due to the chipset (Napa),
Napa is not the chipset. Napa is a platform, Centrino Duo, and no current or past Apple product uses this platform.
Napa's chipset, the 945 series, is also not the reason for this limitation.
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not the processor or the OS. Merom is a 64 bit processor, Tiger is a 64 bit operating system (where it counts, just not all the way up to the GUI like Leopard will be/is).
Tiger's XNU does not have the ability to recognize, let alone execute, Intel 64 / x86_64 / EM64T / AMD64 / x64 Mach-O binary segments.
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When the MacBook Pro comes with Santa Rosa instead of Napa, I expect the 3 GB (ish) ceiling to disappear.
The platform doesn't have anything to do with this.
I'm sorry I'm not being precise enough in my wording, and maybe I'm wrong about Tiger (I didn't realise that it didn't do any x86-64, I'd assumed its 64-bit status on Intel was the same as that on PPC).
When I talk about Napa/Santa Rosa, I assume that you know what I mean. I'm well aware that Napa/Santa Rosa are the codenames for the whole Centrino platform, not the actual northbridge/southbridge chipsets, but it is much more convenient to use the Napa and Santa Rosa codenames because the chipset codenames are not well known.
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Originally Posted by Chucker
The platform doesn't have anything to do with this.
This is incorrect! It would seem that there is an OS and chipset issue. The OS can't address more than 4 GB, and Intel themselves have confirmed that the chipset can't address more than 3.2 GB (or whatever it was) of RAM. Hopefully we can agree it's got nothing to do with the Core 2 Duo (Merom), what with the way that that's an x86-64 chip and therefore capable of performing the necessary memory addressing calculations.
I'm sorry I'm not being precise enough in my wording, and maybe I'm wrong about Tiger (I didn't realise that it didn't do any x86-64, I'd assumed its 64-bit status on Intel was the same as that on PPC).
Wow, I'll have to retract my statement.
Apple must have quietly added x86-64 support in a later build of 10.4.7, because mine of 10.4.8 does have a x86-64 version of libSystem.
That's odd, though, because I've never heard anyone reporting that.
Yeah, Tiger only supports ppc32, ppc64 and x86-32 (IA32).
This would explain why the 10.4.8 update included a rather sizable upgrade of the BSD subsystem, although I have yet to find any binary that actually takes advantage of this, and in addition, there is no way in Xcode 2.x (3.0 doesn't run on Tiger because it uses Objective-C 2.0) to actually compile for 64-bit. (I have not checked whether the 10.4.8-shipped gcc itself allows such compilations, which could then manually be merged using lipo.)
Certainly, though, lipo has been updated to recognize this new binary segment type, because I'm positive I checked this just a while ago (10.4.6? 10.4.7?), and it didn't work.
Sorry for my above mistake.
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When I talk about Napa/Santa Rosa, I assume that you know what I mean. I'm well aware that Napa/Santa Rosa are the codenames for the whole Centrino platform, not the actual northbridge/southbridge chipsets, but it is much more convenient to use the Napa and Santa Rosa codenames because the chipset codenames are not well known.
Yes, I know what you mean and I often use those names myself for simplicity. That said, I still haven't seen any evidence that the chipset would impose such a limit. A 4 GB limit, perhaps (effectively causing the 3.x GB limit). Or, more likely, lack of PAE. Since most of OS X runs in 32-bit mode regardless (and this won't change until Leopard), PAE would still be needed, as I understand it, for the bulk of apps.
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This is incorrect! It would seem that there is an OS and chipset issue. The OS can't address more than 4 GB, and Intel themselves have confirmed that the chipset can't address more than 3.2 GB (or whatever it was) of RAM.
But have Intel confirmed the reason for that limitation? Is it truly with the chipset, or inherent in architectural problems?
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Hopefully we can agree it's got nothing to do with the Core 2 Duo (Merom),
Absolutely.
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what with the way that that's an x86-64 chip and therefore capable of performing the necessary memory addressing calculations.
Is it truly with the chipset, or inherent in architectural problems?
Right. We might be about to get to the bottom of this.
When you say "architectural problems", you are referring to IA-32? And that if the problem is architectural, it doesn't matter which IA-32-supporting chipset you are using, they'll all have a 3 GB ish RAM limitation because of having to map other memory areas into the RAM's address space? (Unless the chipset and OS both support PAE).
My point was that since the chipset that will come with Santa Rosa is designed for x86-64 (unlike Napa's chipset which was designed for 32 bit), its address space will be (much) bigger than 4 GB, so the 3 (ish) GB RAM limitation should go away. Presumably, as things stand with Tiger, if a Santa Rosa MBP ships with Tiger (which I doubt, I'm expecting Leopard and Santa Rosa at the same time, or if anything, Leopard first), RAM would be limited to 4 GB?
When you say "architectural problems", you are referring to IA-32? And that if the problem is architectural, it doesn't matter which IA-32-supporting chipset you are using, they'll all have a 3 GB ish RAM limitation because of having to map other memory areas into the RAM's address space? (Unless the chipset and OS both support PAE).
Yessir.
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My point was that since the chipset that will come with Santa Rosa is designed for x86-64 (unlike Napa's chipset which was designed for 32 bit), its address space will be (much) bigger than 4 GB, so the 3 (ish) GB RAM limitation should go away.
Yes, I understand that. I just don't see (beyond something as vague as "the chipset wasn't designed for it") what, in particular, causes this restriction. If it was a deliberate engineering or marketing decision, that's another matter.
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Presumably, as things stand with Tiger, if a Santa Rosa MBP ships with Tiger (which I doubt, I'm expecting Leopard and Santa Rosa at the same time, or if anything, Leopard first), RAM would be limited to 4 GB?
Such is my assumption, but I'm neither a low-end developer nor a hardware engineer.
When you say "architectural problems", you are referring to IA-32? And that if the problem is architectural, it doesn't matter which IA-32-supporting chipset you are using, they'll all have a 3 GB ish RAM limitation because of having to map other memory areas into the RAM's address space? (Unless the chipset and OS both support PAE).
Yes, it's architectural, it affects all IA-32 (x86) chipsets and it's 3 GB-ish, which means you can get 3.2 GB or you can get 3.7 GB. PAE is another thing, it is so rarely used now that it's almost not worth mentioning.
Quote:
My point was that since the chipset that will come with Santa Rosa is designed for x86-64 (unlike Napa's chipset which was designed for 32 bit), its address space will be (much) bigger than 4 GB, so the 3 (ish) GB RAM limitation should go away. Presumably, as things stand with Tiger, if a Santa Rosa MBP ships with Tiger (which I doubt, I'm expecting Leopard and Santa Rosa at the same time, or if anything, Leopard first), RAM would be limited to 4 GB?
The address space is the function of the mode the processor runs in. For a Core 2 Duo / Merom machine (not Core Duo / Yonah) running in 64-bit mode (that is, a 64-bit operating system like Linux x86-64 and presumably Leopard) the current chipset should already be able to provide full 4 GB for the operating system to use.
On the other hand, Santa Rosa will change nothing for a 32-bit OS like Tiger, because the architectural limitations will stay.
Yes, I understand that. I just don't see (beyond something as vague as "the chipset wasn't designed for it") what, in particular, causes this restriction. If it was a deliberate engineering or marketing decision, that's another matter.
Intel specs state clearly that most variations of i945 chipset (including the ones that are used in CD and C2D Macs) support full 4 GB. With a 32-bit address space not all of it will be available to the OS, but with a 64-bit OS you can use full 4 GB.
Intel specs state clearly that most variations of i945 chipset (including the ones that are used in CD and C2D Macs) support full 4 GB. With a 32-bit address space not all of it will be available to the OS, but with a 64-bit OS you can use full 4 GB.
This doesn't answer the questions about the Mac Pro. Any ideas on that?
Comments
I wish I could give you more details, but without knowing the name, I can't look it up (my attempts at finding it have failed so far), and I don't have sufficient personal experience.
I have less than that.
I won't be getting mine until after MacWorld, but if I remember then, I'll post the results.
I wish I could give you more details, but without knowing the name, I can't look it up (my attempts at finding it have failed so far), and I don't have sufficient personal experience.
I think it might be Physical Address Extension. It bumps the limit to 36 bits addressing, or 64GB.
http://www.microsoft.com/whdc/system...e/default.mspx
I think it might be Physical Address Extension.
That's the one.
No it doesn't. This is an architectural limitation, the chipset has nothing to do with it.
I stand by what I said. The 3 GB limitation of the current MBP is due to the chipset (Napa), not the processor or the OS. Merom is a 64 bit processor, Tiger is a 64 bit operating system (where it counts, just not all the way up to the GUI like Leopard will be/is).
When the MacBook Pro comes with Santa Rosa instead of Napa, I expect the 3 GB (ish) ceiling to disappear.
I think it might be Physical Address Extension. It bumps the limit to 36 bits addressing, or 64GB.
http://www.microsoft.com/whdc/system...e/default.mspx
Woodcrests are not IA-64 (that's Itanium), and while they do have x86-64, there is currently no version of Mac OS X that allows 64-bit mode on Intel. Leopard will. Tiger does not.
I stand by what I said. The 3 GB limitation of the current MBP is due to the chipset (Napa),
Napa is not the chipset. Napa is a platform, Centrino Duo, and no current or past Apple product uses this platform.
Napa's chipset, the 945 series, is also not the reason for this limitation.
not the processor or the OS. Merom is a 64 bit processor, Tiger is a 64 bit operating system (where it counts, just not all the way up to the GUI like Leopard will be/is).
Tiger's XNU does not have the ability to recognize, let alone execute, Intel 64 / x86_64 / EM64T / AMD64 / x64 Mach-O binary segments.
When the MacBook Pro comes with Santa Rosa instead of Napa, I expect the 3 GB (ish) ceiling to disappear.
The platform doesn't have anything to do with this.
When I talk about Napa/Santa Rosa, I assume that you know what I mean. I'm well aware that Napa/Santa Rosa are the codenames for the whole Centrino platform, not the actual northbridge/southbridge chipsets, but it is much more convenient to use the Napa and Santa Rosa codenames because the chipset codenames are not well known.
The platform doesn't have anything to do with this.
This is incorrect! It would seem that there is an OS and chipset issue. The OS can't address more than 4 GB, and Intel themselves have confirmed that the chipset can't address more than 3.2 GB (or whatever it was) of RAM. Hopefully we can agree it's got nothing to do with the Core 2 Duo (Merom), what with the way that that's an x86-64 chip and therefore capable of performing the necessary memory addressing calculations.
I'm sorry I'm not being precise enough in my wording, and maybe I'm wrong about Tiger (I didn't realise that it didn't do any x86-64, I'd assumed its 64-bit status on Intel was the same as that on PPC).
Wow, I'll have to retract my statement.
Apple must have quietly added x86-64 support in a later build of 10.4.7, because mine of 10.4.8 does have a x86-64 version of libSystem.
That's odd, though, because I've never heard anyone reporting that.
Yeah, Tiger only supports ppc32, ppc64 and x86-32 (IA32).
This would explain why the 10.4.8 update included a rather sizable upgrade of the BSD subsystem, although I have yet to find any binary that actually takes advantage of this, and in addition, there is no way in Xcode 2.x (3.0 doesn't run on Tiger because it uses Objective-C 2.0) to actually compile for 64-bit. (I have not checked whether the 10.4.8-shipped gcc itself allows such compilations, which could then manually be merged using lipo.)
Certainly, though, lipo has been updated to recognize this new binary segment type, because I'm positive I checked this just a while ago (10.4.6? 10.4.7?), and it didn't work.
Sorry for my above mistake.
When I talk about Napa/Santa Rosa, I assume that you know what I mean. I'm well aware that Napa/Santa Rosa are the codenames for the whole Centrino platform, not the actual northbridge/southbridge chipsets, but it is much more convenient to use the Napa and Santa Rosa codenames because the chipset codenames are not well known.
Yes, I know what you mean and I often use those names myself for simplicity. That said, I still haven't seen any evidence that the chipset would impose such a limit. A 4 GB limit, perhaps (effectively causing the 3.x GB limit). Or, more likely, lack of PAE. Since most of OS X runs in 32-bit mode regardless (and this won't change until Leopard), PAE would still be needed, as I understand it, for the bulk of apps.
This is incorrect! It would seem that there is an OS and chipset issue. The OS can't address more than 4 GB, and Intel themselves have confirmed that the chipset can't address more than 3.2 GB (or whatever it was) of RAM.
But have Intel confirmed the reason for that limitation? Is it truly with the chipset, or inherent in architectural problems?
Hopefully we can agree it's got nothing to do with the Core 2 Duo (Merom),
Absolutely.
what with the way that that's an x86-64 chip and therefore capable of performing the necessary memory addressing calculations.
Yes.
Is it truly with the chipset, or inherent in architectural problems?
Right. We might be about to get to the bottom of this.
When you say "architectural problems", you are referring to IA-32? And that if the problem is architectural, it doesn't matter which IA-32-supporting chipset you are using, they'll all have a 3 GB ish RAM limitation because of having to map other memory areas into the RAM's address space? (Unless the chipset and OS both support PAE).
My point was that since the chipset that will come with Santa Rosa is designed for x86-64 (unlike Napa's chipset which was designed for 32 bit), its address space will be (much) bigger than 4 GB, so the 3 (ish) GB RAM limitation should go away. Presumably, as things stand with Tiger, if a Santa Rosa MBP ships with Tiger (which I doubt, I'm expecting Leopard and Santa Rosa at the same time, or if anything, Leopard first), RAM would be limited to 4 GB?
When you say "architectural problems", you are referring to IA-32? And that if the problem is architectural, it doesn't matter which IA-32-supporting chipset you are using, they'll all have a 3 GB ish RAM limitation because of having to map other memory areas into the RAM's address space? (Unless the chipset and OS both support PAE).
Yessir.
My point was that since the chipset that will come with Santa Rosa is designed for x86-64 (unlike Napa's chipset which was designed for 32 bit), its address space will be (much) bigger than 4 GB, so the 3 (ish) GB RAM limitation should go away.
Yes, I understand that. I just don't see (beyond something as vague as "the chipset wasn't designed for it") what, in particular, causes this restriction. If it was a deliberate engineering or marketing decision, that's another matter.
Presumably, as things stand with Tiger, if a Santa Rosa MBP ships with Tiger (which I doubt, I'm expecting Leopard and Santa Rosa at the same time, or if anything, Leopard first), RAM would be limited to 4 GB?
Such is my assumption, but I'm neither a low-end developer nor a hardware engineer.
When you say "architectural problems", you are referring to IA-32? And that if the problem is architectural, it doesn't matter which IA-32-supporting chipset you are using, they'll all have a 3 GB ish RAM limitation because of having to map other memory areas into the RAM's address space? (Unless the chipset and OS both support PAE).
Yes, it's architectural, it affects all IA-32 (x86) chipsets and it's 3 GB-ish, which means you can get 3.2 GB or you can get 3.7 GB. PAE is another thing, it is so rarely used now that it's almost not worth mentioning.
My point was that since the chipset that will come with Santa Rosa is designed for x86-64 (unlike Napa's chipset which was designed for 32 bit), its address space will be (much) bigger than 4 GB, so the 3 (ish) GB RAM limitation should go away. Presumably, as things stand with Tiger, if a Santa Rosa MBP ships with Tiger (which I doubt, I'm expecting Leopard and Santa Rosa at the same time, or if anything, Leopard first), RAM would be limited to 4 GB?
The address space is the function of the mode the processor runs in. For a Core 2 Duo / Merom machine (not Core Duo / Yonah) running in 64-bit mode (that is, a 64-bit operating system like Linux x86-64 and presumably Leopard) the current chipset should already be able to provide full 4 GB for the operating system to use.
On the other hand, Santa Rosa will change nothing for a 32-bit OS like Tiger, because the architectural limitations will stay.
Yes, I understand that. I just don't see (beyond something as vague as "the chipset wasn't designed for it") what, in particular, causes this restriction. If it was a deliberate engineering or marketing decision, that's another matter.
Intel specs state clearly that most variations of i945 chipset (including the ones that are used in CD and C2D Macs) support full 4 GB. With a 32-bit address space not all of it will be available to the OS, but with a 64-bit OS you can use full 4 GB.
Intel specs state clearly that most variations of i945 chipset (including the ones that are used in CD and C2D Macs) support full 4 GB. With a 32-bit address space not all of it will be available to the OS, but with a 64-bit OS you can use full 4 GB.
This doesn't answer the questions about the Mac Pro. Any ideas on that?
This doesn't answer the questions about the Mac Pro. Any ideas on that?
The Mac Pro uses PAE. The ceiling is merely bumped from 4 GBs to 64 GBs, i.e. 36-bit.
But since some of OS X is already 64-bit, some processes actually have a 64-bit space, so the ceiling matters even less there.
Of course, you can only install 16 GBs or whatever anyway.
The Mac Pro uses PAE. The ceiling is merely bumped from 4 GBs to 64 GBs, i.e. 36-bit.
But since some of OS X is already 64-bit, some processes actually have a 64-bit space, so the ceiling matters even less there.
Of course, you can only install 16 GBs or whatever anyway.
That's good. I figured it was something like that.