Yesterday I had access to a document discribing the Motorola MPC7400 processor. The document was not from Motorola, but the persons that wrote it seemed to have had deep insight on Motorola semiconductor technology. Although the document was dated January 2000 it looked very interesting.
The first chapter descibed the MPC7400 and included many technical information, this was definately the less interesting part of the document. The second chapter then described some of the problems of the architecture. Apparently the original design was supposed to reach 1 ghz at some point, but the Motorola had serious problems with pipeline related circuits that produced too much heat. If you believe the document Motorola already knew in mid 1999 that the MPC7400 could never exceed 700 mhz (that's the clockspeed mentioned in the document). The document also notices that only very few processors on the wafers were capable to run at speeds higher than 500 mhz, maybe that's the reason why Apple was stuck at 500 mhz for such a long time.
The second chapter then described MPC7400 successor plans with a 7 stage pipelines, 256 kb L2 on-die cache and a 2 mb external L3 cache (that's more or less what we have now with the MPC745x). There was very detailed information about the MPC745x, and that made me wonder a bit because the document was so old (January 2000, as stated above). I know there is no proof for it, but considering the detailed information about current G4 processors I found in this document makes me think that the people who wrote this had some real insight in Motorolas technology.
And now to the most interesting part, the notes about the G4 successor - the G5. Unfortunately I must tell you that there was no entire chapter with many details about the MPC7500, it was only attached as appendix (one page). Here's more or less what I found there:
The G5 was planned for 2002. The basic design was a 64 bit processor featuring a new on-chip bus system and 512 kb on-die L2 cache. The design was intended to be modular, and a version with 32 bit execution units and 256 kb L2 cache was planned too. This already means that there were plans for two G5 processors, a 64 bit version for high-end workstations and servers and a 32 bit version for consumer and portable machines. There was no mention of an external L3 cache or AltiVec, although it said that the G5 would be based on the G4 which makes me think that at least AltiVec should be part of the design. Apparently the G5's block diagram should be very similar to the G4's, and there was no mention of enhanced execution units (except for the fact they should be 64 bits). Unfortunately the comments about the intended G5 design were very vague, but apparently the G5 was planned to use two G4-like cores with a new pipeline.
There was also a paragraph about the planned production process, this one was very clear indeed: 0.10 with speeds starting at 2 ghz in 2002.
Now that's all about what the document said, the following is only speculation...
If I remember well the Motorola roadmap said 2+ ghz some time ago, and now they have changed it to 800 mhz - 2 ghz. This could be related to the fact that we're still far from 0.10, if the G5 should be close now a 0.13 process should be much more likely. 800-2000 mhz would not be that improbable then. I don't think a G5 will be made using the current 0.18 process, but I would not be surprised if we would get 0.13 G4's within the next few months. The current SOI MPC7455 should reach 1.2 ghz, but I don't know why they're not shipping yet, maybe they're not available in high quantities, or maybe Motorola still has some trouble with SOI. An SOI MPC7455 using a 0.13 process should be capable to reach clock speeds of about 1.5 ghz, and I think this could be possible in mid 2002.
Maybe the G5 is ready, and maybe it will be shipping as soon as Motorola gets the 0.13 process ready for quantity production. I really think they had enough time to realize the G5, as the technology was already there (Motorola and (especially) IBM have already realized 64 bit PPC designs). A G5 featuring a 10 stage pipeline using a 0.13 process should reach clock speeds of 1.5 - 2.0 ghz (32 bit version, the 64 bit version should produce more heat).
So that's all I know for now, I will now try to find some detailed information about the G5 - I already tried this, but it's really hard to get any info which makes me think that Apple has something to do with it...
That reminds me that a lot of the things that've been offered as possible features for the G5 (multicoring, for example) were also rumored for the G4, before Motorola settled on the modest "Max" design. So it's not at all unlikely that Mot knew well in advance what features it wanted to add in to the G4 and its heirs: the features they punted from the initial model.
Doesn't Motorola's contract with Apple end by MWNY? If so, has Apple made any moves to renew this contract? If not I think the G5 will turn ot to be a lot better than the one planned by moto. Most rumours lately point to IBM producing the G5, with a dedicated processor for altivec.
Let's face it, all that really counts is multi-processing. All CPUs are going to have a speed limit eventually, whether it be 5Ghz or 20Ghz. Starship Enterprise ain't gonna be run on a 10Ghz Intel P10. Apple needs multiprocessing and bandwidth, which is probably where they are headed. G4 is fine with me if they can get the bandwidth and inter-processor communication worked out. They can even call it a G10 for all I care. All the information out there suggests that is where they are going.
[quote]Maybe the G5 is ready, and maybe it will be shipping as soon as Motorola gets the 0.13 process ready for quantity production.<hr></blockquote>
This is interesting considering it has been said elsewhere Apple is moving to IBM as its sole supplier... Moto got the design done but can't fab it, IBM's got the big fabs ready for it...
"This is interesting considering it has been said elsewhere Apple is moving to IBM as its sole supplier... Moto got the design done but can't fab it, IBM's got the big fabs ready for it..."
Which fits in well with a rumoured quote by Steve Jobs:
"It'll be great in two years time when we don't have to F***ing use you anymore." (In ref; to Moto'...)
I think it's fair to say that Moto' is a company in crisis and they are struggling. They're bleeding losses.
The logic of the aboves quote(s) is not lost on me...
I found the following on maccentral (april 2001). Maybe this could mean that the 'Apollo7' would be ready soon, using 0.13 SOI and - eventually - a 512 kb on-die L2 cache. Adding an improved memory interface (DDR) would make such a chip a big step forward.
Motorola announces 0.13-micron fabrication process
by David Read,
April 10, 2001, 7:00 am ET
Yesterday, Motorola announced its new HiPerMOS7 (Seventh Generation High Performance Metal Oxide Semiconductor -- called HiP7) manufacturing process that will allow future processors from Motorola, including the next PowerPCs, to run faster, use less power, generate less heat and be less expensive than ever before. This new fabrication process will be the first to use 0.13-micron lithography and SOI (Silicon on Insulator) technology along with copper interconnects.
"With HiPerMOS7, Motorola has tried to implement parallel design efforts with all of Motorola's future microprocessors," said Suresh Venkatesan, Motorola's HiP7 Process Technology Manager. "Initial products using SOI and HiP7 will address the embedded and infrastructure markets, with Motorola's PowerPC microprocessors adopting these technologies early next year." Motorola hopes that the smaller size of a processor manufactured with the new process will allow its embedded processors to drop significantly in price and increase in functionality. Venkatesan stresses that HiP7 will migrate to the PowerPC portfolio.
Currently, Motorola uses a 0.18-micron lithography process to manufacture Motorola 7450s, the G4s currently used in Apple's highest end systems. By moving to a far smaller 0.13-micron lithography process, Motorola's new processors will be able to use less energy per transistor, and have more transistors per processor. "Speed and dynamic power consumption are a function of voltage and frequency," said Venkatesan. "All things remaining equal, a processor manufactured using the 0.13-micron fabrication process could see a 50 percent power savings over a similar processor made using a 0.18-micron fabrication process."
That's not all. Because of the lowered power consumption of processors manufactured with the new process, it will be possible for Motorola to ramp up its processor's frequencies. This, coupled with Motorola's SOI technology which allows individual transistors to operate more quickly and efficiently, should allow Motorola to reach the goals that it outlined at last summer's Microprocessor Forum for its GHz+ G4 Apollo.
Mike Mendacino, Motorola's SOI Technology Manager, said that future PowerPC processors created using the 0.13-micron manufacturing process could have larger on-die L2 caches. "With more transistors on a given area, one could logically conclude that we could add more cache if the processor's performance and price worked out in a larger cache's favor," said Mendacino. He also suggested that, given Motorola's history, a larger on-die cache is a logical progression in the PowerPC's development.
Venkatesan also said that Motorola is skipping the 0.15-micron manufacturing process. This may result in Motorola leapfrogging their semiconductor competitors, many of whom have recently begun shipping processor products using a 0.15-micron lithography process -- Nvidia's GeForce3 being a high-profile example. Nevertheless, other major semiconductor manufacturers have announced their own twist of a 0.13-micron manufacturing process. For example, rival processor manufacturer Intel last week announced that it had successfully manufactured its first .13-micron processors on a larger wafer.
Motorola is currently sampling embedded processors fabricated using the 0.13-micron process, which it intends to begin shipping in volume in the second quarter of this year. Motorola also will be showing off its new technology at the Embedded systems conference this week in San Francisco
I think this is Apples year. We've had the LCD iMacs, roll on MWNY, i don't think the G5 will be ready for it but I think the machines will continue to ramp up their speed .
The best information that was provided on future road map was released on MacCentral back in April last year when Motorola released 0.13 micron process. The G4 based 7470 and 7460 seems very logical as Motorola may even ship them in the 2Q02. There were many predictions that next gen of SOI .13 Apollo will borrow features from the much rumored G5. Larger L2 cache and higher clock frequency will be the key changes, and very likely the addition of DDR support to increase bandwidth. The G5, on the other hand will only differ by a faster system bus and longer pipelines. It becomes harder to make sense out of all the G5 rumors. It seems like G5 is just another P4.
<strong>The best information that was provided on future road map was released on MacCentral back in April last year when Motorola released 0.13 micron process. The G4 based 7470 and 7460 seems very logical as Motorola may even ship them in the 2Q02. There were many predictions that next gen of SOI .13 Apollo will borrow features from the much rumored G5. Larger L2 cache and higher clock frequency will be the key changes, and very likely the addition of DDR support to increase bandwidth. The G5, on the other hand will only differ by a faster system bus and longer pipelines. It becomes harder to make sense out of all the G5 rumors. It seems like G5 is just another P4.</strong><hr></blockquote>
Using the 0.13 process with the G4/Apollo should allow to implement a larger L2 cache (512kb) and run higher clock rates (up to 1.5 ghz). DDR would be nice too. I hope to see this for MWNY.
The difference between the G4 and the G5 will be the fact the the G5 will match the Book E specifications while the G4 will not.
First, Moto would be the sole suplier, if they still hold the rights (which remember Apple can buy at the end of the deal) If Apple does get the rights, I say that they don't use Moto, if they don't get the rights Moto is their only choice.
imo, I think that OSX server should run 64-bit saving the 64-bit stations for servers and workstation-like uses.
Using the 0.13 process with the G4/Apollo should allow to implement a larger L2 cache (512kb) and run higher clock rates (up to 1.5 ghz). DDR would be nice too. I hope to see this for MWNY.The difference between the G4 and the G5 will be the fact the the G5 will match the Book E specifications while the G4 will not.
-------------------------------------------------
So the difference is mainly larger cache and faster bus, and may be a few more pipelines. As with the Book E compliant which calls for compatibility between IBM PPC and Motorola PPC should mean very little for Apple. Perhaps Apple should just call .13 Apollo a G5. It makes more sense.
<strong>One of the machines is built in a G4 case with a smaller motherboard.</strong><hr></blockquote>
Noooooo :eek: ! I want all six slots back(I'd really like it if Apple were to surprise us with a native RapidIO graphics chipset . and dump that nasty AGP slot). along with 4 CPUs and at least six drive bays. Hopefully this is just one machine.
[quote]Originally posted by Dorsal M:
<strong>there already is a crimp on upgraders. I have yet to see a non-Apple 500MHz+ upgrade for any Apple machine. Although this may be because of minimum quantity bought is too high now.</strong><hr></blockquote>
Yeah. and this is really bad for the Mac too. as it greatly limits the lifetime value of a given system. if this is the result of Apple's greed. they should stop being so mean. and if this is the result of Motorola not making enough G4s. they should hire more of those korean/taiwanese fabs and increase volume to meet demand(Heck. they should do this anyways. Apple needs to increase channel saturation a LOT).
[quote]Originally posted by Dorsal M:
<strong>main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.</strong><hr></blockquote>
Right on.
[quote]Originally posted by Dorsal M:
<strong>Firewire to IDE bridge chips will need to be redesigned to take advantage. But at 200MBps, even ATA/100 will be hard pressed to max out IEEE1394b.</strong><hr></blockquote>
I wonder if Apple will ever make true FireWire drives.
[quote]Originally posted by smallM:
<strong>* there's only one PCI bus with 4 Slots</strong><hr></blockquote>
This wouldn't effect the RapidIO. as the PCI-X controller is also on-chip.
[quote]Originally posted by Outsider:
<strong>Basically a byte is 8 bits. So when you see something like 400Mb per second, divide by 8 and you get the byte translation: 50MB per second.</strong><hr></blockquote>
Yup.
[quote]Originally posted by vinney57:
<strong>the uptake on HD broadcasts in the US has been pretty dismal I understand;</strong><hr></blockquote>
This is a myth perpetrated by the lazy cable TV industry. don't believe it. <a href="http://www.cbandtv.com/"; target="_blank">C-Band TV</a> carries around 70 channels of domestic HDTV content. as well as granting access to hundreds of channels of foreign <a href="http://www.dvb.org/"; target="_blank">DVB</a> content. as usual. the US is in the dark technologically.
[quote]Originally posted by vinney57:
<strong>and anyway it costs too much.</strong><hr></blockquote>
<strong>Why the SDRam price jumped more than a double in the past few months, did they included some new features in the SDRam?</strong><hr></blockquote>
Because the RAM industry is greedy and evil. even I am starting to wonder if those rumors of subterranean DIMM silos in the midwest are true .
[quote]Originally posted by Programmer:
<strong>-AGP 8x would consume all the bandwidth.</strong><hr></blockquote>
AGP 8x ain't here yet.
[quote]Originally posted by Programmer:
<strong>-Motherboard based graphics chips could easily consume 4-8 GB/sec.</strong><hr></blockquote>
I wish! <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
[quote]Originally posted by Outsider:
<strong>Especially since future processors will have the memory controller totally off the main system bus with its own pipe to the CPU core.</strong><hr></blockquote>
Maybe in the FAR future. but not the G5. it has an onboard DDR 2700 controller.
[quote]Originally posted by MaCommentary:
<strong>The only interesting thing about the first link is the 17" PCTV (something that I have always thought that an iMac configuration should has to satisfy consumers w/o a lot of space such a the college market) implying that maybe when the iMac goes 17" that this will be available? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> </strong><hr></blockquote>
Me too! only why not throw in an IRDA port and a remote too. Apple could easily add this functionality(Remote and analog TV tuner) for around $25.
By the way. monitors with TV tuners in them are stupid.
Quote:
Originally posted by HOS:
<strong>Anyway, as per the older supposition, the assumption about the G5 is that it will adopt a built-in DDR controller, and thus move from a traditional shared bus approach (as in your CPU/memory controller/memory example above) to one where a CPU's local memory is on a "backside bus", to adopt an older expression.</strong><hr></blockquote>
Thus, in a multiple-CPU situation, each CPU gets its own local memory. However, in order for CPU 1 to access CPU 2's local memory, you use the RapidIO bus to do so.
Pardon the ASCII art:
local DDR RAM <--> CPU 1 <--> RIO bus <--> CPU 2 <--> local DDR RAM[/QB]
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
CPUs need their own dedicated SRAM cache in order to have somewhere to put large numbers of variables. and all CPUs as a whole(Also other components like graphics and sound chipsets. as I favor unified memory architectures ) require a large pool of equally accessible memory as well.
This is easily verifiable though. as anyone with a near-final prototype G5 could just pop open the case and see whether or not everything's crammed onto a daughterboard.
[quote]Originally posted by Programmer:
<strong>and I'm not sure which bus you are refering to. Certainly none of the ones discussed approach 10 GBytes/sec, and most exceed 10 Gbits/sec. The RapidIO bus discussed will be in the 2-4 GBytes/sec range.</strong><hr></blockquote>
RapidIO scales up to 8MBps. by "Discussed". do you mean the one that will actually be on the very first G5 when it ships?
Not that RAM speeds affect RapidIO or HyperTransport in any way. as the DDR has it's own dedicated frontside bus.
[quote]Originally posted by Programmer:
<strong>There is no DDR400 spec, and DDR333 is rare enough that I don't expect to see it in an Apple machine. DDR266 is what I'm hoping to see, which ought to deliver about 2 GBytes/sec (or close to it). DDR-II is still a ways off yet.
[QUOTE]Originally posted by Programmer:
[QB]I suppose there is an outside chance Apple could use RAMBus, but I wouldn't be too happy about that... although it would be fast</strong><hr></blockquote>
DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.
[quote]Originally posted by Programmer:
<strong>Its more expensi(...Snipped...)rease the base RAM configuration so that MacOSX runs faster.</strong><hr></blockquote>
This wouldn't matter. a 333Mhz DDR motherboard can use 266Mhz DDR modules just fine. Apple has to plan ahead. and they'll be competing against the new Rambus systems too. so Apple needs to look to the future.
[quote]Originally posted by Programmer:
<strong>The x16 is because many graphics boards use a 128-bit bus.</strong><hr></blockquote>
<strong>This kind of configuration doesn't really work for the main CPU, although with the advent of onchip memory controllers and per-CPU memory some of this will move to the motherboard. If Dorsal's description of the system is accurate then a dual G5 machine, could be built each with its own 128-bit bus to its own private memory, would effectively have a 2 x 128-bit memory bus. If the memory is kept very close to the processor(s) then it might be possible that the bus can be wider and/or faster than 128-bit 133 MHz double pumped, but I won't speculate on that.</strong><hr></blockquote>
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
[quote]Originally posted by Gamblor:
<strong>The cache is SRAM, main memory would be DDR SDRAM. Different memory design, basically. (SRAM is much, MUCH more expensive than DDR SDRAM...)</strong><hr></blockquote>
<strong>In addition to the 256-KB L2 cache built into the PowerPC G4 microprocessor, the 933-MHz and 1-GHz configurations also have an external level 3 (L3) backside cache. The L3 cache consists of 2 MB of DDR (double data rate) SDRAM. The ratio of the clock speeds of the microprocessor and cache is 4:1; the clock speeds are shown in Table 2-1.</strong><hr></blockquote>
Table 2-1 however is very confusing. as they list both clock frequency and data rate in Mhz.
I still think Apple should stick with a dedicated BSB hooked up to REAL SRAM. preferably running at the CPU's exact frequency(So as to deliver data whenever needed. even if this means sacrificing bus width). and leave the FSB alone.
[quote]Originally posted by Eskimo:
<strong>Micron and Samsung are the biggest proponents and as of yet the only companies which have stated they will produce and sell DDR I 400MHz memory. The others are waiting for DDR II.</strong><hr></blockquote>
400Mhz DDR is basically a temporery stopgap for the overclocker types that are too impatient to wait for DDR II.
[quote]Originally posted by Programmer:
<strong>The visual quality of DirectX and OpenGL is essentially the same because they run on the same hardware. Any perceived differences you see will generally be specific driver, application, or art issues.</strong><hr></blockquote>
Speaking of driver issues. do any of you think will nVidia/ATI ever enable FSAA, motion blur etc. on older Mac chipsets(GeForce2 MX for example?)? those jagged edges are really irritating.
[quote]Originally posted by Outsider:
<strong>Preview it like they previewed the g4. It's a technology demo to show developers what is in the pipeline and comsumers that the mac platform is going to grow with the rest of the industry. Same reason the preview future releases of OS X.</strong><hr></blockquote>
He's right. it would absolutely destroy Apple's PowerMac sales(Though one might debate over whether or not there's anything much left to destroy). but then it would also reassure Mac aficionados that the PowerMac will return to it's rightful spot soon. I suppose that's just a tradeoff only Jobs could decide on.
[quote]Originally posted by mattyj:
<strong>with a dedicated processor for altivec.</strong><hr></blockquote>
You mean like the external FPUs on the old 68ks? that would've been a pretty cool way for Apple to introduce AltiVec without forcing the issue. and it might even be a nifty option on G3 based iBooks(Most of all. I wish they'd bring back the Duo ). but I can't imagine it adding anything other than latency on Apple's "Big" CPU.
[quote]Originally posted by AirSluf:
<strong>The OS would need to be recompiled with an appropriate compiler to use 64-bitness. Rumors of the G5 say it will handle existing 32-bit code transparently with no changes or speed hit.</strong><hr></blockquote>
Judging from IBM's POWER 32-bit to 64-bit transition, SGI's MIPS 16-bit to 32-bit to 64-bit transition, ARM's ARM 16-bit to 32-bit transition, DEC's Alpha 32-bit to 64-bit transition and Motorola's 68xxx 24-bit to 32-bit transition. 32-bit PPC code should run with no speed hit whatsoever on a 64-bit G5.
Apple could sell 64-bit G5s with 32-bit OS X(Mac OS <9.x, BeOS, BSD, Linux etc. would also work fine too) installed. and use it as a way of "Selling potential" like the way the G4's AltiVec and multiprocessing capabilities were bought by customers who knew that it wouldn't benefit them at all until OS X came to fruition.
[quote]Originally posted by tiramisubomb:
<strong>Perhaps Apple should just call .13 Apollo a G5. It makes more sense.</strong><hr></blockquote>
Apple would get flambéed by the Mac community if they tried to pull a dirty trick like that.
I won't call it a G5 unless it says "85xx" somewhere on it. and I doubt most others will either.
Comments
The first chapter descibed the MPC7400 and included many technical information, this was definately the less interesting part of the document. The second chapter then described some of the problems of the architecture. Apparently the original design was supposed to reach 1 ghz at some point, but the Motorola had serious problems with pipeline related circuits that produced too much heat. If you believe the document Motorola already knew in mid 1999 that the MPC7400 could never exceed 700 mhz (that's the clockspeed mentioned in the document). The document also notices that only very few processors on the wafers were capable to run at speeds higher than 500 mhz, maybe that's the reason why Apple was stuck at 500 mhz for such a long time.
The second chapter then described MPC7400 successor plans with a 7 stage pipelines, 256 kb L2 on-die cache and a 2 mb external L3 cache (that's more or less what we have now with the MPC745x). There was very detailed information about the MPC745x, and that made me wonder a bit because the document was so old (January 2000, as stated above). I know there is no proof for it, but considering the detailed information about current G4 processors I found in this document makes me think that the people who wrote this had some real insight in Motorolas technology.
And now to the most interesting part, the notes about the G4 successor - the G5. Unfortunately I must tell you that there was no entire chapter with many details about the MPC7500, it was only attached as appendix (one page). Here's more or less what I found there:
The G5 was planned for 2002. The basic design was a 64 bit processor featuring a new on-chip bus system and 512 kb on-die L2 cache. The design was intended to be modular, and a version with 32 bit execution units and 256 kb L2 cache was planned too. This already means that there were plans for two G5 processors, a 64 bit version for high-end workstations and servers and a 32 bit version for consumer and portable machines. There was no mention of an external L3 cache or AltiVec, although it said that the G5 would be based on the G4 which makes me think that at least AltiVec should be part of the design. Apparently the G5's block diagram should be very similar to the G4's, and there was no mention of enhanced execution units (except for the fact they should be 64 bits). Unfortunately the comments about the intended G5 design were very vague, but apparently the G5 was planned to use two G4-like cores with a new pipeline.
There was also a paragraph about the planned production process, this one was very clear indeed: 0.10 with speeds starting at 2 ghz in 2002.
Now that's all about what the document said, the following is only speculation...
If I remember well the Motorola roadmap said 2+ ghz some time ago, and now they have changed it to 800 mhz - 2 ghz. This could be related to the fact that we're still far from 0.10, if the G5 should be close now a 0.13 process should be much more likely. 800-2000 mhz would not be that improbable then. I don't think a G5 will be made using the current 0.18 process, but I would not be surprised if we would get 0.13 G4's within the next few months. The current SOI MPC7455 should reach 1.2 ghz, but I don't know why they're not shipping yet, maybe they're not available in high quantities, or maybe Motorola still has some trouble with SOI. An SOI MPC7455 using a 0.13 process should be capable to reach clock speeds of about 1.5 ghz, and I think this could be possible in mid 2002.
Maybe the G5 is ready, and maybe it will be shipping as soon as Motorola gets the 0.13 process ready for quantity production. I really think they had enough time to realize the G5, as the technology was already there (Motorola and (especially) IBM have already realized 64 bit PPC designs). A G5 featuring a 10 stage pipeline using a 0.13 process should reach clock speeds of 1.5 - 2.0 ghz (32 bit version, the 64 bit version should produce more heat).
So that's all I know for now, I will now try to find some detailed information about the G5 - I already tried this, but it's really hard to get any info which makes me think that Apple has something to do with it...
[ 04-19-2002: Message edited by: haderach ]</p>
If only.
This is interesting considering it has been said elsewhere Apple is moving to IBM as its sole supplier... Moto got the design done but can't fab it, IBM's got the big fabs ready for it...
Which fits in well with a rumoured quote by Steve Jobs:
"It'll be great in two years time when we don't have to F***ing use you anymore." (In ref; to Moto'...)
I think it's fair to say that Moto' is a company in crisis and they are struggling. They're bleeding losses.
The logic of the aboves quote(s) is not lost on me...
Lemon Bon Bon.
--------------------------------------------------------
Motorola announces 0.13-micron fabrication process
by David Read,
April 10, 2001, 7:00 am ET
Yesterday, Motorola announced its new HiPerMOS7 (Seventh Generation High Performance Metal Oxide Semiconductor -- called HiP7) manufacturing process that will allow future processors from Motorola, including the next PowerPCs, to run faster, use less power, generate less heat and be less expensive than ever before. This new fabrication process will be the first to use 0.13-micron lithography and SOI (Silicon on Insulator) technology along with copper interconnects.
"With HiPerMOS7, Motorola has tried to implement parallel design efforts with all of Motorola's future microprocessors," said Suresh Venkatesan, Motorola's HiP7 Process Technology Manager. "Initial products using SOI and HiP7 will address the embedded and infrastructure markets, with Motorola's PowerPC microprocessors adopting these technologies early next year." Motorola hopes that the smaller size of a processor manufactured with the new process will allow its embedded processors to drop significantly in price and increase in functionality. Venkatesan stresses that HiP7 will migrate to the PowerPC portfolio.
Currently, Motorola uses a 0.18-micron lithography process to manufacture Motorola 7450s, the G4s currently used in Apple's highest end systems. By moving to a far smaller 0.13-micron lithography process, Motorola's new processors will be able to use less energy per transistor, and have more transistors per processor. "Speed and dynamic power consumption are a function of voltage and frequency," said Venkatesan. "All things remaining equal, a processor manufactured using the 0.13-micron fabrication process could see a 50 percent power savings over a similar processor made using a 0.18-micron fabrication process."
That's not all. Because of the lowered power consumption of processors manufactured with the new process, it will be possible for Motorola to ramp up its processor's frequencies. This, coupled with Motorola's SOI technology which allows individual transistors to operate more quickly and efficiently, should allow Motorola to reach the goals that it outlined at last summer's Microprocessor Forum for its GHz+ G4 Apollo.
Mike Mendacino, Motorola's SOI Technology Manager, said that future PowerPC processors created using the 0.13-micron manufacturing process could have larger on-die L2 caches. "With more transistors on a given area, one could logically conclude that we could add more cache if the processor's performance and price worked out in a larger cache's favor," said Mendacino. He also suggested that, given Motorola's history, a larger on-die cache is a logical progression in the PowerPC's development.
Venkatesan also said that Motorola is skipping the 0.15-micron manufacturing process. This may result in Motorola leapfrogging their semiconductor competitors, many of whom have recently begun shipping processor products using a 0.15-micron lithography process -- Nvidia's GeForce3 being a high-profile example. Nevertheless, other major semiconductor manufacturers have announced their own twist of a 0.13-micron manufacturing process. For example, rival processor manufacturer Intel last week announced that it had successfully manufactured its first .13-micron processors on a larger wafer.
Motorola is currently sampling embedded processors fabricated using the 0.13-micron process, which it intends to begin shipping in volume in the second quarter of this year. Motorola also will be showing off its new technology at the Embedded systems conference this week in San Francisco
[ 04-21-2002: Message edited by: MacGregor ]</p>
<strong>The best information that was provided on future road map was released on MacCentral back in April last year when Motorola released 0.13 micron process. The G4 based 7470 and 7460 seems very logical as Motorola may even ship them in the 2Q02. There were many predictions that next gen of SOI .13 Apollo will borrow features from the much rumored G5. Larger L2 cache and higher clock frequency will be the key changes, and very likely the addition of DDR support to increase bandwidth. The G5, on the other hand will only differ by a faster system bus and longer pipelines. It becomes harder to make sense out of all the G5 rumors. It seems like G5 is just another P4.</strong><hr></blockquote>
Using the 0.13 process with the G4/Apollo should allow to implement a larger L2 cache (512kb) and run higher clock rates (up to 1.5 ghz). DDR would be nice too. I hope to see this for MWNY.
The difference between the G4 and the G5 will be the fact the the G5 will match the Book E specifications while the G4 will not.
<a href="http://maccentral.macworld.com/news/0204/22.ibmmot.php"; target="_blank">http://maccentral.macworld.com/news/0204/22.ibmmot.php</a>;
So. Moto' will be the sole supplier.
Yeesh.
Lemon Bon Bon
imo, I think that OSX server should run 64-bit saving the 64-bit stations for servers and workstation-like uses.
Has this been proven, or is this just more MOSR/TheRegister **CONFIRMED** horseshit?
Using the 0.13 process with the G4/Apollo should allow to implement a larger L2 cache (512kb) and run higher clock rates (up to 1.5 ghz). DDR would be nice too. I hope to see this for MWNY.The difference between the G4 and the G5 will be the fact the the G5 will match the Book E specifications while the G4 will not.
-------------------------------------------------
So the difference is mainly larger cache and faster bus, and may be a few more pipelines. As with the Book E compliant which calls for compatibility between IBM PPC and Motorola PPC should mean very little for Apple. Perhaps Apple should just call .13 Apollo a G5. It makes more sense.
<strong>One of the machines is built in a G4 case with a smaller motherboard.</strong><hr></blockquote>
Noooooo :eek: ! I want all six slots back(I'd really like it if Apple were to surprise us with a native RapidIO graphics chipset
[quote]Originally posted by Dorsal M:
<strong>there already is a crimp on upgraders. I have yet to see a non-Apple 500MHz+ upgrade for any Apple machine. Although this may be because of minimum quantity bought is too high now.</strong><hr></blockquote>
Yeah. and this is really bad for the Mac too. as it greatly limits the lifetime value of a given system. if this is the result of Apple's greed. they should stop being so mean. and if this is the result of Motorola not making enough G4s. they should hire more of those korean/taiwanese fabs and increase volume to meet demand(Heck. they should do this anyways. Apple needs to increase channel saturation a LOT).
[quote]Originally posted by Dorsal M:
<strong>main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.</strong><hr></blockquote>
Right on.
[quote]Originally posted by Dorsal M:
<strong>Firewire to IDE bridge chips will need to be redesigned to take advantage. But at 200MBps, even ATA/100 will be hard pressed to max out IEEE1394b.</strong><hr></blockquote>
I wonder if Apple will ever make true FireWire drives.
[quote]Originally posted by smallM:
<strong>* there's only one PCI bus with 4 Slots</strong><hr></blockquote>
This wouldn't effect the RapidIO. as the PCI-X controller is also on-chip.
[quote]Originally posted by Outsider:
<strong>Basically a byte is 8 bits. So when you see something like 400Mb per second, divide by 8 and you get the byte translation: 50MB per second.</strong><hr></blockquote>
Yup.
[quote]Originally posted by vinney57:
<strong>the uptake on HD broadcasts in the US has been pretty dismal I understand;</strong><hr></blockquote>
This is a myth perpetrated by the lazy cable TV industry. don't believe it. <a href="http://www.cbandtv.com/"; target="_blank">C-Band TV</a> carries around 70 channels of domestic HDTV content. as well as granting access to hundreds of channels of foreign <a href="http://www.dvb.org/"; target="_blank">DVB</a> content. as usual. the US is in the dark technologically.
[quote]Originally posted by vinney57:
<strong>and anyway it costs too much.</strong><hr></blockquote>
Not so. wintel owners have been able to buy $100-$300 HDTV tuners like <a href="http://www.hauppauge.com/html/products.htm#digital"; target="_blank">this</a> and <a href="http://www.pentamedia.com/english/products/pentacable.htm"; target="_blank">this</a> for over three years now.
[quote]Originally posted by ihxo:
<strong>Why the SDRam price jumped more than a double in the past few months, did they included some new features in the SDRam?</strong><hr></blockquote>
Because the RAM industry is greedy and evil. even I am starting to wonder if those rumors of subterranean DIMM silos in the midwest are true
[quote]Originally posted by Programmer:
<strong>-AGP 8x would consume all the bandwidth.</strong><hr></blockquote>
AGP 8x ain't here yet.
[quote]Originally posted by Programmer:
<strong>-Motherboard based graphics chips could easily consume 4-8 GB/sec.</strong><hr></blockquote>
I wish! <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
[quote]Originally posted by Outsider:
<strong>Especially since future processors will have the memory controller totally off the main system bus with its own pipe to the CPU core.</strong><hr></blockquote>
Maybe in the FAR future. but not the G5. it has an onboard DDR 2700 controller.
[quote]Originally posted by MaCommentary:
<strong>The only interesting thing about the first link is the 17" PCTV (something that I have always thought that an iMac configuration should has to satisfy consumers w/o a lot of space such a the college market) implying that maybe when the iMac goes 17" that this will be available? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> </strong><hr></blockquote>
Me too! only why not throw in an IRDA port and a remote too. Apple could easily add this functionality(Remote and analog TV tuner) for around $25.
By the way. monitors with TV tuners in them are stupid.
Originally posted by HOS:
<strong>Anyway, as per the older supposition, the assumption about the G5 is that it will adopt a built-in DDR controller, and thus move from a traditional shared bus approach (as in your CPU/memory controller/memory example above) to one where a CPU's local memory is on a "backside bus", to adopt an older expression.</strong><hr></blockquote>
Thus, in a multiple-CPU situation, each CPU gets its own local memory. However, in order for CPU 1 to access CPU 2's local memory, you use the RapidIO bus to do so.
Pardon the ASCII art:
local DDR RAM <--> CPU 1 <--> RIO bus <--> CPU 2 <--> local DDR RAM[/QB]
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
CPUs need their own dedicated SRAM cache in order to have somewhere to put large numbers of variables. and all CPUs as a whole(Also other components like graphics and sound chipsets. as I favor unified memory architectures
This is easily verifiable though. as anyone with a near-final prototype G5 could just pop open the case and see whether or not everything's crammed onto a daughterboard.
[quote]Originally posted by Programmer:
<strong>and I'm not sure which bus you are refering to. Certainly none of the ones discussed approach 10 GBytes/sec, and most exceed 10 Gbits/sec. The RapidIO bus discussed will be in the 2-4 GBytes/sec range.</strong><hr></blockquote>
RapidIO scales up to 8MBps. by "Discussed". do you mean the one that will actually be on the very first G5 when it ships?
[quote]Originally posted by Programmer:
<strong>HyperTrans(...SNIPPED...)eds.</strong><hr></blockquote>
Not that RAM speeds affect RapidIO or HyperTransport in any way. as the DDR has it's own dedicated frontside bus.
[quote]Originally posted by Programmer:
<strong>There is no DDR400 spec, and DDR333 is rare enough that I don't expect to see it in an Apple machine. DDR266 is what I'm hoping to see, which ought to deliver about 2 GBytes/sec (or close to it). DDR-II is still a ways off yet.
[QUOTE]Originally posted by Programmer:
[QB]I suppose there is an outside chance Apple could use RAMBus, but I wouldn't be too happy about that... although it would be fast</strong><hr></blockquote>
DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.
[quote]Originally posted by Programmer:
<strong>Its more expensi(...Snipped...)rease the base RAM configuration so that MacOSX runs faster.</strong><hr></blockquote>
This wouldn't matter. a 333Mhz DDR motherboard can use 266Mhz DDR modules just fine. Apple has to plan ahead. and they'll be competing against the new Rambus systems too. so Apple needs to look to the future.
[quote]Originally posted by Programmer:
<strong>The x16 is because many graphics boards use a 128-bit bus.</strong><hr></blockquote>
So what? many CPUs use a 64-bit bus and 32-bit addressing. but 1 <a href="http://www.webopedia.com/TERM/B/byte.html"; target="_blank">byte</a> still equals 8 <a href="http://www.webopedia.com/TERM/B/bit.html"; target="_blank">bits</a> whenever you're referring to hard disks, RAM, throughput etc.
Let's just keep things simple and stick with 8-bit bytes for measurement. to convert from <a href="http://www.webopedia.com/TERM/M/Mbps.html"; target="_blank">Mbps</a> to <a href="http://www.webopedia.com/TERM/M/MBps_megabytes.html"; target="_blank">MBps</a>. divide by 8. not 16.
For more clarification on DDR, Rambus and how all this fits in with the G5. read the lower parts of <a href="http://forums.appleinsider.com/cgi-bin/ultimatebb.cgi?ubb=get_topic&f=1&t=001542"; target="_blank">this thread</a>.
[quote]Originally posted by Programmer:
<strong>This kind of configuration doesn't really work for the main CPU, although with the advent of onchip memory controllers and per-CPU memory some of this will move to the motherboard. If Dorsal's description of the system is accurate then a dual G5 machine, could be built each with its own 128-bit bus to its own private memory, would effectively have a 2 x 128-bit memory bus. If the memory is kept very close to the processor(s) then it might be possible that the bus can be wider and/or faster than 128-bit 133 MHz double pumped, but I won't speculate on that.</strong><hr></blockquote>
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
[quote]Originally posted by Gamblor:
<strong>The cache is SRAM, main memory would be DDR SDRAM. Different memory design, basically. (SRAM is much, MUCH more expensive than DDR SDRAM...)</strong><hr></blockquote>
The cache isn't SRAM.
[quote]Originally posted at <a href="http://developer.apple.com/techpubs/hardware/Developer_Notes/Macintosh_CPUs-G4/PowerMacG4/2Architecture/Cache_Memory.html"; target="_blank">Apple's G4 developer page</a>:
<strong>In addition to the 256-KB L2 cache built into the PowerPC G4 microprocessor, the 933-MHz and 1-GHz configurations also have an external level 3 (L3) backside cache. The L3 cache consists of 2 MB of DDR (double data rate) SDRAM. The ratio of the clock speeds of the microprocessor and cache is 4:1; the clock speeds are shown in Table 2-1.</strong><hr></blockquote>
Table 2-1 however is very confusing. as they list both clock frequency and data rate in Mhz.
I still think Apple should stick with a dedicated BSB hooked up to REAL SRAM. preferably running at the CPU's exact frequency(So as to deliver data whenever needed. even if this means sacrificing bus width). and leave the FSB alone.
[quote]Originally posted by Eskimo:
<strong>Micron and Samsung are the biggest proponents and as of yet the only companies which have stated they will produce and sell DDR I 400MHz memory. The others are waiting for DDR II.</strong><hr></blockquote>
400Mhz DDR is basically a temporery stopgap for the overclocker types that are too impatient to wait for DDR II.
[quote]Originally posted by Programmer:
<strong>The visual quality of DirectX and OpenGL is essentially the same because they run on the same hardware. Any perceived differences you see will generally be specific driver, application, or art issues.</strong><hr></blockquote>
Speaking of driver issues. do any of you think will nVidia/ATI ever enable FSAA, motion blur etc. on older Mac chipsets(GeForce2 MX for example?)? those jagged edges are really irritating.
[quote]Originally posted by Outsider:
<strong>Preview it like they previewed the g4. It's a technology demo to show developers what is in the pipeline and comsumers that the mac platform is going to grow with the rest of the industry. Same reason the preview future releases of OS X.</strong><hr></blockquote>
He's right. it would absolutely destroy Apple's PowerMac sales(Though one might debate over whether or not there's anything much left to destroy). but then it would also reassure Mac aficionados that the PowerMac will return to it's rightful spot soon. I suppose that's just a tradeoff only Jobs could decide on.
[quote]Originally posted by mattyj:
<strong>with a dedicated processor for altivec.</strong><hr></blockquote>
You mean like the external FPUs on the old 68ks? that would've been a pretty cool way for Apple to introduce AltiVec without forcing the issue. and it might even be a nifty option on G3 based iBooks(Most of all. I wish they'd bring back the Duo
[quote]Originally posted by AirSluf:
<strong>The OS would need to be recompiled with an appropriate compiler to use 64-bitness. Rumors of the G5 say it will handle existing 32-bit code transparently with no changes or speed hit.</strong><hr></blockquote>
Judging from IBM's POWER 32-bit to 64-bit transition, SGI's MIPS 16-bit to 32-bit to 64-bit transition, ARM's ARM 16-bit to 32-bit transition, DEC's Alpha 32-bit to 64-bit transition and Motorola's 68xxx 24-bit to 32-bit transition. 32-bit PPC code should run with no speed hit whatsoever on a 64-bit G5.
Apple could sell 64-bit G5s with 32-bit OS X(Mac OS <9.x, BeOS, BSD, Linux etc. would also work fine too) installed. and use it as a way of "Selling potential" like the way the G4's AltiVec and multiprocessing capabilities were bought by customers who knew that it wouldn't benefit them at all until OS X came to fruition.
[quote]Originally posted by tiramisubomb:
<strong>Perhaps Apple should just call .13 Apollo a G5. It makes more sense.</strong><hr></blockquote>
Apple would get flambéed by the Mac community if they tried to pull a dirty trick like that.
I won't call it a G5 unless it says "85xx" somewhere on it. and I doubt most others will either.
Eric,
either you know something most people don't or you sound just very confident. please elaborate...